mirror of https://github.com/openXC7/prjxray.git
FUZZER - DSP - Refactor
Refactor the DSP Python scripts to be easier to manage. Use JSON instead of CSV. Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
This commit is contained in:
parent
596bb27e3b
commit
e0fb0c0cb1
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@ -1,154 +1,123 @@
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#!/usr/bin/env python3
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from prjxray.segmaker import Segmaker
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import csv
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from prjxray.verilog import to_int
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from prjxray.verilog import quote
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import json
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segmk = Segmaker("design.bits", verbose=True)
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def bits_in(value, width):
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bits = []
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for i in range(width):
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bits.append(value & 1)
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value >>= 1
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return bits
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print("Loading tags")
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with open('params.csv', 'r') as f:
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for d in csv.DictReader(f):
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dsp = "DSP_0" if d['SITE'][-1] in "02468" else "DSP_1"
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acascreg = int(d['ACASCREG'])
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segmk.add_site_tag(
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d['SITE'], "%s.ZACASCREG[0]" % (dsp), ~(acascreg >> 0) & 1)
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segmk.add_site_tag(
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d['SITE'], "%s.ZACASCREG[1]" % (dsp), ~(acascreg >> 1) & 1)
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def add(segmk, site, dsp, tag, bit, value, invert):
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tag = dsp + '.' + '%s' % ('Z' if invert else '') + tag + '[%u]' % bit
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value = (~value if invert else value)
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value >>= bit
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return segmk.add_site_tag(site, tag, value & 1)
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adreg = int(d['ADREG'])
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segmk.add_site_tag(d['SITE'], "%s.ADREG[0]" % (dsp), adreg & 1)
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alumodereg = int(d['ALUMODEREG'])
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segmk.add_site_tag(
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d['SITE'], "%s.ZALUMODEREG[0]" % (dsp), ~alumodereg & 1)
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def run():
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segmk = Segmaker("design.bits", verbose=True)
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areg = int(d['AREG'])
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segmk.add_site_tag(d['SITE'], "%s.ZAREG[0]" % (dsp), ~(areg >> 0) & 1)
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segmk.add_site_tag(d['SITE'], "%s.ZAREG[1]" % (dsp), ~(areg >> 1) & 1)
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print("Loading tags")
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with open('params.json', 'r') as fp:
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data = json.load(fp)
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bcascreg = int(d['BCASCREG'])
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segmk.add_site_tag(
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d['SITE'], "%s.ZBCASCREG[0]" % (dsp), ~(bcascreg >> 0) & 1)
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segmk.add_site_tag(
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d['SITE'], "%s.ZBCASCREG[1]" % (dsp), ~(bcascreg >> 1) & 1)
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for params in data['instances']:
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dsp = "DSP_0" if params['SITE'][-1] in "02468" else "DSP_1"
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site = params['SITE']
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breg = int(d['BREG'])
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segmk.add_site_tag(d['SITE'], "%s.ZBREG[0]" % (dsp), ~(breg >> 0) & 1)
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segmk.add_site_tag(d['SITE'], "%s.ZBREG[1]" % (dsp), ~(breg >> 1) & 1)
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add(segmk, site, dsp, 'ADREG', 0, to_int(params['ADREG']), 0)
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add(segmk, site, dsp, 'ALUMODEREG', 0, to_int(params['ALUMODEREG']), 1)
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carryinreg = int(d['CARRYINREG'])
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segmk.add_site_tag(d['SITE'], "%s.ZCARRYINREG[0]" % (dsp), ~carryinreg)
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for i in range(2):
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add(segmk, site, dsp, 'AREG', i, to_int(params['AREG']), 1)
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carryinselreg = int(d['CARRYINSELREG'])
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segmk.add_site_tag(
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d['SITE'], "%s.ZCARRYINSELREG[0]" % (dsp), ~carryinselreg)
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for i in range(2):
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add(segmk, site, dsp, 'ACASCREG', i, to_int(params['ACASCREG']), 1)
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creg = int(d['CREG'])
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segmk.add_site_tag(d['SITE'], "%s.ZCREG[0]" % (dsp), ~creg)
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for i in range(2):
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add(segmk, site, dsp, 'BREG', i, to_int(params['BREG']), 1)
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dreg = int(d['DREG'])
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segmk.add_site_tag(d['SITE'], "%s.DREG[0]" % (dsp), dreg)
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for i in range(2):
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add(segmk, site, dsp, 'BCASCREG', i, to_int(params['BCASCREG']), 1)
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inmodereg = int(d['INMODEREG'])
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segmk.add_site_tag(d['SITE'], "%s.ZINMODEREG[0]" % (dsp), ~inmodereg)
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add(segmk, site, dsp, 'CARRYINREG', 0, to_int(params['CARRYINREG']), 1)
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add(segmk, site, dsp, 'CARRYINSELREG', 0, to_int(params['CARRYINSELREG']), 1)
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add(segmk, site, dsp, 'CREG', 0, to_int(params['CREG']), 1)
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mreg = int(d['MREG'])
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segmk.add_site_tag(d['SITE'], "%s.ZMREG[0]" % (dsp), ~mreg)
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add(segmk, site, dsp, 'DREG', 0, to_int(params['DREG']), 0)
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add(segmk, site, dsp, 'INMODEREG', 0, to_int(params['INMODEREG']), 1)
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add(segmk, site, dsp, 'OPMODEREG', 0, to_int(params['OPMODEREG']), 1)
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add(segmk, site, dsp, 'PREG', 0, to_int(params['PREG']), 1)
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opmodereg = int(d['OPMODEREG'])
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segmk.add_site_tag(d['SITE'], "%s.ZOPMODEREG[0]" % (dsp), ~opmodereg)
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INPUT = {}
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INPUT[quote('DIRECT')] = 0
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INPUT[quote('CASCADE')] = 1
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preg = int(d['PREG'])
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segmk.add_site_tag(d['SITE'], "%s.ZPREG[0]" % (dsp), ~preg)
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add(segmk, site, dsp, 'A_INPUT', 0, INPUT[params['A_INPUT']], 0)
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add(segmk, site, dsp, 'B_INPUT', 0, INPUT[params['B_INPUT']], 0)
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a_input = str(d['A_INPUT'])
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segmk.add_site_tag(
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d['SITE'], "%s.ZA_INPUT[0]" % (dsp),
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(0 if a_input == "DIRECT" else 1))
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BOOL = {}
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BOOL[quote('FALSE')] = 0
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BOOL[quote('TRUE')] = 1
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b_input = str(d['B_INPUT'])
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segmk.add_site_tag(
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d['SITE'], "%s.ZB_INPUT[0]" % (dsp),
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(0 if b_input == "DIRECT" else 1))
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add(segmk, site, dsp, 'USE_DPORT', 0, BOOL[params['USE_DPORT']], 0)
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use_dport = str(d['USE_DPORT'])
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segmk.add_site_tag(
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d['SITE'], "%s.USE_DPORT[0]" % (dsp),
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(0 if use_dport == "FALSE" else 1))
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SIMD = {}
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SIMD[quote('ONE48')] = 0
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SIMD[quote('TWO24')] = 1
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SIMD[quote('FOUR12')] = 2
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use_mult = str(d['USE_MULT'])
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if use_mult == "NONE":
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segmk.add_site_tag(d['SITE'], "%s.USE_MULT[0]" % (dsp), 0)
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segmk.add_site_tag(d['SITE'], "%s.ZUSE_MULT[1]" % (dsp), ~0)
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elif use_mult == "MULTIPLY":
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segmk.add_site_tag(d['SITE'], "%s.USE_MULT[0]" % (dsp), 0)
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segmk.add_site_tag(d['SITE'], "%s.ZUSE_MULT[1]" % (dsp), ~1)
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elif use_mult == "DYNAMIC":
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segmk.add_site_tag(d['SITE'], "%s.USE_MULT[0]" % (dsp), 1)
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segmk.add_site_tag(d['SITE'], "%s.ZUSE_MULT[1]" % (dsp), ~1)
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for i in range(2):
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add(segmk, site, dsp, 'USE_SIMD', i, SIMD[params['USE_SIMD']], 0)
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use_simd = str(d['USE_SIMD'])
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if use_simd == "ONE48":
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segmk.add_site_tag(d['SITE'], "%s.USE_SIMD[0]" % (dsp), 0)
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segmk.add_site_tag(d['SITE'], "%s.USE_SIMD[1]" % (dsp), 0)
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elif use_simd == "TWO24":
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segmk.add_site_tag(d['SITE'], "%s.USE_SIMD[0]" % (dsp), 0)
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segmk.add_site_tag(d['SITE'], "%s.USE_SIMD[1]" % (dsp), 1)
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elif use_simd == "FOUR12":
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segmk.add_site_tag(d['SITE'], "%s.USE_SIMD[0]" % (dsp), 1)
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segmk.add_site_tag(d['SITE'], "%s.USE_SIMD[1]" % (dsp), 1)
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MULT = {}
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MULT[quote('NONE')] = 0
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MULT[quote('MULTIPLY')] = 1
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MULT[quote('DYNAMIC')] = 2
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autoreset_patdet = str(d['AUTORESET_PATDET'])
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if autoreset_patdet == "RESET_MATCH":
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segmk.add_site_tag(d['SITE'], "%s.AUTO_RESET_PATDET[0]" % (dsp), 0)
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segmk.add_site_tag(
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d['SITE'], "%s.ZAUTO_RESET_PATDET[1]" % (dsp), 1)
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elif autoreset_patdet == "NO_RESET":
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segmk.add_site_tag(d['SITE'], "%s.AUTO_RESET_PATDET[0]" % (dsp), 0)
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segmk.add_site_tag(
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d['SITE'], "%s.ZAUTO_RESET_PATDET[1]" % (dsp), 0)
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elif autoreset_patdet == "RESET_NOT_MATCH":
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segmk.add_site_tag(d['SITE'], "%s.AUTO_RESET_PATDET[0]" % (dsp), 1)
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segmk.add_site_tag(
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d['SITE'], "%s.ZAUTO_RESET_PATDET[1]" % (dsp), 1)
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for i in range(2):
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add(segmk, site, dsp, 'USE_MULT', i, MULT[params['USE_MULT']], 0)
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mask = int(d['MASK'])
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pattern = int(d['PATTERN'])
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add(segmk, site, dsp, 'MREG', 0, to_int(params['MREG']), 1)
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AUTORESET = {}
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AUTORESET[quote('NO_RESET')] = 0
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AUTORESET[quote('RESET_NOT_MATCH')] = 1
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AUTORESET[quote('RESET_MATCH')] = 2
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add(segmk, site, dsp, 'AUTORESET_PATDET', 0, AUTORESET[params['AUTORESET_PATDET']], 0)
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add(segmk, site, dsp, 'AUTORESET_PATDET', 1, AUTORESET[params['AUTORESET_PATDET']], 1)
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for i in range(48):
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segmk.add_site_tag(
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d['SITE'], "%s.MASK[%d]" % (dsp, i), (mask >> i) & 1)
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segmk.add_site_tag(
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d['SITE'], "%s.PATTERN[%d]" % (dsp, i), (pattern >> i) & 1)
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add(segmk, site, dsp, 'MASK', i, to_int(params['MASK']), 0)
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sel_mask = str(d['SEL_MASK'])
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if sel_mask == "MASK":
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segmk.add_site_tag(d['SITE'], "%s.SEL_MASK[0]" % (dsp), 0)
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segmk.add_site_tag(d['SITE'], "%s.SEL_MASK[1]" % (dsp), 0)
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segmk.add_site_tag(d['SITE'], "%s.SEL_MASK[2]" % (dsp), 0)
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elif sel_mask == "C":
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segmk.add_site_tag(d['SITE'], "%s.SEL_MASK[0]" % (dsp), 0)
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segmk.add_site_tag(d['SITE'], "%s.SEL_MASK[1]" % (dsp), 1)
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segmk.add_site_tag(d['SITE'], "%s.SEL_MASK[2]" % (dsp), 0)
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elif sel_mask == "ROUNDING_MODE1":
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segmk.add_site_tag(d['SITE'], "%s.SEL_MASK[0]" % (dsp), 1)
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segmk.add_site_tag(d['SITE'], "%s.SEL_MASK[1]" % (dsp), 1)
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segmk.add_site_tag(d['SITE'], "%s.SEL_MASK[2]" % (dsp), 0)
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elif sel_mask == "ROUNDING_MODE2":
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segmk.add_site_tag(d['SITE'], "%s.SEL_MASK[0]" % (dsp), 0)
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segmk.add_site_tag(d['SITE'], "%s.SEL_MASK[1]" % (dsp), 0)
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segmk.add_site_tag(d['SITE'], "%s.SEL_MASK[2]" % (dsp), 1)
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for i in range(48):
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add(segmk, site, dsp, 'PATTERN', i, to_int(params['PATTERN']), 0)
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sel_pattern = str(d['SEL_PATTERN'])
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segmk.add_site_tag(
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d['SITE'], "%s.ZSEL_PATTERN[0]" % (dsp),
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(0 if sel_pattern == "PATTERN" else 1))
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SEL_MASK = {}
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SEL_MASK[quote('MASK')] = 0
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SEL_MASK[quote('C')] = 1
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SEL_MASK[quote('ROUNDING_MODE1')] = 2
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SEL_MASK[quote('ROUNDING_MODE2')] = 3
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use_pattern_detect = str(d['USE_PATTERN_DETECT'])
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segmk.add_site_tag(
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d['SITE'], "%s.USE_PATTERN_DETECT[0]" % (dsp),
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(0 if use_pattern_detect == "PATDET" else 1))
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for i in range(2):
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add(segmk, site, dsp, 'SEL_MASK', i, SEL_MASK[params['SEL_MASK']], 0)
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segmk.compile()
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segmk.write()
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USE_PATTERN_DETECT = {}
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USE_PATTERN_DETECT[quote('NO_PATDET')] = 0
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USE_PATTERN_DETECT[quote('PATDET')] = 1
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add(segmk, site, dsp, 'USE_PATTERN_DETECT', 0, USE_PATTERN_DETECT[params['USE_PATTERN_DETECT']], 0)
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segmk.compile()
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segmk.write()
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if __name__ == '__main__':
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run()
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@ -1,8 +1,9 @@
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import os
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import random
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import csv
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import json
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import verilog
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from prjxray.db import Database
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@ -29,146 +30,68 @@ def fuzz(*args):
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def run():
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# Attributes list:
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# Attribute name
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# Verilog parameter value prefix
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# Arguments to `fuzz`
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# Verilog parameter value suffix
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attributes = []
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attributes.append(('ADREG', '', (0, 1), ''))
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attributes.append(('ALUMODEREG', '', (0, 1), ''))
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# AREG/BREG requires inputs to be connected when configured with a value of
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# 2, contstraining to 0 and 1 for now.
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attributes.append(('AREG', '', (0, 1), ''))
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attributes.append(('BREG', '', (0, 1), ''))
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attributes.append(('CARRYINREG', '', (0, 1), ''))
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attributes.append(('CARRYINSELREG', '', (0, 1), ''))
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attributes.append(('CREG', '', (0, 1), ''))
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attributes.append(('DREG', '', (0, 1), ''))
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attributes.append(('INMODEREG', '', (0, 1), ''))
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attributes.append(('OPMODEREG', '', (0, 1), ''))
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attributes.append(('PREG', '', (0, 1), ''))
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attributes.append(('A_INPUT', '"', ('DIRECT', 'CASCADE'), '"'))
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attributes.append(('B_INPUT', '"', ('DIRECT', 'CASCADE'), '"'))
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attributes.append(('USE_DPORT', '"', ('TRUE', 'FALSE'), '"'))
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attributes.append(('USE_SIMD', '"', ('ONE48', 'TWO24', 'FOUR12'), '"'))
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attributes.append(
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(
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'AUTORESET_PATDET', '"',
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('NO_RESET', 'RESET_MATCH', 'RESET_NOT_MATCH'), '"'))
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attributes.append(('MASK', '48\'d', (48), ''))
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attributes.append(('PATTERN', '48\'d', (48), ''))
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attributes.append(
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(
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'SEL_MASK', '"', ('MASK', 'C', 'ROUNDING_MODE1', 'ROUNDING_MODE2'),
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'"'))
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attributes.append(('SEL_PATTERN', '"', ('PATTERN', 'C'), '"'))
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attributes.append(
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('USE_PATTERN_DETECT', '"', ('NO_PATDET', 'PATDET'), '"'))
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# CSV headings
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headings = []
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headings.append('TILE')
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headings.append('SITE')
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for attribute in attributes:
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headings.append(attribute[0])
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# ACASCREG dependent on AREG
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if attribute[0] == 'AREG':
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headings.append('ACASCREG')
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# BCASCREG dependent on BREG
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if attribute[0] == 'BREG':
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headings.append('BCASCREG')
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# USE_MULT dependent on USE_SIMD
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if attribute[0] == 'USE_SIMD':
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headings.append('USE_MULT')
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# MREG dependent on USE_MULT
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headings.append('MREG')
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# CSV rows
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rows = []
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rows.append(headings)
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data = {}
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data['instances'] = []
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print('module top();')
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sites = list(gen_sites())
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# For every DSP site:
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# Add an instance to top.v with fuzzed attributes
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# Add a row for params.csv
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for (tile, site) in sites:
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row = []
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row.append(tile)
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row.append(site)
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print('\t(* KEEP, DONT_TOUCH, LOC = "{0}" *)'.format(site))
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print('\tDSP48E1 #(')
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synthesis = '(* KEEP, DONT_TOUCH, LOC = "%s" *)' % (site)
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module = 'DSP48E1'
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instance = 'INST_%s' % (site)
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ports = {}
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params = {}
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for attr in attributes[:-1]:
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val = fuzz(attr[2])
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row.append(val)
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print(
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'\t\t.{0}({1}{2}{3}),'.format(attr[0], attr[1], val, attr[3]))
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params['ADREG'] = fuzz((0, 1))
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params['ALUMODEREG'] = fuzz((0, 1))
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# AREG/BREG requires inputs to be connected when configured with a value
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# of 2, constraining to 0 and 1 for now.
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params['AREG'] = fuzz((0, 1))
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params['ACASCREG'] = params['AREG'] if params[
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'AREG'] == 0 or params['AREG'] == 1 else fuzz((1, 2))
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params['BREG'] = fuzz((0, 1))
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||||
params['BCASCREG'] = params['BREG'] if params[
|
||||
'BREG'] == 0 or params['BREG'] == 1 else fuzz((1, 2))
|
||||
params['CARRYINREG'] = fuzz((0, 1))
|
||||
params['CARRYINSELREG'] = fuzz((0, 1))
|
||||
params['CREG'] = fuzz((0, 1))
|
||||
params['DREG'] = fuzz((0, 1))
|
||||
params['INMODEREG'] = fuzz((0, 1))
|
||||
params['OPMODEREG'] = fuzz((0, 1))
|
||||
params['PREG'] = fuzz((0, 1))
|
||||
params['A_INPUT'] = verilog.quote(fuzz(('DIRECT', 'CASCADE')))
|
||||
params['B_INPUT'] = verilog.quote(fuzz(('DIRECT', 'CASCADE')))
|
||||
params['USE_DPORT'] = verilog.quote(fuzz(('TRUE', 'FALSE')))
|
||||
params['USE_SIMD'] = verilog.quote(
|
||||
fuzz(('ONE48', 'TWO24', 'FOUR12')))
|
||||
params['USE_MULT'] = verilog.quote(
|
||||
'NONE' if params['USE_SIMD'] != verilog.quote('ONE48') else
|
||||
fuzz(('NONE', 'MULTIPLY', 'DYNAMIC')))
|
||||
params['MREG'] = 0 if params['USE_MULT'] == verilog.quote(
|
||||
'NONE') else fuzz((0, 1))
|
||||
params['AUTORESET_PATDET'] = verilog.quote(
|
||||
fuzz(('NO_RESET', 'RESET_MATCH', 'RESET_NOT_MATCH')))
|
||||
params['MASK'] = '48\'d%s' % fuzz(48)
|
||||
params['PATTERN'] = '48\'d%s' % fuzz(48)
|
||||
params['SEL_MASK'] = verilog.quote(
|
||||
fuzz(('MASK', 'C', 'ROUNDING_MODE1', 'ROUNDING_MODE2')))
|
||||
params['USE_PATTERN_DETECT'] = verilog.quote(
|
||||
fuzz(('NO_PATDET', 'PATDET')))
|
||||
|
||||
# ACASCREG dependent on AREG
|
||||
if attr[0] == 'AREG':
|
||||
if val == 0 or val == 1:
|
||||
print('\t\t.ACASCREG({0}),'.format(val))
|
||||
elif val == 2:
|
||||
val = fuzz((1, 2))
|
||||
print('\t\t.ACASCREG({0}),'.format(val))
|
||||
verilog.instance(synthesis + ' ' + module, instance, ports, params)
|
||||
|
||||
row.append(val)
|
||||
params['TILE'] = tile
|
||||
params['SITE'] = site
|
||||
|
||||
# BCASCREG dependent on BREG
|
||||
elif attr[0] == 'BREG':
|
||||
if val == 0 or val == 1:
|
||||
print('\t\t.BCASCREG({0}),'.format(val))
|
||||
elif val == 2:
|
||||
val = fuzz((1, 2))
|
||||
print('\t\t.BCASCREG({0}),'.format(val))
|
||||
data['instances'].append(params)
|
||||
|
||||
row.append(val)
|
||||
|
||||
# USE_MULT dependent on USE_SIMD
|
||||
elif attr[0] == 'USE_SIMD':
|
||||
if val != "ONE48":
|
||||
val = 'NONE'
|
||||
print('\t\t.USE_MULT("{0}"),'.format(val))
|
||||
else:
|
||||
val = fuzz(('NONE', 'MULTIPLY', 'DYNAMIC'))
|
||||
print('\t\t.USE_MULT("{0}"),'.format(val))
|
||||
|
||||
row.append(val)
|
||||
|
||||
# MREG dependent on USE_MULT
|
||||
if val == 'NONE':
|
||||
val = 0
|
||||
print('\t\t.MREG("{0}"),'.format(val))
|
||||
else:
|
||||
val = fuzz((0, 1))
|
||||
print('\t\t.MREG("{0}"),'.format(val))
|
||||
|
||||
row.append(val)
|
||||
|
||||
attr = attributes[-1]
|
||||
val = fuzz(attr[2])
|
||||
row.append(val)
|
||||
print('\t\t.{0}({1}{2}{3})'.format(attr[0], attr[1], val, attr[3]))
|
||||
|
||||
rows.append(row)
|
||||
print('\t) dsp_{0} ();\n'.format(site))
|
||||
with open('params.json', 'w') as fp:
|
||||
json.dump(data, fp)
|
||||
|
||||
print("endmodule")
|
||||
|
||||
# Generate params.csv
|
||||
with open('params.csv', 'w') as writeFile:
|
||||
writer = csv.writer(writeFile)
|
||||
writer.writerows(rows)
|
||||
writeFile.close()
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
run()
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
import sys
|
||||
import random
|
||||
import re
|
||||
|
||||
|
||||
def top_harness(DIN_N, DOUT_N, f=sys.stdout):
|
||||
|
|
@ -64,6 +65,35 @@ def unquote(s):
|
|||
assert s[0] == '"' and s[-1] == '"'
|
||||
return s[1:-1]
|
||||
|
||||
def to_int(s):
|
||||
value = 0
|
||||
|
||||
match = re.search(r'^(\d+)\'([sS]*)([bBoOdDhH])(.*)', str(s))
|
||||
|
||||
if match:
|
||||
width = int(match.group(1))
|
||||
signed = match.group(2)
|
||||
radix = match.group(3)
|
||||
value = match.group(4)
|
||||
|
||||
# Convert to int type
|
||||
if re.match(r'[bB]', radix):
|
||||
value = int(value, 2)
|
||||
elif re.match(r'[oO]', radix):
|
||||
value = int(value, 8)
|
||||
elif re.match(r'[dD]', radix):
|
||||
value = int(value, 10)
|
||||
elif re.match(r'[hH]', radix):
|
||||
value = int(value, 16)
|
||||
else:
|
||||
raise ValueError('Don\'t know how to interpret input %s' % (s))
|
||||
|
||||
# Truncate to `width` bits
|
||||
value &= 2**width - 1
|
||||
else:
|
||||
value = int(s)
|
||||
|
||||
return value
|
||||
|
||||
def parsei(s):
|
||||
if s == "1'b0":
|
||||
|
|
|
|||
Loading…
Reference in New Issue