mirror of https://github.com/openXC7/prjxray.git
Merge pull request #1080 from JakeMercer/dsp
DSP - Add Attribute Fuzzing
This commit is contained in:
litghost
GitHub
commit
4cec0817ab
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@ -8,3 +8,4 @@ database
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run.ok
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__pycache__
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*.pyc
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*.swp
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@ -1,23 +1,126 @@
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#!/usr/bin/env python3
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from prjxray.segmaker import Segmaker
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import csv
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from prjxray.verilog import to_int
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from prjxray.verilog import quote
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import json
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segmk = Segmaker("design.bits", verbose=True)
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print("Loading tags")
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with open('params.csv', 'r') as f:
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for d in csv.DictReader(f):
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dsp = "DSP_0" if d['site'][-1] in "02468" else "DSP_1"
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def add(segmk, site, dsp, tag, bit, value, invert):
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tag = "%s.%s%s[%u]" % (dsp, ('Z' if invert else ''), tag, bit)
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value = (~value if invert else value)
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value >>= bit
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return segmk.add_site_tag(site, tag, value & 1)
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mask = int(d['mask'])
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pattern = int(d['pattern'])
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def run():
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segmk = Segmaker("design.bits", verbose=True)
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print("Loading tags")
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with open('params.json', 'r') as fp:
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data = json.load(fp)
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for params in data['instances']:
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dsp = "DSP_0" if params['SITE'][-1] in "02468" else "DSP_1"
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site = params['SITE']
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add(segmk, site, dsp, 'ADREG', 0, to_int(params['ADREG']), 0)
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add(segmk, site, dsp, 'ALUMODEREG', 0, to_int(params['ALUMODEREG']), 1)
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for i in range(2):
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add(segmk, site, dsp, 'AREG', i, to_int(params['AREG']), 1)
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for i in range(2):
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add(segmk, site, dsp, 'ACASCREG', i, to_int(params['ACASCREG']), 1)
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for i in range(2):
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add(segmk, site, dsp, 'BREG', i, to_int(params['BREG']), 1)
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for i in range(2):
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add(segmk, site, dsp, 'BCASCREG', i, to_int(params['BCASCREG']), 1)
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add(segmk, site, dsp, 'CARRYINREG', 0, to_int(params['CARRYINREG']), 1)
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add(
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segmk, site, dsp, 'CARRYINSELREG', 0,
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to_int(params['CARRYINSELREG']), 1)
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add(segmk, site, dsp, 'CREG', 0, to_int(params['CREG']), 1)
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add(segmk, site, dsp, 'DREG', 0, to_int(params['DREG']), 0)
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add(segmk, site, dsp, 'INMODEREG', 0, to_int(params['INMODEREG']), 1)
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add(segmk, site, dsp, 'OPMODEREG', 0, to_int(params['OPMODEREG']), 1)
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add(segmk, site, dsp, 'PREG', 0, to_int(params['PREG']), 1)
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INPUT = {}
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INPUT[quote('DIRECT')] = 0
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INPUT[quote('CASCADE')] = 1
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add(segmk, site, dsp, 'A_INPUT', 0, INPUT[params['A_INPUT']], 0)
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add(segmk, site, dsp, 'B_INPUT', 0, INPUT[params['B_INPUT']], 0)
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BOOL = {}
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BOOL[quote('FALSE')] = 0
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BOOL[quote('TRUE')] = 1
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add(segmk, site, dsp, 'USE_DPORT', 0, BOOL[params['USE_DPORT']], 0)
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SIMD = {}
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SIMD[quote('ONE48')] = 0
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SIMD[quote('TWO24')] = 1
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SIMD[quote('FOUR12')] = 2
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for i in range(2):
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add(segmk, site, dsp, 'USE_SIMD', i, SIMD[params['USE_SIMD']], 0)
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MULT = {}
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MULT[quote('NONE')] = 0
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MULT[quote('MULTIPLY')] = 1
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MULT[quote('DYNAMIC')] = 2
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for i in range(2):
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add(segmk, site, dsp, 'USE_MULT', i, MULT[params['USE_MULT']], 0)
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add(segmk, site, dsp, 'MREG', 0, to_int(params['MREG']), 1)
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AUTORESET = {}
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AUTORESET[quote('NO_RESET')] = 0
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AUTORESET[quote('RESET_NOT_MATCH')] = 1
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AUTORESET[quote('RESET_MATCH')] = 2
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add(
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segmk, site, dsp, 'AUTORESET_PATDET', 0,
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AUTORESET[params['AUTORESET_PATDET']], 0)
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add(
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segmk, site, dsp, 'AUTORESET_PATDET', 1,
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AUTORESET[params['AUTORESET_PATDET']], 1)
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for i in range(48):
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segmk.add_site_tag(
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d['site'], "%s.MASK[%d]" % (dsp, i), (mask >> i) & 1)
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segmk.add_site_tag(
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d['site'], "%s.PATTERN[%d]" % (dsp, i), (pattern >> i) & 1)
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add(segmk, site, dsp, 'MASK', i, to_int(params['MASK']), 0)
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segmk.compile()
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segmk.write()
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for i in range(48):
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add(segmk, site, dsp, 'PATTERN', i, to_int(params['PATTERN']), 0)
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SEL_MASK = {}
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SEL_MASK[quote('MASK')] = 0
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SEL_MASK[quote('C')] = 1
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SEL_MASK[quote('ROUNDING_MODE1')] = 2
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SEL_MASK[quote('ROUNDING_MODE2')] = 3
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for i in range(2):
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add(
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segmk, site, dsp, 'SEL_MASK', i, SEL_MASK[params['SEL_MASK']],
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0)
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USE_PATTERN_DETECT = {}
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USE_PATTERN_DETECT[quote('NO_PATDET')] = 0
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USE_PATTERN_DETECT[quote('PATDET')] = 1
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add(
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segmk, site, dsp, 'USE_PATTERN_DETECT', 0,
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USE_PATTERN_DETECT[params['USE_PATTERN_DETECT']], 0)
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segmk.compile()
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segmk.write()
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if __name__ == '__main__':
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run()
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@ -5,10 +5,19 @@ proc run {} {
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_param tcl.collectionResultDisplayLimit 0
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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@ -1,55 +1,149 @@
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import os
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import random
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import json
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import verilog
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from prjxray.db import Database
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def gen_sites():
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db = Database(util.get_db_root())
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grid = db.grid()
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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for tile in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile)
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gridinfo = grid.gridinfo_at_loc(loc)
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if gridinfo.tile_type in ['DSP_L', 'DSP_R']:
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for site in sorted(gridinfo.sites.keys()):
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if gridinfo.sites[site] == 'DSP48E1':
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yield tile_name, site
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yield tile, site
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def write_params(lines):
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pinstr = 'tile,site,mask,pattern\n'
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for tile, site, mask, pattern in lines:
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pinstr += '%s,%s,%s,%s\n' % (tile, site, mask, pattern)
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open('params.csv', 'w').write(pinstr)
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def fuzz(*args):
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if len(args) == 1 and isinstance(args[0], int):
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# Argument indicates that we should generate a random integer with
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# args[0] number of bits.
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return random.getrandbits(args[0])
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else:
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# Otherwise make a random choice
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return random.choice(*args)
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def run():
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print('''
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module top();
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''')
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verilog.top_harness(48, 48)
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lines = []
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print('module roi(input clk, input [47:0] din, output [47:0] dout);')
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data = {}
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data['instances'] = []
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sites = list(gen_sites())
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for (tile_name, site_name) in sites:
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mask = random.randint(0, 2**48 - 1)
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pattern = random.randint(0, 2**48 - 1)
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lines.append((tile_name, site_name, mask, pattern))
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print(
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'''
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(* KEEP, DONT_TOUCH, LOC = "{0}" *)
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DSP48E1 #(
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.MASK(48'h{1:x}),
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.PATTERN(48'h{2:x})
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) dsp_{0} (
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);
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'''.format(site_name, mask, pattern))
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for i, (tile, site) in enumerate(sites):
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synthesis = '(* KEEP, DONT_TOUCH, LOC = "%s" *)' % (site)
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module = 'DSP48E1'
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instance = 'INST_%s' % (site)
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ports = {}
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params = {}
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ports['A'] = '{30{1\'b1}}'
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ports['ACIN'] = '{30{1\'b1}}'
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ports['ACOUT'] = '30\'b0'
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ports['ALUMODE'] = '4\'b1'
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ports['B'] = '{18{1\'b1}}'
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ports['BCIN'] = '{18{1\'b1}}'
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ports['BCOUT'] = '18\'b0'
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ports['C'] = '{48{1\'b1}}'
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ports['CARRYCASCIN'] = '1\'b1'
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ports['CARRYCASCOUT'] = '1\'b0'
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ports['CARRYIN'] = '1\'b1'
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ports['CARRYINSEL'] = '3\'b000'
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ports['CARRYOUT'] = '4\'b0'
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ports['CEA1'] = '1\'b1'
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ports['CEA2'] = '1\'b1'
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ports['CEAD'] = '1\'b1'
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ports['CEALUMODE'] = '1\'b1'
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ports['CEB1'] = '1\'b1'
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ports['CEB2'] = '1\'b1'
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ports['CEC'] = '1\'b1'
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ports['CECARRYIN'] = '1\'b1'
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ports['CECTRL'] = '1\'b1'
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ports['CED'] = '1\'b1'
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ports['CEINMODE'] = '1\'b1'
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ports['CEM'] = '1\'b1'
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ports['CEP'] = '1\'b1'
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ports['CLK'] = '1\'b1'
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ports['D'] = '{25{1\'b1}}'
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ports['INMODE'] = '5\'b11111'
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#ports['MULTISIGNIN'] = '1\'b1'
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#ports['MULTISIGNOUT'] = '1\'b0'
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ports['OPMODE'] = '7\'b1111111'
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ports['OVERFLOW'] = '1\'b0'
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ports['P'] = '48\'b0'
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ports['PATTERNBDETECT'] = '1\'b0'
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ports['PATTERNDETECT'] = '1\'b0'
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ports['PCIN'] = '{48{1\'b1}}'
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ports['PCOUT'] = '48\'b0'
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ports['RSTA'] = '1\'b1'
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ports['RSTALLCARRYIN'] = '1\'b1'
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ports['RSTALUMODE'] = '1\'b1'
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ports['RSTB'] = '1\'b1'
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ports['RSTC'] = '1\'b1'
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ports['RSTCTRL'] = '1\'b1'
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ports['RSTD'] = '1\'b1'
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ports['RSTINMODE'] = '1\'b1'
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ports['RSTM'] = '1\'b1'
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ports['RSTP'] = '1\'b1'
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ports['UNDERFLOW'] = '1\'b0'
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params['ADREG'] = fuzz((0, 1))
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params['ALUMODEREG'] = fuzz((0, 1))
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params['AREG'] = fuzz((0, 1, 2))
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if params['AREG'] == 0 or params['AREG'] == 1:
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params['ACASCREG'] = params['AREG']
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else:
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params['ACASCREG'] = fuzz((1, 2))
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params['BREG'] = fuzz((0, 1, 2))
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if params['BREG'] == 0 or params['BREG'] == 1:
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params['BCASCREG'] = params['BREG']
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else:
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params['BCASCREG'] = fuzz((1, 2))
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params['CARRYINREG'] = fuzz((0, 1))
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params['CARRYINSELREG'] = fuzz((0, 1))
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params['CREG'] = fuzz((0, 1))
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params['DREG'] = fuzz((0, 1))
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params['INMODEREG'] = fuzz((0, 1))
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params['OPMODEREG'] = fuzz((0, 1))
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params['PREG'] = fuzz((0, 1))
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params['A_INPUT'] = verilog.quote(fuzz(('DIRECT', 'CASCADE')))
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params['B_INPUT'] = verilog.quote(fuzz(('DIRECT', 'CASCADE')))
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params['USE_DPORT'] = verilog.quote(fuzz(('TRUE', 'FALSE')))
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params['USE_SIMD'] = verilog.quote(fuzz(('ONE48', 'TWO24', 'FOUR12')))
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params['USE_MULT'] = verilog.quote(
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'NONE' if params['USE_SIMD'] != verilog.quote('ONE48') else fuzz(
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('NONE', 'MULTIPLY', 'DYNAMIC')))
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params['MREG'] = 0 if params['USE_MULT'] == verilog.quote(
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'NONE') else fuzz((0, 1))
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params['AUTORESET_PATDET'] = verilog.quote(
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fuzz(('NO_RESET', 'RESET_MATCH', 'RESET_NOT_MATCH')))
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params['MASK'] = '48\'d%s' % fuzz(48)
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params['PATTERN'] = '48\'d%s' % fuzz(48)
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params['SEL_MASK'] = verilog.quote(
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fuzz(('MASK', 'C', 'ROUNDING_MODE1', 'ROUNDING_MODE2')))
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params['USE_PATTERN_DETECT'] = verilog.quote(
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fuzz(('NO_PATDET', 'PATDET')))
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verilog.instance(synthesis + ' ' + module, instance, ports, params)
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params['TILE'] = tile
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params['SITE'] = site
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data['instances'].append(params)
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with open('params.json', 'w') as fp:
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json.dump(data, fp)
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print("endmodule")
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write_params(lines)
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if __name__ == '__main__':
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@ -1,5 +1,6 @@
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import sys
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import random
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import re
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def top_harness(DIN_N, DOUT_N, f=sys.stdout):
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@ -65,6 +66,37 @@ def unquote(s):
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return s[1:-1]
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def to_int(s):
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value = 0
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match = re.search(r'^(\d+)\'([sS]*)([bBoOdDhH])(.*)', str(s))
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if match:
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width = int(match.group(1))
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signed = match.group(2)
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radix = match.group(3)
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value = match.group(4)
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# Convert to int type
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if re.match(r'[bB]', radix):
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value = int(value, 2)
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elif re.match(r'[oO]', radix):
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value = int(value, 8)
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elif re.match(r'[dD]', radix):
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value = int(value, 10)
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elif re.match(r'[hH]', radix):
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value = int(value, 16)
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else:
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raise ValueError('Don\'t know how to interpret input %s' % (s))
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# Truncate to `width` bits
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value &= 2**width - 1
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else:
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value = int(s)
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return value
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def parsei(s):
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if s == "1'b0":
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return 0
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