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Handle weird bel pins that aren't really clocks. 

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2020-02-12 12:50:54 -08:00
parent 2f388235e4
commit 49b5a8cde6
3 changed files with 21 additions and 8 deletions
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2
fuzzers/007-timing/bel/fixup_timings_txt.py
View File

@ -56,7 +56,7 @@ def fix_line(line, site, filetype):
entries.append(line[loc])
loc += 1
elif filetype == 'pins':
for pin_word in range(0, 3):
for pin_word in range(0, 4):
entries.append(line[loc])
loc += 1
elif filetype == 'properties':

6
fuzzers/007-timing/bel/runme.tcl
View File

@ -56,8 +56,9 @@ proc dump_tile_timings {tile timing_fp config_fp pins_fp tile_pins_fp} {
foreach pin $site_pins {
set direction [get_property DIRECTION $pin]
set is_part_of_bus [get_property IS_PART_OF_BUS $pin]
regexp {\/(.*)$} $pin -> pin
lappend tile_pins_line $pin $direction
lappend tile_pins_line $pin $direction $is_part_of_bus
}
# dump bel pins, speed_models and configs
@ -78,8 +79,9 @@ proc dump_tile_timings {tile timing_fp config_fp pins_fp tile_pins_fp} {
foreach pin $bel_pins {
set direction [get_property DIRECTION $pin]
set is_clock [get_property IS_CLOCK $pin]
set is_part_of_bus [get_property IS_PART_OF_BUS $pin]
regexp {\/.*\/(.*)$} $pin -> pin
lappend pins_line $pin $direction $is_clock
lappend pins_line $pin $direction $is_clock $is_part_of_bus
}
lappend config_line $bel_type

21
fuzzers/007-timing/bel/tim2json.py
View File

@ -407,7 +407,8 @@ def read_raw_timings(fin, properties, pins, site_pins, pin_alias_map):
if pim:
if pins[slice][site_name][delay_btype_orig][orig_pin][
'is_clock']:
'is_clock'] and not pins[slice][site_name][
delay_btype_orig][orig_pin]['is_part_of_bus']:
bel_clock = pin
bel_clock_orig_pin = orig_pin
elif pins[slice][site_name][delay_btype_orig][orig_pin][
@ -425,8 +426,9 @@ def read_raw_timings(fin, properties, pins, site_pins, pin_alias_map):
orig_pin = pin
pim, pin = pin_in_model(pin.lower(), speed_model_clean)
if pim:
if site_pins[slice][site_name.
lower()][orig_pin]['is_clock']:
if site_pins[slice][site_name.lower(
)][orig_pin]['is_clock'] and not site_pins[slice][
site_name.lower()][orig_pin]['is_part_of_bus']:
bel_clock = pin
bel_clock_orig_pin = orig_pin
speed_model_clean = remove_pin_from_model(
@ -655,6 +657,7 @@ def read_bel_pins(pins_file):
pin_name = raw_pins[pin_loc]
pin_direction = raw_pins[pin_loc + 1]
pin_is_clock = raw_pins[pin_loc + 2]
pin_is_part_of_bus = raw_pins[pin_loc + 3]
yield (
tile, site_name, bel_name, pin_name,
@ -662,7 +665,11 @@ def read_bel_pins(pins_file):
yield (
tile, site_name, bel_name, pin_name,
'is_clock'), int(pin_is_clock) == 1
pin_loc += 3
yield (
tile, site_name, bel_name, pin_name,
'is_part_of_bus'
), int(pin_is_part_of_bus) == 1
pin_loc += 4
return merged_dict(inner())
@ -688,6 +695,7 @@ def read_site_pins(pins_file):
for pin in range(0, site_pins_count):
pin_name = raw_pins[pin_loc]
pin_direction = raw_pins[pin_loc + 1]
pin_is_part_of_bus = raw_pins[pin_loc + 2]
yield (
(tile, site_name, pin_name, 'direction'),
@ -695,9 +703,12 @@ def read_site_pins(pins_file):
yield (
(tile, site_name, pin_name, 'is_clock'),
pin_name.lower() == 'clk')
yield (
(tile, site_name, pin_name, 'is_part_of_bus'),
int(pin_is_part_of_bus))
# site clock pins are always named 'CLK'
pin_loc += 2
pin_loc += 3
return merged_dict(inner())