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Added fuzzing of local inverters 

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2019-07-16 14:18:18 +02:00
parent c880707d27
commit c935d44fdc
3 changed files with 32 additions and 6 deletions
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8
fuzzers/035a-iob-idelay/generate.py
View File

@ -45,6 +45,14 @@ for params in data:
value = verilog.unquote(params["PIPE_SEL"])
segmk.add_site_tag(loc, "PIPE_SEL", int(value == "TRUE"))
if "IS_C_INVERTED" in params:
segmk.add_site_tag(loc, "IS_C_INVERTED", int(params["IS_C_INVERTED"]))
segmk.add_site_tag(
loc, "IS_DATAIN_INVERTED", int(params["IS_DATAIN_INVERTED"]))
segmk.add_site_tag(
loc, "IS_IDATAIN_INVERTED", int(params["IS_IDATAIN_INVERTED"]))
def bitfilter(frame_idx, bit_idx):
return True

1
fuzzers/035a-iob-idelay/generate.tcl
View File

@ -8,6 +8,7 @@ set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
set_param tcl.collectionResultDisplayLimit 0
set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-79}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-81}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-84}]

29
fuzzers/035a-iob-idelay/top.py
View File

@ -54,7 +54,6 @@ def gen_sites():
except KeyError:
pass
#idelay = [k for k,v in ioi_gridinfo.sites.items() if v == "IDELAYE2"][0]
iob33s = [k for k, v in iob_gridinfo.sites.items() if v == "IOB33S"][0]
iob33m = [k for k, v in iob_gridinfo.sites.items() if v == "IOB33M"][0]
idelay_s = iob33s.replace("IOB", "IDELAY")
@ -74,10 +73,14 @@ def run():
print(
'''
module top (
(* CLOCK_BUFFER_TYPE = "NONE" *)
input wire clk,
input wire [{N}:0] di,
output wire [{N}:0] do
);
wire clk_buf = clk;
wire [{N}:0] di_buf;
wire [{N}:0] do_buf;
'''.format(**{"N": len(tiles) - 1}))
@ -111,6 +114,12 @@ wire [{N}:0] do_buf;
"\"" + random.choice(["TRUE", "FALSE"]) + "\"",
"PIPE_SEL":
"\"" + random.choice(["TRUE", "FALSE"]) + "\"",
"IS_C_INVERTED":
random.randint(0, 1),
"IS_DATAIN_INVERTED":
random.randint(0, 1),
"IS_IDATAIN_INVERTED":
random.randint(0, 1),
}
if params["IDELAY_TYPE"] != "\"VAR_LOAD_PIPE\"":
@ -122,7 +131,8 @@ wire [{N}:0] do_buf;
if params["IDELAY_TYPE"] == "\"VAR_LOAD_PIPE\"":
params["IDELAY_VALUE"] = 0
# SIGNAL_PATTERN and HIGH_PERFORMANCE_MODE have no bits
if params["IDELAY_TYPE"] == "\"FIXED\"":
params["IS_C_INVERTED"] = 0
param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items())
@ -132,8 +142,8 @@ wire [{N}:0] do_buf;
print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o)
print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i))
print(
'mod #(%s) mod_%03d (.I(di_buf[%3d]), .O(do_buf[%3d]));' %
(param_str, i, i, i))
'mod #(%s) mod_%03d (.clk(clk_buf), .I(di_buf[%3d]), .O(do_buf[%3d]));'
% (param_str, i, i, i))
data.append(params)
@ -151,6 +161,7 @@ endmodule
(* KEEP, DONT_TOUCH *)
module mod(
input wire clk,
input wire I,
output wire O
);
@ -163,6 +174,9 @@ parameter HIGH_PERFORMANCE_MODE = "TRUE";
parameter SIGNAL_PATTERN = "DATA";
parameter CINVCTRL_SEL = "FALSE";
parameter PIPE_SEL = "FALSE";
parameter IS_C_INVERTED = 0;
parameter IS_DATAIN_INVERTED = 0;
parameter IS_IDATAIN_INVERTED = 0;
wire x;
@ -175,11 +189,14 @@ IDELAYE2 #(
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE),
.SIGNAL_PATTERN(SIGNAL_PATTERN),
.CINVCTRL_SEL(CINVCTRL_SEL),
.PIPE_SEL(PIPE_SEL)
.PIPE_SEL(PIPE_SEL),
.IS_C_INVERTED(IS_C_INVERTED),
.IS_DATAIN_INVERTED(IS_DATAIN_INVERTED),
.IS_IDATAIN_INVERTED(IS_IDATAIN_INVERTED)
)
idelay
(
.C(),
.C(clk),
.REGRST(),
.LD(),
.CE(),