Merge pull request #1000 from litghost/iob_hclk_iostandard

Add stepdown feature to HCLK_IOI.

fuzzers/005-tilegrid/add_tdb.py

@@ -89,7 +89,7 @@ def run(fn_in, fn_out, verbose=False):
         ("clk_hrow/build/segbits_tilegrid.tdb", 30, 18),
         ("clk_bufg/build/segbits_tilegrid.tdb", 30, 8),
         ("hclk_cmt/build/segbits_tilegrid.tdb", 30, 10),
-        ("hclk_ioi/build/segbits_tilegrid.tdb", 42, 10),
+        ("hclk_ioi/build/segbits_tilegrid.tdb", 42, 1),
         ("clb_int/build/segbits_tilegrid.tdb", int_frames, int_words),
         ("iob_int/build/segbits_tilegrid.tdb", int_frames, int_words),
         ("bram_int/build/segbits_tilegrid.tdb", int_frames, int_words),

fuzzers/005-tilegrid/hclk_ioi/Makefile

@@ -1,4 +1,4 @@
 N ?= 5
-GENERATE_ARGS?="--oneval 1 --design params.csv --dword 5 --dframe 21"
+GENERATE_ARGS?="--oneval 1 --design params.csv --dword 0 --dframe 21"
 include ../fuzzaddr/common.mk
 

fuzzers/030-iob/Makefile

@@ -17,7 +17,7 @@ build/segbits_xiob33.db: build/segbits_xiob33.rdb process_rdb.py bits.dbf
 	${XRAY_MASKMERGE} build/mask_xiob33.db $$(find -name segdata_liob33.txt) $$(find -name segdata_riob33.txt)
 
 build/segbits_hclk_ioi3.rdb: $(SPECIMENS_OK)
-	${XRAY_SEGMATCH} -o build/segbits_hclk_ioi3.rdb $$(find -name segdata_hclk_ioi3.txt)
+	${XRAY_SEGMATCH} -c 4 -o build/segbits_hclk_ioi3.rdb $$(find -name segdata_hclk_ioi3.txt)
 
 build/segbits_hclk_ioi3.db: build/segbits_hclk_ioi3.rdb
 	${XRAY_DBFIXUP} --db-root build --zero-db hclk_bits.dbf --seg-fn-in build/segbits_hclk_ioi3.rdb --seg-fn-out $@

fuzzers/030-iob/generate.py

@@ -52,6 +52,25 @@ IBUF_LOW_PWR_SUPPORTED = ['SSTL135']
 
 
 def main():
+    # Create map of iobank -> sites
+    iobanks = {}
+    site_to_iobank = {}
+    iobank_iostandards = {}
+    with open(os.path.join(os.getenv('FUZDIR'), 'build', 'iobanks.txt')) as f:
+        for l in f:
+            iob_site, iobank = l.strip().split(',')
+            iobank = int(iobank)
+
+            if iobank not in iobanks:
+                iobanks[iobank] = set()
+
+            iobanks[iobank].add(iob_site)
+            assert iob_site not in site_to_iobank
+            site_to_iobank[iob_site] = iobank
+
+    for iobank in iobanks:
+        iobank_iostandards[iobank] = set()
+
     print("Loading tags")
     segmk = Segmaker("design.bits")
     '''
@@ -81,6 +100,8 @@ def main():
             if iostandard.startswith('DIFF_'):
                 iostandard = iostandard[5:]
 
+            iobank_iostandards[site_to_iobank[site]].add(iostandard)
+
             segmk.add_site_tag(
                 site, '_'.join(STEPDOWN_IOSTANDARDS) + '.STEPDOWN',
                 iostandard in STEPDOWN_IOSTANDARDS)
@@ -185,18 +206,6 @@ def main():
                 segmk.add_site_tag(
                     site, 'INTERMDISABLE.I', d['intermdisable_wire'] != '0')
 
-    # Create map of iobank -> sites
-    iobanks = {}
-    with open(os.path.join(os.getenv('FUZDIR'), 'build', 'iobanks.txt')) as f:
-        for l in f:
-            iob_site, iobank = l.strip().split(',')
-            iobank = int(iobank)
-
-            if iobank not in iobanks:
-                iobanks[iobank] = set()
-
-            iobanks[iobank].add(iob_site)
-
     site_to_cmt = {}
     site_to_tile = {}
     tile_to_cmt = {}
@@ -240,6 +249,26 @@ def main():
             opt = 'VREF.V_{:d}_MV'.format(int(float(vref) * 1000))
             segmk.add_tile_tag(hclk_cmt_tile, opt, 1)
 
+    for iobank in iobank_iostandards:
+        if len(iobank_iostandards[iobank]) == 0:
+            continue
+
+        for cmt_site in iobanks[iobank]:
+            if cmt_site in site_to_cmt:
+                cmt = site_to_cmt[cmt_site]
+                break
+
+        if cmt is None:
+            continue
+
+        _, hclk_cmt_tile = cmt_to_idelay[cmt]
+
+        assert len(iobank_iostandards[iobank]) == 1, iobank_iostandards[iobank]
+
+        iostandard = list(iobank_iostandards[iobank])[0]
+        segmk.add_tile_tag(
+            hclk_cmt_tile, 'STEPDOWN', iostandard in STEPDOWN_IOSTANDARDS)
+
     # For IOBANK's with no active VREF, clear all VREF options.
     for cmt, (_, hclk_cmt_tile) in cmt_to_idelay.items():
         if cmt in cmt_vref_active: