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Refactor clock invert tags for ISERDES/OSERDES. 

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2019-07-30 09:23:24 -07:00
parent 693c621e96
commit 48f97be0c7
3 changed files with 24 additions and 10 deletions
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7
fuzzers/035-iob-ilogic/generate.py
View File

@ -91,7 +91,7 @@ def main():
segmk.add_site_tag(
site, 'IFF.ZSRVAL_Q4', not d['SRVAL_Q4'])
if 'IS_CLK_INVERTED' in d:
if 'IS_CLK_INVERTED' in d and not d['DISABLE_CLOCKS']:
if verilog.unquote(d['INTERFACE_TYPE']) == 'MEMORY_DDR3':
segmk.add_site_tag(
site, 'IFF.INV_CLK', d['IS_CLK_INVERTED'])
@ -123,7 +123,7 @@ def main():
d['IS_CLK_INVERTED']
and d['IS_CLKB_INVERTED']))
if 'IS_OCLK_INVERTED' in d:
if 'IS_OCLK_INVERTED' in d and not d['DISABLE_CLOCKS']:
segmk.add_site_tag(
site, 'IFF.INV_OCLK', d['IS_OCLK_INVERTED'])
segmk.add_site_tag(
@ -133,7 +133,8 @@ def main():
segmk.add_site_tag(
site, 'IFF.ZINV_OCLKB', not d['IS_OCLKB_INVERTED'])
if 'IS_CLKDIV_INVERTED' in d:
if 'IS_CLKDIV_INVERTED' in d and not d['DISABLE_CLOCKS'] and \
verilog.unquote(d['INTERFACE_TYPE']) == 'MEMORY':
segmk.add_site_tag(
site, 'IFF.INV_CLKDIV', d['IS_CLKDIV_INVERTED'])
segmk.add_site_tag(

16
fuzzers/035-iob-ilogic/top.py
View File

@ -189,12 +189,14 @@ def use_iserdese2(p, luts, connects):
'clk_BUFG2',
))
clkdiv = random.choice(('0', ))
clkdiv = random.choice(('clk_BUFG3', 'clk_BUFG4'))
if random.randint(0, 1):
p['DISABLE_CLOCKS'] = random.randint(0, 1)
if p['DISABLE_CLOCKS']:
clknet = '0'
clkbnet = '0'
oclknet = '0'
clkdiv = '0'
print(
'''
@ -424,6 +426,8 @@ module top(input clk, inout wire [`N_DI-1:0] dio);
wire clk_BUFG1;
wire clk_BUFG2;
wire clk_BUFG3;
wire clk_BUFG4;
(* KEEP, DONT_TOUCH *)
BUFG bufg1(
@ -433,6 +437,14 @@ module top(input clk, inout wire [`N_DI-1:0] dio);
BUFG bufg2(
.O(clk_BUFG2)
);
(* KEEP, DONT_TOUCH *)
BUFG bufg3(
.O(clk_BUFG3)
);
(* KEEP, DONT_TOUCH *)
BUFG bufg4(
.O(clk_BUFG4)
);
'''.format(n_di=idx))
# Always output a LUT6 to make placer happy.

11
fuzzers/036-iob-ologic/generate.py
View File

@ -66,11 +66,12 @@ def main():
segmk.add_site_tag(
site, 'ZINV_{}'.format(opt), 1 ^ d[k])
for idx in range(4):
k = 'IS_T{}_INVERTED'.format(idx + 1)
segmk.add_site_tag(site, k, d[k])
segmk.add_site_tag(
site, 'ZINV_T{}'.format(idx + 1), 1 ^ d[k])
if d['io']:
for idx in range(4):
k = 'IS_T{}_INVERTED'.format(idx + 1)
segmk.add_site_tag(site, k, d[k])
segmk.add_site_tag(
site, 'ZINV_T{}'.format(idx + 1), 1 ^ d[k])
for idx in range(8):
k = 'IS_D{}_INVERTED'.format(idx + 1)