mirror of https://github.com/openXC7/prjxray.git
Refactor IOB fuzzer.
- Add SSTL135 - Refactor process_rdb to handle varying SLEW by IOSTANDARD. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
parent
ae526981a2
commit
aa331131f2
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@ -1,10 +1,15 @@
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N := 50
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SPECIMENS_DEPS := build/iobanks.txt
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include ../fuzzer.mk
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database: build/segbits_xiob33.db
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build/iobanks.txt: write_io_banks.tcl
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mkdir -p build
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cd build/ && ${XRAY_VIVADO} -mode batch -source ${FUZDIR}/write_io_banks.tcl
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build/segbits_xiob33.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -c 7 -o build/segbits_xiob33.rdb $$(find -name segdata_liob33.txt) $$(find -name segdata_riob33.txt)
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${XRAY_SEGMATCH} -c 12 -o build/segbits_xiob33.rdb $$(find -name segdata_liob33.txt) $$(find -name segdata_riob33.txt)
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build/segbits_xiob33.db: build/segbits_xiob33.rdb process_rdb.py bits.dbf
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python3 process_rdb.py build/segbits_xiob33.rdb > build/segbits_xiob33_processed.rdb
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@ -1,4 +1,4 @@
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38_92 39_93 38_94,IOB33.IOB_Y0.PULLTYPE.PULLDOWN
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38_106 38_110 39_105 39_109,IOB33.IOB_Y0.SLEW.FAST
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38_106 39_107 39_111 38_106 38_110 39_105 39_109,IOB33.IOB_Y0.SLEW.FAST
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39_33 38_34 39_35,IOB33.IOB_Y1.PULLTYPE.PULLDOWN
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38_18 38_22 39_17 39_21,IOB33.IOB_Y1.SLEW.FAST
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39_21 38_16 38_20 38_18 38_22 39_17,IOB33.IOB_Y1.SLEW.FAST
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@ -24,11 +24,11 @@ def process_parts(parts):
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if parts[0] == 'INOUT':
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yield 'type', 'IOBUF_INTERMDISABLE'
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if parts[0] == 'IN_ONLY':
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if parts[-1] == 'IN_ONLY':
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yield 'type', 'IBUF'
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if parts[0] == 'SLEW':
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yield 'SLEW', verilog.quote(parts[1])
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if len(parts) > 2 and parts[-2] == 'SLEW':
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yield 'SLEW', verilog.quote(parts[-1])
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if parts[0] == 'PULLTYPE':
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yield 'PULLTYPE', verilog.quote(parts[1])
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@ -38,7 +38,11 @@ def process_parts(parts):
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if len(parts) > 1 and parts[1] == 'DRIVE':
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yield 'IOSTANDARDS', parts[0].split('_')
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yield 'DRIVES', parts[2].split('_')
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if parts[2] == 'I_FIXED':
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yield 'DRIVES', [None]
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else:
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yield 'DRIVES', parts[2].split('_')
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def create_sites_from_fasm(root):
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@ -67,7 +71,7 @@ def create_sites_from_fasm(root):
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sites[key]['type'] = None
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else:
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assert 'IOSTANDARDS' in sites[key], sites[key]
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assert 'DRIVES' in sites[key]
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assert 'DRIVES' in sites[key], sites[key]
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sites[key]['type'] = "OBUF"
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return sites
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@ -76,10 +80,10 @@ def create_sites_from_fasm(root):
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def process_specimen(root):
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sites = create_sites_from_fasm(root)
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with open(os.path.join(root, 'params.jl')) as f:
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with open(os.path.join(root, 'params.json')) as f:
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params = json.load(f)
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for p in params:
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for p in params['tiles']:
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tile = p['tile']
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site = p['site']
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site_y = int(site[site.find('Y') + 1:]) % 2
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@ -96,7 +100,7 @@ def process_specimen(root):
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site_from_fasm = sites[(tile, site_key)]
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assert p['type'] == site_from_fasm['type'], (
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tile, site_key, p, site_from_fasm)
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tile, site_key, p['type'], site_from_fasm['type'])
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if p['type'] is None:
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continue
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@ -104,16 +108,28 @@ def process_specimen(root):
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assert p['PULLTYPE'] == site_from_fasm['PULLTYPE'], (
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tile, site_key, p, site_from_fasm)
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assert 'IOSTANDARDS' in site_from_fasm, (root, tile, site)
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assert verilog.unquote(
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p['IOSTANDARD']) in site_from_fasm['IOSTANDARDS'], (
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tile, site_key, p, site_from_fasm)
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p['IOSTANDARD'],
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site_from_fasm['IOSTANDARDS'],
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)
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if p['type'] != 'IBUF':
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assert p['SLEW'] == site_from_fasm['SLEW'], (
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tile, site_key, p, site_from_fasm)
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assert 'I{}'.format(p['DRIVE']) in site_from_fasm['DRIVES'], (
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tile, site_key, p, site_from_fasm)
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assert 'DRIVES' not in p, p
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assert 'DRIVES' in site_from_fasm, (
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tile, site, p['type'], site_from_fasm)
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if p['DRIVE'] is None:
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assert None in site_from_fasm['DRIVES'], (
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tile, site_key, p['DRIVE'], site_from_fasm['DRIVES'])
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else:
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assert 'I{}'.format(p['DRIVE']) in site_from_fasm['DRIVES'], (
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tile, site_key, p['DRIVE'], site_from_fasm['DRIVES'])
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def main():
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@ -15,6 +15,8 @@ def bitfilter(frame, word):
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def mk_drive_opt(iostandard, drive):
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if drive is None:
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drive = '_FIXED'
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return '{}.DRIVE.I{}'.format(iostandard, drive)
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@ -37,13 +39,15 @@ def drives_for_iostandard(iostandard):
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drives = [4, 8, 12, 16, 24]
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elif iostandard == 'LVCMOS12':
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drives = [4, 8, 12]
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elif iostandard == 'SSTL135':
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return ['_FIXED']
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else:
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drives = [4, 8, 12, 16]
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return drives
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STEPDOWN_IOSTANDARDS = ['LVCMOS12', 'LVCMOS15', 'LVCMOS18']
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STEPDOWN_IOSTANDARDS = ['LVCMOS12', 'LVCMOS15', 'LVCMOS18', 'SSTL135']
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def main():
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@ -54,10 +58,10 @@ def main():
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di[0],IOB_X0Y107,LIOB33_X0Y107,A21,PULLDOWN
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di[10],IOB_X0Y147,LIOB33_X0Y147,F14,PULLUP
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'''
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with open('params.jl', 'r') as f:
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with open('params.json', 'r') as f:
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design = json.load(f)
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for d in design:
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for d in design['tiles']:
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site = d['site']
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if skip_broken_tiles(d):
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@ -65,44 +69,31 @@ def main():
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iostandard = verilog.unquote(d['IOSTANDARD'])
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stepdown = iostandard in STEPDOWN_IOSTANDARDS
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segmk.add_site_tag(site, '_'.join(STEPDOWN_IOSTANDARDS), stepdown)
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segmk.add_site_tag(
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site, '_'.join(STEPDOWN_IOSTANDARDS) + '.STEPDOWN',
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iostandard in STEPDOWN_IOSTANDARDS)
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if d['type'] is None:
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segmk.add_site_tag(site, 'INOUT', 0)
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segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 0)
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segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
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segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
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for drive in drives_for_iostandard(iostandard):
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segmk.add_site_tag(
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site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
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iostandard, drive), 0)
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segmk.add_site_tag(site, '{}.IN_ONLY'.format(iostandard), 0)
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elif d['type'] == 'IBUF':
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segmk.add_site_tag(site, 'INOUT', 0)
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segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
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segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
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segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
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for drive in drives_for_iostandard(iostandard):
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segmk.add_site_tag(
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site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
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iostandard, drive), 1)
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segmk.add_site_tag(site, '{}.IN_ONLY'.format(iostandard), 1)
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elif d['type'] == 'OBUF':
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segmk.add_site_tag(site, 'INOUT', 0)
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segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
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segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
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segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
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for drive in drives_for_iostandard(iostandard):
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if drive == d['DRIVE']:
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segmk.add_site_tag(
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site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
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iostandard, drive), 1)
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else:
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segmk.add_site_tag(
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site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
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iostandard, drive), 0)
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elif d['type'] == 'IOBUF_INTERMDISABLE':
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segmk.add_site_tag(site, 'INOUT', 1)
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segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
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segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
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segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
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if d['type'] is not None:
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@ -126,13 +117,16 @@ def main():
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drive_opts.add(mk_drive_opt(opt, drive_opt))
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drive_opts.add(mk_drive_opt("SSTL135", None))
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segmaker.add_site_group_zero(
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segmk, site, '', drive_opts, mk_drive_opt('LVCMOS25', '12'),
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mk_drive_opt(iostandard, d['DRIVE']))
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segmaker.add_site_group_zero(
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segmk, site, "SLEW.", ("SLOW", "FAST"), "FAST",
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verilog.unquote(d['SLEW']))
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for opt in ["SLOW", "FAST"]:
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segmk.add_site_tag(
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site, iostandard + ".SLEW." + opt, opt == verilog.unquote(
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d['SLEW']))
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if 'ibufdisable_wire' in d:
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segmk.add_site_tag(
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@ -75,12 +75,25 @@ proc loc_pins {} {
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}
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}
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proc set_vref {} {
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set fp [open "iobank_vref.csv" r]
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for {gets $fp line} {$line != ""} {gets $fp line} {
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set parts [split $line ","]
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set iobank [lindex $parts 0]
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set vref [lindex $parts 1]
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puts "setting $iobank ([get_iobanks $iobank]) to INTERNAL_VREF $vref"
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set_property INTERNAL_VREF $vref [get_iobanks $iobank]
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}
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}
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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loc_pins
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set_vref
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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@ -66,127 +66,129 @@ def main():
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iostandard_lines = []
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with open(args.input_rdb) as f:
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for l in f:
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if ('.LVCMOS' in l or '.LVTTL' in l) and 'IOB_' in l:
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if ('.SSTL135' in l or '.LVCMOS' in l
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or '.LVTTL' in l) and 'IOB_' in l:
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iostandard_lines.append(l)
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else:
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print(l.strip())
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common_in_only_bits = {
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'IOB_Y0': set(),
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'IOB_Y1': set(),
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}
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for l in iostandard_lines:
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if 'IN_OUT_COMMON' in l:
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common_in_only_bits[get_site(l)] |= parse_bits(l)
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for site in sorted(common_in_only_bits):
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print(
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'IOB33.{}.IN_ONLY'.format(site), ' '.join(
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common_in_only_bits[site]))
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iostandard_in = {}
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outs = {}
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drives = {}
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in_use = {}
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sites = {}
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for l in iostandard_lines:
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name = get_name(l)
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feature = get_name(l)
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feature_parts = feature.split('.')
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site = get_site(l)
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iostandard = name.split('.')[2]
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iostandard = feature_parts[2]
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if name.endswith('.IN_USE'):
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in_use[(site, iostandard)] = parse_bits(l)
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bits = parse_bits(l)
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bits = filter_bits(site, bits)
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for l in iostandard_lines:
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name = get_name(l)
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site = get_site(l)
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iostandard = name.split('.')[2]
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if site not in sites:
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sites[site] = {}
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if name.endswith('.IN'):
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in_bits = parse_bits(l) | in_use[(site, iostandard)]
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group = feature_parts[3]
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if group not in sites[site]:
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sites[site][group] = {}
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if in_bits not in iostandard_in:
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iostandard_in[in_bits] = []
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if group in ['DRIVE', 'SLEW']:
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enum = feature_parts[4]
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sites[site][group][(iostandard, enum)] = bits
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elif group in ['IN', 'IN_ONLY', 'IN_USE', 'OUT', 'STEPDOWN']:
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sites[site][group][(iostandard, None)] = bits
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else:
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assert False, group
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iostandard_in[in_bits].append((site, iostandard))
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for site in sites:
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for iostandard, enum in sites[site]['DRIVE']:
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sites[site]['DRIVE'][(iostandard, enum)] |= sites[site]['OUT'][(
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iostandard, None)]
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if name.endswith('.OUT'):
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outs[(site,
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iostandard)] = parse_bits(l) | in_use[(site, iostandard)]
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if '.DRIVE.' in name and '.IN_OUT_COMMON' not in name:
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drive = name.split('.')[-1]
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if (site, iostandard) not in drives:
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drives[(site, iostandard)] = {}
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if drive not in drives[(site, iostandard)]:
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drives[(site, iostandard)][drive] = {}
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drives[(site, iostandard)][drive] = filter_bits(
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site, parse_bits(l))
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common_in_bits = {
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'IOB_Y0': set(),
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'IOB_Y1': set(),
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}
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for bits in sorted(iostandard_in.keys()):
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sites, standards = zip(*iostandard_in[bits])
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site = set(sites)
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assert len(site) == 1, site
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site = site.pop()
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common_in_bits[site] |= bits
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for bits in sorted(iostandard_in.keys()):
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sites, standards = zip(*iostandard_in[bits])
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site = set(sites)
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assert len(site) == 1, site
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site = site.pop()
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neg_bits = set('!' + bit for bit in (common_in_bits[site] - bits))
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print(
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'IOB33.{}.{}.IN'.format(site, '_'.join(standards)),
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' '.join(bits | neg_bits))
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iodrives = {}
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for iostandard, enum in sites[site]['IN']:
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sites[site]['IN_ONLY'][(iostandard, enum)] -= sites[site]['IN'][(
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iostandard, enum)]
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common_bits = {}
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for site in sites:
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for group in sites[site]:
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if (site, group) not in common_bits:
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common_bits[(site, group)] = set()
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for site, iostandard in drives:
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for drive in drives[(site, iostandard)]:
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combined_bits = drives[(site, iostandard)][drive] | outs[(
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site, iostandard)]
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for bits in sites[site][group].values():
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common_bits[(site, group)] |= bits
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if site not in common_bits:
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common_bits[site] = set(common_in_only_bits[site])
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slew_in_drives = {}
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common_bits[site] |= combined_bits
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for site in sites:
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common_bits[(site, 'DRIVE')] -= common_bits[(site, 'SLEW')]
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common_bits[(site, 'DRIVE')] -= common_bits[(site, 'STEPDOWN')]
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common_bits[(site, 'IN_ONLY')] |= common_bits[(site, 'DRIVE')]
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common_bits[(site, 'IN_ONLY')] -= common_bits[(site, 'STEPDOWN')]
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if combined_bits not in iodrives:
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iodrives[combined_bits] = []
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for iostandard, enum in sites[site]['DRIVE']:
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slew_in_drive = common_bits[
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(site, 'SLEW')] & sites[site]['DRIVE'][(iostandard, enum)]
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if slew_in_drive:
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if (site, iostandard) not in slew_in_drives:
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slew_in_drives[(site, iostandard)] = set()
|
||||
|
||||
iodrives[combined_bits].append((site, iostandard, drive))
|
||||
slew_in_drives[(site, iostandard)] |= slew_in_drive
|
||||
sites[site]['DRIVE'][(iostandard, enum)] -= slew_in_drive
|
||||
|
||||
for bits in iodrives:
|
||||
sites, standards, drives = zip(*iodrives[bits])
|
||||
sites[site]['DRIVE'][(iostandard,
|
||||
enum)] -= common_bits[(site, 'STEPDOWN')]
|
||||
|
||||
site = set(sites)
|
||||
for site, iostandard in slew_in_drives:
|
||||
for _, enum in sites[site]['SLEW']:
|
||||
sites[site]['SLEW'][(iostandard,
|
||||
enum)] |= slew_in_drives[(site, iostandard)]
|
||||
|
||||
assert len(site) == 1, site
|
||||
site = site.pop()
|
||||
for site in sites:
|
||||
del sites[site]['OUT']
|
||||
del sites[site]['IN_USE']
|
||||
|
||||
neg_bits = set('!' + bit for bit in (common_bits[site] - bits))
|
||||
for site in sites:
|
||||
for group in sites[site]:
|
||||
common_groups = {}
|
||||
|
||||
print(
|
||||
'IOB33.{}.{}.DRIVE.{}'.format(
|
||||
site, '_'.join(sorted(set(standards))), '_'.join(
|
||||
sorted(set(drives)))), ' '.join(bits | neg_bits))
|
||||
# Merge features that are identical.
|
||||
#
|
||||
# For example:
|
||||
#
|
||||
# IOB33.IOB_Y1.LVCMOS15.IN 38_42 39_41
|
||||
# IOB33.IOB_Y1.LVCMOS18.IN 38_42 39_41
|
||||
#
|
||||
# Must be grouped.
|
||||
for (iostandard, enum), bits in sites[site][group].items():
|
||||
if bits not in common_groups:
|
||||
common_groups[bits] = {
|
||||
'IOSTANDARDS': set(),
|
||||
'enums': set(),
|
||||
}
|
||||
|
||||
common_groups[bits]['IOSTANDARDS'].add(iostandard)
|
||||
if enum is not None:
|
||||
common_groups[bits]['enums'].add(enum)
|
||||
|
||||
for bits, v in common_groups.items():
|
||||
if v['enums']:
|
||||
feature = 'IOB33.{site}.{iostandards}.{group}.{enums}'.format(
|
||||
site=site,
|
||||
iostandards='_'.join(sorted(v['IOSTANDARDS'])),
|
||||
group=group,
|
||||
enums='_'.join(sorted(v['enums'])),
|
||||
)
|
||||
else:
|
||||
feature = 'IOB33.{site}.{iostandards}.{group}'.format(
|
||||
site=site,
|
||||
iostandards='_'.join(sorted(v['IOSTANDARDS'])),
|
||||
group=group,
|
||||
)
|
||||
|
||||
neg_bits = frozenset(
|
||||
'!{}'.format(b)
|
||||
for b in (common_bits[(site, group)] - bits))
|
||||
print(
|
||||
'{} {}'.format(feature, ' '.join(sorted(bits | neg_bits))))
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
|
|
|
|||
|
|
@ -45,14 +45,22 @@ def run():
|
|||
io_idx = 0
|
||||
|
||||
iostandards = [
|
||||
'LVCMOS12', 'LVCMOS15', 'LVCMOS18', 'LVCMOS25', 'LVCMOS33', 'LVTTL'
|
||||
'LVCMOS12',
|
||||
'LVCMOS15',
|
||||
'LVCMOS18',
|
||||
'LVCMOS25',
|
||||
'LVCMOS33',
|
||||
'LVTTL',
|
||||
'SSTL135',
|
||||
]
|
||||
iostandard = random.choice(iostandards)
|
||||
|
||||
if iostandard in ['LVTTL', 'LVCMOS18']:
|
||||
drives = [4, 8, 12, 16, 24]
|
||||
elif iostandard == 'LVCMOS12':
|
||||
elif iostandard in ['LVCMOS12']:
|
||||
drives = [4, 8, 12]
|
||||
elif iostandard == 'SSTL135':
|
||||
drives = None
|
||||
else:
|
||||
drives = [4, 8, 12, 16]
|
||||
|
||||
|
|
@ -64,7 +72,26 @@ def run():
|
|||
connects = io.StringIO()
|
||||
|
||||
tile_params = []
|
||||
params = []
|
||||
params = {
|
||||
"tiles": [],
|
||||
'INTERNAL_VREF': {},
|
||||
}
|
||||
|
||||
with open(os.path.join(os.getenv('FUZDIR'), 'build', 'iobanks.txt')) as f:
|
||||
iobanks = [int(l.strip()) for l in f]
|
||||
|
||||
params['iobanks'] = iobanks
|
||||
|
||||
if iostandard in ['SSTL135']:
|
||||
for iobank in iobanks:
|
||||
params['INTERNAL_VREF'][iobank] = random.choice(
|
||||
(
|
||||
.600,
|
||||
.675,
|
||||
.75,
|
||||
.90,
|
||||
))
|
||||
|
||||
any_idelay = False
|
||||
for tile, site in gen_sites():
|
||||
p = {}
|
||||
|
|
@ -93,7 +120,10 @@ def run():
|
|||
elif p['type'] == 'OBUF':
|
||||
p['pad_wire'] = 'do[{}]'.format(o_idx)
|
||||
p['iwire'] = luts.get_next_output_net()
|
||||
p['DRIVE'] = random.choice(drives)
|
||||
if drives is not None:
|
||||
p['DRIVE'] = random.choice(drives)
|
||||
else:
|
||||
p['DRIVE'] = None
|
||||
p['SLEW'] = verilog.quote(random.choice(slews))
|
||||
|
||||
o_idx += 1
|
||||
|
|
@ -101,7 +131,10 @@ def run():
|
|||
p['pad_wire'] = 'dio[{}]'.format(io_idx)
|
||||
p['iwire'] = luts.get_next_output_net()
|
||||
p['owire'] = luts.get_next_input_net()
|
||||
p['DRIVE'] = random.choice(drives)
|
||||
if drives is not None:
|
||||
p['DRIVE'] = random.choice(drives)
|
||||
else:
|
||||
p['DRIVE'] = None
|
||||
p['SLEW'] = verilog.quote(random.choice(slews))
|
||||
p['tristate_wire'] = random.choice(
|
||||
('0', luts.get_next_output_net()))
|
||||
|
|
@ -111,7 +144,11 @@ def run():
|
|||
('0', luts.get_next_output_net()))
|
||||
io_idx += 1
|
||||
|
||||
params.append(p)
|
||||
if 'DRIVE' in p:
|
||||
if p['DRIVE'] is not None:
|
||||
p['DRIVE_STR'] = '.DRIVE({}),'.format(p['DRIVE'])
|
||||
else:
|
||||
p['DRIVE_STR'] = ''
|
||||
|
||||
if p['type'] is not None:
|
||||
tile_params.append(
|
||||
|
|
@ -119,9 +156,14 @@ def run():
|
|||
tile, site, p['pad_wire'], iostandard, p['DRIVE'],
|
||||
verilog.unquote(p['SLEW']) if p['SLEW'] else None,
|
||||
verilog.unquote(p['PULLTYPE'])))
|
||||
params['tiles'].append(p)
|
||||
|
||||
write_params(tile_params)
|
||||
|
||||
with open('iobank_vref.csv', 'w') as f:
|
||||
for iobank, vref in params['INTERNAL_VREF'].items():
|
||||
f.write('{},{}\n'.format(iobank, vref))
|
||||
|
||||
print(
|
||||
'''
|
||||
`define N_DI {n_di}
|
||||
|
|
@ -141,7 +183,7 @@ module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N
|
|||
(* KEEP, DONT_TOUCH *)
|
||||
LUT6 dummy_lut();''')
|
||||
|
||||
for p in params:
|
||||
for p in params['tiles']:
|
||||
if p['type'] is None:
|
||||
continue
|
||||
elif p['type'] == 'IBUF':
|
||||
|
|
@ -173,7 +215,7 @@ module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N
|
|||
(* KEEP, DONT_TOUCH *)
|
||||
OBUF #(
|
||||
.IOSTANDARD({IOSTANDARD}),
|
||||
.DRIVE({DRIVE}),
|
||||
{DRIVE_STR}
|
||||
.SLEW({SLEW})
|
||||
) ibuf_{site} (
|
||||
.O({pad_wire}),
|
||||
|
|
@ -186,7 +228,7 @@ module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N
|
|||
(* KEEP, DONT_TOUCH *)
|
||||
IOBUF_INTERMDISABLE #(
|
||||
.IOSTANDARD({IOSTANDARD}),
|
||||
.DRIVE({DRIVE}),
|
||||
{DRIVE_STR}
|
||||
.SLEW({SLEW})
|
||||
) ibuf_{site} (
|
||||
.IO({pad_wire}),
|
||||
|
|
@ -205,7 +247,7 @@ module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N
|
|||
|
||||
print("endmodule")
|
||||
|
||||
with open('params.jl', 'w') as f:
|
||||
with open('params.json', 'w') as f:
|
||||
json.dump(params, f, indent=2)
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue