mirror of https://github.com/openXC7/prjxray.git
Add HCLK (BUFR) fuzzer and solve additional bits in CLK_HROW.
These fuzzer updates are required for use of BUFR for clock dividing. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
parent
ae80db55ad
commit
6f999ed3d1
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@ -0,0 +1,22 @@
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N ?= 50
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include ../fuzzer.mk
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database: build/segbits_hclk_ioi3.db
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build/segbits_hclk_ioi3.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -c 5 -o build/segbits_hclk_ioi3.rdb \
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$(addsuffix /segdata_hclk_ioi3.txt,$(SPECIMENS))
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build/segbits_hclk_ioi3.db: build/segbits_hclk_ioi3.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
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--seg-fn-in build/segbits_hclk_ioi3.rdb \
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--seg-fn-out build/segbits_hclk_ioi3.db
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${XRAY_MASKMERGE} build/mask_hclk_ioi3.db \
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$(addsuffix /segdata_hclk_ioi3.txt,$(SPECIMENS))
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pushdb: database
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${XRAY_MERGEDB} hclk_ioi3 build/segbits_hclk_ioi3.db
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${XRAY_MERGEDB} mask_hclk_ioi3 build/mask_hclk_ioi3.db
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.PHONY: database pushdb
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@ -0,0 +1,4 @@
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32_22 33_18 33_19 33_20 33_21,HCLK_IOI3.BUFR_Y0.BUFR_DIVIDE.BYPASS
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32_17 33_14 33_15 33_16 33_17,HCLK_IOI3.BUFR_Y1.BUFR_DIVIDE.BYPASS
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33_27 33_28 33_29 33_30 33_31,HCLK_IOI3.BUFR_Y2.BUFR_DIVIDE.BYPASS
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32_28 33_23 33_24 33_25 33_26,HCLK_IOI3.BUFR_Y3.BUFR_DIVIDE.BYPASS
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@ -0,0 +1,46 @@
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#!/usr/bin/env python3
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import json
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from prjxray.segmaker import Segmaker
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def bitfilter(frame, bit):
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return True
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def main():
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segmk = Segmaker("design.bits")
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print("Loading tags")
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with open('params.json') as f:
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params = json.load(f)
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for row in params:
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base_name = 'BUFR_Y{}'.format(row['y'])
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segmk.add_tile_tag(
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row['tile'], '{}.IN_USE'.format(base_name), row['IN_USE'])
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if not row['IN_USE']:
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continue
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segmk.add_tile_tag(
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row['tile'], '{}.BUFR_DIVIDE.BYPASS'.format(base_name),
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'"BYPASS"' == row['BUFR_DIVIDE'])
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for opt in range(1, 9):
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if row['BUFR_DIVIDE'] == str(opt):
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segmk.add_tile_tag(
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row['tile'], '{}.BUFR_DIVIDE.D{}'.format(base_name, opt),
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1)
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elif '"BYPASS"' == row['BUFR_DIVIDE']:
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segmk.add_tile_tag(
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row['tile'], '{}.BUFR_DIVIDE.D{}'.format(base_name, opt),
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0)
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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if __name__ == '__main__':
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main()
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@ -0,0 +1,17 @@
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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}
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run
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@ -0,0 +1,149 @@
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import json
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import os
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray.db import Database
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from prjxray import util
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from prjxray.lut_maker import LutMaker
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def gen_sites():
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xy_fun = util.create_xy_fun('BUFR_')
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db = Database(util.get_db_root())
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grid = db.grid()
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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sites = []
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xs = []
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ys = []
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for site, site_type in gridinfo.sites.items():
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if site_type == 'BUFR':
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x, y = xy_fun(site)
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xs.append(x)
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ys.append(y)
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sites.append((site, x, y))
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if not sites:
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continue
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ioi3 = grid.gridinfo_at_loc((loc.grid_x, loc.grid_y - 1))
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assert 'IOI3' in ioi3.tile_type
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if ioi3.tile_type.startswith('R'):
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dx = 1
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else:
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assert ioi3.tile_type.startswith('L')
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dx = -1
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iobs = []
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for dy in (-1, -3, 2, 4):
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iob = grid.gridinfo_at_loc((loc.grid_x + dx, loc.grid_y + dy))
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for site, site_type in iob.sites.items():
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if site_type == 'IOB33M':
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iobs.append(site)
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yield tile_name, min(xs), min(ys), sorted(sites), sorted(iobs)
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def main():
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params_list = []
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num_clocks = 0
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outputs = []
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luts = LutMaker()
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for tile_name, x_min, y_min, sites, iobs in gen_sites():
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ioclks = []
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for iob in iobs:
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ioclk = 'clk_{}'.format(iob)
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ioclks.append(ioclk)
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idx = num_clocks
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num_clocks += 1
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outputs.append(
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'''
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wire {ioclk};
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(* KEEP, DONT_TOUCH, LOC="{site}" *)
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IBUF #(
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.IOSTANDARD("LVCMOS33")
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) ibuf_{site} (
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.I(clks[{idx}]),
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.O({ioclk})
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);'''.format(
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ioclk=ioclk,
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site=iob,
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idx=idx,
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))
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for site, x, y in sites:
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params = {}
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params['tile'] = tile_name
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params['site'] = site
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params['IN_USE'] = random.randint(0, 1)
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params['x'] = x - x_min
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params['y'] = y - y_min
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if params['IN_USE']:
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params['BUFR_DIVIDE'] = random.choice(
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(
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'"BYPASS"',
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'1',
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'2',
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'3',
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'4',
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'5',
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'6',
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'7',
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'8',
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))
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params['I'] = random.choice(ioclks)
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if params['BUFR_DIVIDE'] == '"BYPASS"':
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params['CE'] = '1'
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params['CLR'] = '0'
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else:
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params['CE'] = luts.get_next_output_net()
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params['CLR'] = luts.get_next_output_net()
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outputs.append(
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'''
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFR #(
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.BUFR_DIVIDE({BUFR_DIVIDE})
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) buf_{site} (
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.CE({CE}),
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.CLR({CLR}),
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.I({I})
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);
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'''.format(**params))
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params_list.append(params)
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print(
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'''
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module top(input [{n1}:0] clks);
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'''.format(n1=num_clocks - 1))
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print("""
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(* KEEP, DONT_TOUCH *)
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LUT6 dummy (
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);""")
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for l in luts.create_wires_and_luts():
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print(l)
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for l in outputs:
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print(l)
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print("endmodule")
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with open('params.json', 'w') as f:
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json.dump(params_list, f, indent=2)
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if __name__ == '__main__':
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main()
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@ -38,6 +38,10 @@ def main():
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if dst.startswith('CLK_HROW_CK_MUX_OUT_'):
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clk_list[tile_type].add(src)
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if dst.startswith('CLK_HROW_BOT_R_CK_BUFG_'):
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if 'CASCIN' not in src:
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clk_list[tile_type].add(src)
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
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'clk_hrow', 'clk_hrow_top_r.txt')) as f:
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for l in f:
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@ -55,6 +59,10 @@ def main():
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if dst.startswith('CLK_HROW_CK_MUX_OUT_'):
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clk_list[tile_type].add(src)
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if dst.startswith('CLK_HROW_TOP_R_CK_BUFG_'):
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if 'CASCIN' not in src:
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clk_list[tile_type].add(src)
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print("Loading tags from design.txt.")
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with open("design.txt", "r") as f:
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for line in f:
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