mirror of https://github.com/openXC7/prjxray.git
fuzzers: Add fuzzer for HCLK_IOI3 PIPs
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
This commit is contained in:
Tomasz Michalak
parent
db785ed575
commit
727d5ca377
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@ -0,0 +1,44 @@
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export FUZDIR=$(shell pwd)
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PIP_TYPE?=hclk_ioi3
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PIPLIST_TCL=$(FUZDIR)/hclk_ioi3_pip_list.tcl
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TODO_RE=".*"
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MAKETODO_FLAGS= --sides "" --pip-type ${PIP_TYPE} --seg-type ${PIP_TYPE} --re $(TODO_RE)
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N = 50
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SEGMATCH_FLAGS=-c 3 -m 15 -M 45
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SPECIMENS_DEPS=build/cmt_regions.csv
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A_PIPLIST=hclk_ioi3.txt
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include ../pip_loop.mk
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build/segbits_hclk_ioi3.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o build/segbits_hclk_ioi3.rdb \
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$(shell find build -name segdata_hclk_ioi3.txt)
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build/segbits_hclk_ioi3.db: build/segbits_hclk_ioi3.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
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--seg-fn-in build/segbits_hclk_ioi3.rdb \
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--seg-fn-out build/segbits_hclk_ioi3.db
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# Keep a copy to track iter progress
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cp build/segbits_hclk_ioi3.rdb build/$(ITER)/segbits_hclk_ioi3.rdb
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${XRAY_MASKMERGE} build/mask_hclk_ioi3.db \
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$(shell find build -name segdata_hclk_ioi3.txt)
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database: build/segbits_hclk_ioi3.db
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# Clobber existing .db to eliminate potential conflicts
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cp ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/segbits*.db build/database/${XRAY_DATABASE}
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XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} hclk_ioi3 build/segbits_hclk_ioi3.db
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build/cmt_regions.csv: output_cmt.tcl
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mkdir -p build
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cd build/ && ${XRAY_VIVADO} -mode batch -source ${FUZDIR}/output_cmt.tcl
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pushdb: database
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${XRAY_MERGEDB} hclk_ioi3 build/segbits_hclk_ioi3.db
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${XRAY_MERGEDB} mask_hclk_ioi build/mask_hclk_ioi3.db
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.PHONY: database pushdb
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@ -0,0 +1,3 @@
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# HCLK_IOI interconnect fuzzer
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Solves pips located within the HCLK_IOI switch box.
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@ -0,0 +1,86 @@
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#!/usr/bin/env python3
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from prjxray.segmaker import Segmaker
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import os
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import os.path
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def bitfilter(frame, word):
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if frame < 26:
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return False
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return True
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def main():
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segmk = Segmaker("design.bits")
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tiledata = {}
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pipdata = {}
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ignpip = set()
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tile_ports = {}
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
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'hclk_ioi3', 'hclk_ioi3.txt')) as f:
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for l in f:
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tile_type, dst, src = l.strip().split('.')
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if tile_type not in pipdata:
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pipdata[tile_type] = []
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tile_ports[tile_type] = set()
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pipdata[tile_type].append((src, dst))
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tile_ports[tile_type].add(src)
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tile_ports[tile_type].add(dst)
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print("Loading tags from design.txt.")
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with open("design.txt", "r") as f:
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for line in f:
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tile, pip, src, dst, pnum, pdir = line.split()
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if not tile.startswith('HCLK_IOI3'):
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continue
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pip_prefix, _ = pip.split(".")
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tile_from_pip, tile_type = pip_prefix.split('/')
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assert tile == tile_from_pip
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_, src = src.split("/")
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_, dst = dst.split("/")
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pnum = int(pnum)
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pdir = int(pdir)
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if tile not in tiledata:
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tiledata[tile] = {
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"type": tile_type,
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"pips": set(),
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"srcs": set(),
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"dsts": set()
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}
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tiledata[tile]["pips"].add((src, dst))
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tiledata[tile]["srcs"].add(src)
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tiledata[tile]["dsts"].add(dst)
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if pdir == 0:
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tiledata[tile]["srcs"].add(dst)
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tiledata[tile]["dsts"].add(src)
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if pnum == 1 or pdir == 0:
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ignpip.add((src, dst))
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for tile, pips_srcs_dsts in tiledata.items():
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tile_type = pips_srcs_dsts["type"]
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pips = pips_srcs_dsts["pips"]
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for src, dst in pipdata[tile_type]:
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if (src, dst) in ignpip:
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pass
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elif (src, dst) in pips:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
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elif dst not in tiledata[tile]["dsts"]:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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if __name__ == "__main__":
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main()
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@ -0,0 +1,57 @@
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc write_pip_txtdata {filename} {
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puts "FUZ([pwd]): Writing $filename."
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set fp [open $filename w]
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set nets [get_nets -hierarchical]
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set nnets [llength $nets]
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set neti 0
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foreach net $nets {
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incr neti
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if {($neti % 100) == 0 } {
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puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)"
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}
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foreach pip [get_pips -of_objects $net] {
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set tile [get_tiles -of_objects $pip]
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set src_wire [get_wires -uphill -of_objects $pip]
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set dst_wire [get_wires -downhill -of_objects $pip]
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set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
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set dir_prop [get_property IS_DIRECTIONAL $pip]
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puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
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}
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}
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close $fp
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}
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property IS_ENABLED 0 [get_drc_checks {PDRC-29}]
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set_property IS_ENABLED 0 [get_drc_checks {PDRC-38}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-13}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-123}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-161}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-1575}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-1684}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-1712}]
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set_property IS_ENABLED 0 [get_drc_checks {AVAL-50}]
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set_property IS_ENABLED 0 [get_drc_checks {AVAL-78}]
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set_property IS_ENABLED 0 [get_drc_checks {AVAL-81}]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_pip_txtdata design.txt
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}
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run
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@ -0,0 +1,39 @@
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proc print_tile_pips {tile_type filename} {
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set fp [open $filename w]
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set pips [dict create]
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foreach tile [get_tiles -filter "TYPE == $tile_type"] {
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puts "Dumping PIPs for tile $tile ($tile_type) to $filename."
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foreach pip [lsort [get_pips -of_objects $tile]] {
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set src [get_wires -uphill -of_objects $pip]
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set dst [get_wires -downhill -of_objects $pip]
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# Skip pips with disconnected nodes
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set src_node [get_nodes -of_objects $src]
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if { $src_node == {} } {
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continue
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}
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set dst_node [get_nodes -of_objects $dst]
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if { $dst_node == {} } {
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continue
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}
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if {[llength [get_nodes -uphill -of_objects $dst_node]] > 1} {
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set pip_string "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
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if ![dict exists $pips $pip_string] {
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puts $fp $pip_string
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dict set pips $pip_string 1
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}
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} else {
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puts "Ignoring PIP: $pip"
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}
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}
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}
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close $fp
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}
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create_project -force -part $::env(XRAY_PART) design design
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set_property design_mode PinPlanning [current_fileset]
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open_io_design -name io_1
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print_tile_pips HCLK_IOI3 hclk_ioi3.txt
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@ -0,0 +1,11 @@
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create_project -force -part $::env(XRAY_PART) design design
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set_property design_mode PinPlanning [current_fileset]
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open_io_design -name io_1
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set fp [open "cmt_regions.csv" "w"]
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foreach site_type {MMCME2_ADV PLLE2_ADV BUFHCE IOB33M BUFR BUFMRCE BUFIO ILOGICE3 IDELAYCTRL} {
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foreach site [get_sites -filter "SITE_TYPE == $site_type"] {
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puts $fp "$site,[get_property CLOCK_REGION $site]"
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}
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}
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close $fp
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@ -0,0 +1,457 @@
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""" Emits top.v's for various BUFHCE routing inputs. """
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import os
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray.lut_maker import LutMaker
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from prjxray.db import Database
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from io import StringIO
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CMT_XY_FUN = util.create_xy_fun(prefix='')
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def read_site_to_cmt():
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""" Yields clock sources and which CMT they route within. """
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with open(os.path.join(os.getenv('FUZDIR'), 'build',
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'cmt_regions.csv')) as f:
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for l in f:
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site, cmt = l.strip().split(',')
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yield (site, cmt)
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class ClockSources(object):
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""" Class for tracking clock sources.
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"""
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def __init__(self, limit=14):
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self.sources = {}
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self.source_to_cmt = {}
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self.used_sources_from_cmt = {}
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self.limit = limit
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def add_clock_source(self, source, cmt):
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""" Adds a source from a specific CMT.
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cmt='ANY' indicates that this source can be routed to any CMT.
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"""
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if cmt not in self.sources:
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self.sources[cmt] = []
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self.sources[cmt].append(source)
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self.source_to_cmt[source] = cmt
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def get_random_source(self, cmt, no_repeats=False):
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""" Get a random source that is routable to the specific CMT.
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get_random_source will return a source that is either cmt='ANY',
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cmt equal to the input CMT, or the adjecent CMT.
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"""
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choices = []
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if cmt in self.sources:
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choices.extend(self.sources[cmt])
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random.shuffle(choices)
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for source in choices:
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source_cmt = self.source_to_cmt[source]
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if source_cmt not in self.used_sources_from_cmt:
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self.used_sources_from_cmt[source_cmt] = set()
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if no_repeats and source in self.used_sources_from_cmt[source_cmt]:
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continue
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if len(self.used_sources_from_cmt[source_cmt]) >= self.limit:
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continue
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self.used_sources_from_cmt[source_cmt].add(source)
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return source
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return None
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def main():
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"""
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HCLK_IOI has the following inputs:
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12 (east) BUFH from the right side of the HROW
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12 (west) Bounce PIPs from one BUFH to any of 6 GCLK_BOT and 6 GCLK_TOP
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4 (east) PHSR_PERFCLK (IOCLK_PLL) from HCLK_CLB to input of BUFIO
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8 (4 north and 4 south) BUFR CLR and CE
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2 (south) I2IOCLK to input of BUFR
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2 (north) I2IOCLK to input of BUFR
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2 RCLK IMUX (IMUX0 and IMUX1) choosing input of BUFR
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outputs:
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4 (east) BUFRCLK - from BUFR to HROW
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4 (north) BUFR2IO - from BUFR
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4 (north) IOCLK from BUFIO
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"""
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global_clock_sources = ClockSources()
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cmt_clock_sources = ClockSources()
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cmt_fast_clock_sources = ClockSources(4)
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bufr_clock_sources = ClockSources()
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bufio_clock_sources = ClockSources()
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site_to_cmt = dict(read_site_to_cmt())
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clock_region_limit = dict()
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clock_region_serdes_location = dict()
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db = Database(util.get_db_root())
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grid = db.grid()
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def gen_sites(desired_site_type):
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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for site, site_type in gridinfo.sites.items():
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if site_type == desired_site_type:
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yield tile_name, site
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def serdes_relative_location(tile, site):
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(serdes_loc_x, serdes_loc_y) = grid.loc_of_tilename(tile)
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serdes_clk_reg = site_to_cmt[site]
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for tile_name in sorted(grid.tiles()):
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if 'HCLK_IOI3' in tile_name:
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(hclk_tile_loc_x,
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hclk_tile_loc_y) = grid.loc_of_tilename(tile_name)
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if hclk_tile_loc_x == serdes_loc_x:
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gridinfo = grid.gridinfo_at_loc(
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(hclk_tile_loc_x, hclk_tile_loc_y))
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random_site = next(iter(gridinfo.sites.keys()))
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hclk_clk_reg = site_to_cmt[random_site]
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if hclk_clk_reg == serdes_clk_reg:
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if serdes_loc_y < hclk_tile_loc_y:
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return "TOP"
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elif serdes_loc_y > hclk_tile_loc_y:
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return "BOTTOM"
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else:
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assert False
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clock_region_sites = set()
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def get_clock_region_site(site_type, clk_reg):
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for site_name, reg in site_to_cmt.items():
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if site_name.startswith(site_type) and reg in clk_reg:
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if site_name not in clock_region_sites:
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clock_region_sites.add(site_name)
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return site_name
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print(
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'''
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module top();
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(* KEEP, DONT_TOUCH *)
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LUT6 dummy();
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''')
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luts = LutMaker()
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bufs = StringIO()
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for _, site in gen_sites('MMCME2_ADV'):
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mmcm_clocks = [
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'mmcm_clock_{site}_{idx}'.format(site=site, idx=idx)
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for idx in range(13)
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]
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for idx, clk in enumerate(mmcm_clocks):
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if idx < 4:
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cmt_fast_clock_sources.add_clock_source(clk, site_to_cmt[site])
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else:
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cmt_clock_sources.add_clock_source(clk, site_to_cmt[site])
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print(
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"""
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wire cin1_{site}, cin2_{site}, clkfbin_{site}, {c0}, {c1}, {c2}, {c3}, {c4}, {c5};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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MMCME2_ADV pll_{site} (
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.CLKIN1(cin1_{site}),
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.CLKIN2(cin2_{site}),
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.CLKFBIN(clkfbin_{site}),
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.CLKOUT0({c0}),
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.CLKOUT0B({c4}),
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.CLKOUT1({c1}),
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.CLKOUT1B({c5}),
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.CLKOUT2({c2}),
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.CLKOUT2B({c6}),
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.CLKOUT3({c3}),
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.CLKOUT3B({c7}),
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.CLKOUT4({c8}),
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.CLKOUT5({c9}),
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.CLKOUT6({c10}),
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.CLKFBOUT({c11}),
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.CLKFBOUTB({c12})
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);
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""".format(
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site=site,
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c0=mmcm_clocks[0],
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c1=mmcm_clocks[1],
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c2=mmcm_clocks[2],
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c3=mmcm_clocks[3],
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c4=mmcm_clocks[4],
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c5=mmcm_clocks[5],
|
||||
c6=mmcm_clocks[6],
|
||||
c7=mmcm_clocks[7],
|
||||
c8=mmcm_clocks[8],
|
||||
c9=mmcm_clocks[9],
|
||||
c10=mmcm_clocks[10],
|
||||
c11=mmcm_clocks[11],
|
||||
c12=mmcm_clocks[12],
|
||||
))
|
||||
|
||||
for _, site in gen_sites('PLLE2_ADV'):
|
||||
pll_clocks = [
|
||||
'pll_clock_{site}_{idx}'.format(site=site, idx=idx)
|
||||
for idx in range(7)
|
||||
]
|
||||
|
||||
for clk in pll_clocks:
|
||||
cmt_clock_sources.add_clock_source(clk, site_to_cmt[site])
|
||||
|
||||
print(
|
||||
"""
|
||||
wire cin1_{site}, cin2_{site}, clkfbin_{site}, {c0}, {c1}, {c2}, {c3}, {c4}, {c5}, {c6};
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
PLLE2_ADV pll_{site} (
|
||||
.CLKIN1(cin1_{site}),
|
||||
.CLKIN2(cin2_{site}),
|
||||
.CLKFBIN(clkfbin_{site}),
|
||||
.CLKOUT0({c0}),
|
||||
.CLKOUT1({c1}),
|
||||
.CLKOUT2({c2}),
|
||||
.CLKOUT3({c3}),
|
||||
.CLKOUT4({c4}),
|
||||
.CLKOUT5({c5}),
|
||||
.CLKFBOUT({c6})
|
||||
);
|
||||
""".format(
|
||||
site=site,
|
||||
c0=pll_clocks[0],
|
||||
c1=pll_clocks[1],
|
||||
c2=pll_clocks[2],
|
||||
c3=pll_clocks[3],
|
||||
c4=pll_clocks[4],
|
||||
c5=pll_clocks[5],
|
||||
c6=pll_clocks[6],
|
||||
))
|
||||
|
||||
for tile_name, site in gen_sites('BUFHCE'):
|
||||
print(
|
||||
"""
|
||||
wire I_{site};
|
||||
wire O_{site};
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
BUFHCE buf_{site} (
|
||||
.I(I_{site}),
|
||||
.O(O_{site})
|
||||
);""".format(site=site),
|
||||
file=bufs)
|
||||
global_clock_sources.add_clock_source(
|
||||
'O_{site}'.format(site=site), site_to_cmt[site])
|
||||
|
||||
hclks_used_by_clock_region = {}
|
||||
for cmt in site_to_cmt.values():
|
||||
hclks_used_by_clock_region[cmt] = set()
|
||||
|
||||
def check_hclk_src(src, src_cmt):
|
||||
if len(hclks_used_by_clock_region[src_cmt]
|
||||
) >= 12 and src not in hclks_used_by_clock_region[src_cmt]:
|
||||
return None
|
||||
else:
|
||||
hclks_used_by_clock_region[src_cmt].add(src)
|
||||
return src
|
||||
|
||||
cmt_clks_used_by_clock_region = {}
|
||||
for cmt in site_to_cmt.values():
|
||||
cmt_clks_used_by_clock_region[cmt] = list()
|
||||
|
||||
def check_cmt_clk_src(src, src_clock_region):
|
||||
print(
|
||||
"//src: {}, clk_reg: {}, len {}".format(
|
||||
src, src_clock_region,
|
||||
len(cmt_clks_used_by_clock_region[src_clock_region])))
|
||||
if len(cmt_clks_used_by_clock_region[src_clock_region]) >= 4:
|
||||
return None
|
||||
else:
|
||||
cmt_clks_used_by_clock_region[src_clock_region].append(src)
|
||||
return src
|
||||
|
||||
#Add IDELAYCTRL
|
||||
idelayctrl_in_clock_region = {}
|
||||
for cmt in site_to_cmt.values():
|
||||
idelayctrl_in_clock_region[cmt] = False
|
||||
for _, site in gen_sites('IDELAYCTRL'):
|
||||
if random.random() < 0.5:
|
||||
wire_name = global_clock_sources.get_random_source(
|
||||
site_to_cmt[site], no_repeats=False)
|
||||
if wire_name is None:
|
||||
continue
|
||||
src_cmt = global_clock_sources.source_to_cmt[wire_name]
|
||||
wire_name = check_hclk_src(wire_name, src_cmt)
|
||||
|
||||
if wire_name is None:
|
||||
continue
|
||||
idelayctrl_in_clock_region[src_cmt] = True
|
||||
print(
|
||||
"""
|
||||
assign I_{site} = {clock_source};
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
IDELAYCTRL idelay_ctrl_{site} (
|
||||
.RDY(),
|
||||
.REFCLK(I_{site}),
|
||||
.RST()
|
||||
);""".format(site=site, clock_source=wire_name))
|
||||
|
||||
# Add SERDES driven by BUFH or MMCM
|
||||
for tile, site in gen_sites('ILOGICE3'):
|
||||
wire_name = None
|
||||
clock_region = site_to_cmt[site]
|
||||
if clock_region not in clock_region_limit:
|
||||
# Select serdes limit and relative location per clock region
|
||||
serdes_location = random.choice(["TOP", "BOTTOM", "ANY"])
|
||||
if serdes_location in "ANY":
|
||||
#We want TOP and BOTTOM IGCLK PIPs occupied but leave one slot for IDELAYCTRL
|
||||
if idelayctrl_in_clock_region[clock_region]:
|
||||
clock_region_limit[clock_region] = 0 if random.random(
|
||||
) < 0.2 else 11
|
||||
else:
|
||||
clock_region_limit[clock_region] = 0 if random.random(
|
||||
) < 0.2 else 12
|
||||
else:
|
||||
if idelayctrl_in_clock_region[clock_region]:
|
||||
clock_region_limit[clock_region] = 0 if random.random(
|
||||
) < 0.2 else 5
|
||||
else:
|
||||
clock_region_limit[clock_region] = 0 if random.random(
|
||||
) < 0.2 else 6
|
||||
|
||||
clock_region_serdes_location[clock_region] = serdes_location
|
||||
|
||||
# We reached the limit of hclks in this clock region
|
||||
if clock_region_limit[clock_region] == 0:
|
||||
continue
|
||||
|
||||
# Add a serdes if it's located at the correct side from the HCLK_IOI tile
|
||||
if clock_region_serdes_location[clock_region] not in "ANY" and \
|
||||
serdes_relative_location(tile, site) != clock_region_serdes_location[clock_region]:
|
||||
continue
|
||||
if random.random() > 0.3:
|
||||
wire_name = global_clock_sources.get_random_source(
|
||||
site_to_cmt[site], no_repeats=True)
|
||||
if wire_name is None:
|
||||
continue
|
||||
src_cmt = global_clock_sources.source_to_cmt[wire_name]
|
||||
wire_name = check_hclk_src(wire_name, src_cmt)
|
||||
if wire_name is None:
|
||||
print("//wire is None")
|
||||
continue
|
||||
clock_region_limit[clock_region] -= 1
|
||||
print(
|
||||
"""
|
||||
assign serdes_clk_{site} = {clock_source};""".format(
|
||||
site=site, clock_source=wire_name))
|
||||
else:
|
||||
wire_name = cmt_fast_clock_sources.get_random_source(
|
||||
site_to_cmt[site], no_repeats=False)
|
||||
if wire_name is None:
|
||||
continue
|
||||
src_cmt = cmt_fast_clock_sources.source_to_cmt[wire_name]
|
||||
wire_name = check_cmt_clk_src(wire_name, src_cmt)
|
||||
if wire_name is None:
|
||||
continue
|
||||
bufio_site = get_clock_region_site("BUFIO", clock_region)
|
||||
if bufio_site is None:
|
||||
continue
|
||||
print(
|
||||
"""
|
||||
assign serdes_clk_{serdes_loc} = O_{site};
|
||||
assign I_{site} = {clock_source};
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
BUFIO bufio_{site} (
|
||||
.O(O_{site}),
|
||||
.I(I_{site})
|
||||
);""".format(site=bufio_site, clock_source=wire_name, serdes_loc=site))
|
||||
|
||||
print(
|
||||
"// clock_region: {} {}".format(
|
||||
clock_region, clock_region_serdes_location[clock_region]))
|
||||
print(
|
||||
"""
|
||||
(* KEEP, DONT_TOUCH, LOC = "{loc}" *)
|
||||
ISERDESE2 #(
|
||||
.DATA_RATE("SDR"),
|
||||
.DATA_WIDTH(4),
|
||||
.DYN_CLKDIV_INV_EN("FALSE"),
|
||||
.DYN_CLK_INV_EN("FALSE"),
|
||||
.INIT_Q1(1'b0),
|
||||
.INIT_Q2(1'b0),
|
||||
.INIT_Q3(1'b0),
|
||||
.INIT_Q4(1'b0),
|
||||
.INTERFACE_TYPE("OVERSAMPLE"),
|
||||
.IOBDELAY("NONE"),
|
||||
.NUM_CE(2),
|
||||
.OFB_USED("FALSE"),
|
||||
.SERDES_MODE("MASTER"),
|
||||
.SRVAL_Q1(1'b0),
|
||||
.SRVAL_Q2(1'b0),
|
||||
.SRVAL_Q3(1'b0),
|
||||
.SRVAL_Q4(1'b0)
|
||||
)
|
||||
ISERDESE2_inst_{loc} (
|
||||
.CLK(serdes_clk_{loc}),
|
||||
.CLKB(),
|
||||
.CLKDIV(),
|
||||
.D(1'b0),
|
||||
.DDLY(),
|
||||
.OFB(),
|
||||
.OCLKB(),
|
||||
.RST(),
|
||||
.SHIFTIN1(),
|
||||
.SHIFTIN2()
|
||||
);
|
||||
""".format(loc=site, clock_source=wire_name))
|
||||
|
||||
# BUFRs
|
||||
for _, site in gen_sites('BUFR'):
|
||||
if random.random() < 0.5:
|
||||
wire_name = cmt_fast_clock_sources.get_random_source(
|
||||
site_to_cmt[site], no_repeats=False)
|
||||
if wire_name is None:
|
||||
continue
|
||||
src_cmt = cmt_fast_clock_sources.source_to_cmt[wire_name]
|
||||
wire_name = check_cmt_clk_src(wire_name, src_cmt)
|
||||
if wire_name is None:
|
||||
continue
|
||||
bufr_clock_sources.add_clock_source(
|
||||
'O_{site}'.format(site=site), site_to_cmt[site])
|
||||
print(
|
||||
"""
|
||||
assign I_{site} = {clock_source};
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
BUFR bufr_{site} (
|
||||
.O(O_{site}),
|
||||
.I(I_{site})
|
||||
);""".format(site=site, clock_source=wire_name),
|
||||
file=bufs)
|
||||
|
||||
for _, site in gen_sites('MMCME2_ADV'):
|
||||
wire_name = bufr_clock_sources.get_random_source(
|
||||
site_to_cmt[site], no_repeats=True)
|
||||
|
||||
if wire_name is None:
|
||||
continue
|
||||
print(
|
||||
"""
|
||||
assign cin1_{site} = {wire_name};""".format(
|
||||
site=site, wire_name=wire_name))
|
||||
|
||||
print(bufs.getvalue())
|
||||
|
||||
print("endmodule")
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
main()
|
||||
|
|
@ -95,6 +95,7 @@ $(eval $(call fuzzer,043-clk-rebuf-pips,005-tilegrid))
|
|||
$(eval $(call fuzzer,044-clk-bufg-pips,046-clk-bufg-muxed-pips))
|
||||
$(eval $(call fuzzer,045-hclk-cmt-pips,005-tilegrid))
|
||||
$(eval $(call fuzzer,046-clk-bufg-muxed-pips,005-tilegrid))
|
||||
$(eval $(call fuzzer,047-hclk-ioi-pips,005-tilegrid))
|
||||
$(eval $(call fuzzer,048-int-piplist,005-tilegrid))
|
||||
$(eval $(call fuzzer,049-int-imux-gfan,048-int-piplist))
|
||||
$(eval $(call fuzzer,050-pip-seed,048-int-piplist))
|
||||
|
|
|
|||
|
|
@ -123,6 +123,9 @@ case "$1" in
|
|||
cfg_center_mid)
|
||||
cp "$2" "$tmp1" ;;
|
||||
|
||||
hclk_ioi3)
|
||||
cp "$2" "$tmp1" ;;
|
||||
|
||||
mask_*)
|
||||
db=$XRAY_DATABASE_DIR/$XRAY_DATABASE/$1.db
|
||||
ismask=true
|
||||
|
|
|
|||
Loading…
Reference in New Issue