mirror of https://github.com/openXC7/prjxray.git
Modified 034 to manually force routing through specific PIPs and exclude PPIPs from segdata.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc
parent
844036dd83
commit
89abe7ad47
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@ -1,7 +1,8 @@
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CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT ^ CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN
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CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT ^ CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1
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CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT ^ CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2
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CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT ^ CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1
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CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT ^ CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2
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28_43 29_42 29_43 28_44
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@ -17,25 +17,37 @@ def main():
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tiledata = {}
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pipdata = {}
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ppipdata = {}
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ignpip = set()
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
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'cmt_top', 'cmt_top_l_upper_t.txt')) as f:
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for l in f:
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tile_type, dst, src = l.strip().split('.')
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if tile_type not in pipdata:
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pipdata[tile_type] = []
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# Load PIP lists
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piplists = ['cmt_top_l_upper_t.txt', 'cmt_top_r_upper_t.txt']
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for piplist in piplists:
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build', 'cmt_top', piplist)) as f:
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for l in f:
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tile_type, dst, src = l.strip().split('.')
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if tile_type not in pipdata:
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pipdata[tile_type] = []
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pipdata[tile_type].append((src, dst))
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pipdata[tile_type].append((src, dst))
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
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'cmt_top', 'cmt_top_r_upper_t.txt')) as f:
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for l in f:
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tile_type, dst, src = l.strip().split('.')
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if tile_type not in pipdata:
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pipdata[tile_type] = []
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# Load PPIP lists (to exclude them)
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ppiplists = ['ppips_cmt_top_l_upper_t.db', 'ppips_cmt_top_r_upper_t.db']
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for ppiplist in ppiplists:
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fname = os.path.join(os.getenv('FUZDIR'), '..', '071-ppips', 'build', ppiplist)
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with open(fname, 'r') as f:
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for l in f:
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pip_data, pip_type = l.strip().split()
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pipdata[tile_type].append((src, dst))
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print(pip_data, pip_type)
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if pip_type != 'always':
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continue
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tile_type, dst, src = pip_data.split('.')
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if tile_type not in ppipdata:
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ppipdata[tile_type] = []
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ppipdata[tile_type].append((src, dst))
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print("Loading tags from design.txt.")
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with open("design.txt", "r") as f:
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@ -47,6 +59,8 @@ def main():
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if 'UPPER_B' in tile:
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continue
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if 'LOWER_T' in tile:
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continue
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pip_prefix, _ = pip.split(".")
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tile_from_pip, tile_type = pip_prefix.split('/')
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@ -76,6 +90,11 @@ def main():
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dst.startswith('CMT_TOP_L_UPPER_T_CLK'):
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ignpip.add((src, dst))
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# Ignore pseudo pips
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for ppip in ppipdata[tile_type]:
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if ppip == (src, dst):
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ignpip.add((src, dst, ))
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for tile, pips_srcs_dsts in tiledata.items():
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tile_type = pips_srcs_dsts["type"]
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pips = pips_srcs_dsts["pips"]
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@ -23,6 +23,93 @@ proc write_pip_txtdata {filename} {
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close $fp
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}
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proc load_routes {filename} {
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puts "MANROUTE: Loading routes from $filename"
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set fp [open $filename r]
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foreach line [split [read $fp] "\n"] {
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if {$line eq ""} {
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continue
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}
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puts "MANROUTE: Line: $line"
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# Parse the line
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set fields [split $line " "]
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set tile_name [lindex $fields 0]
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set site_name [lindex $fields 1]
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set pin_name [lindex $fields 2]
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set route_dir [lindex $fields 3]
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set wires [lrange $fields 4 end]
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# Get net
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set tile [get_tiles $tile_name]
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set site [get_sites -of_objects $tile $site_name]
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set pin [get_site_pins -of_objects $site "*/$pin_name"]
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set net [get_nets -quiet -of_objects $pin]
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if {$net eq "" } {
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puts "MANROUTE: No net for pin $pin_name found! Skipping..."
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continue
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}
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# Fixed part read from file
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set route_list {}
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foreach wire $wires {
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lappend route_list [get_nodes -of_objects [get_wires -of_objects $tile "*/$wire"]]
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}
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# Complete the route
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if {$route_dir eq "up"} {
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set node_to [lindex $route_list 0]
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set node_from [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]]
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set rpart [find_routing_path -from $node_from -to $node_to]
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if {$rpart eq ""} {
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puts "MANROUTE: No possible route continuation for net $net"
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continue
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}
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set route_list [concat [lrange $rpart 0 end-1] $route_list]
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}
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if {$route_dir eq "down"} {
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set node_from [lindex $route_list e]
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set node_to [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]]
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set rpart [find_routing_path -from $node_from -to $node_to]
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if {$rpart eq ""} {
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puts "MANROUTE: No possible route continuation for net $net"
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continue
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}
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set route_list [concat $route_list [lrange $rpart 1 end]]
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}
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# Set the fixed route
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puts "MANROUTE: Net: $net, Route: $route_list. routing..."
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regsub -all {{}} $route_list "" route
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set_property FIXED_ROUTE $route $net
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# Route the single net. Needed to detect conflicts when evaluating
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# other ones
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route_design -quiet -nets $net
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# Check for conflicts.
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set status [get_property ROUTE_STATUS $net]
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if {$status ne "ROUTED"} {
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# Ripup and discard the fixed route.
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set_property FIXED_ROUTE "" $net
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route_design -unroute -nets $net
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puts "MANROUTE: Net $net status $status, ripping up..."
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} else {
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set_property IS_ROUTE_FIXED 1 $net
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puts "MANROUTE: Successful manual route for $net"
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}
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}
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close $fp
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}
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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@ -47,7 +134,11 @@ proc run {} {
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set_property IS_ENABLED 0 [get_drc_checks {REQP-13}]
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place_design
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route_design
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load_routes routes.txt
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write_checkpoint -force design_pre_route.dcp
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route_design -preserve
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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@ -39,7 +39,56 @@ def gen_sites():
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for site_name, site_type in gridinfo.sites.items():
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if site_type in ['PLLE2_ADV']:
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phasers = find_phasers_for_pll(grid, loc)
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yield site_name, phasers
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yield tile_name, site_name, phasers
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def get_random_route_from_site_pin(db, tile_name, site_name, site_pin, direction, occupied_wires):
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grid = db.grid()
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tile = db.tilegrid[tile_name]
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tile_type = tile["type"]
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site_type = tile["sites"][site_name]
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tile = db.get_tile_type(tile_type)
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site = [s for s in tile.get_sites() if s.type == site_type][0] # FIXME: find correct site by vivado loc
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# Find site wire
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wire = None
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for pin in site.site_pins:
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if pin.name == site_pin:
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wire = pin.wire
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break
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assert wire is not None
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# Walk randomly over not occupied wires.
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route = []
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while True:
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route.append(wire)
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wires = []
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for pip in tile.pips:
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if direction == "down" and pip.net_from == wire:
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next_wire = pip.net_to
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elif direction == "up" and pip.net_to == wire:
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next_wire = pip.net_from
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else:
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continue
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if next_wire not in occupied_wires:
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wires.append(next_wire)
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if len(wires) == 0:
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break
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wire = random.choice(wires)
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occupied_wires.add(wire)
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# For "up" direction reverse the route.
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if direction == "down":
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return route
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if direction == "up":
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return route[::-1]
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def main():
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@ -50,16 +99,61 @@ module top();
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LUT6 dummy();
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''')
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db = Database(util.get_db_root())
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bufg_count = 0
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for site, phasers in sorted(gen_sites(), key=lambda x: x[0]):
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drive_feedback = random.randint(0, 1)
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clkfbin_src = random.choice(('BUFH', '0', '1', None))
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routes_file = open('routes.txt', 'w')
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if drive_feedback:
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for tile, site, phasers in sorted(gen_sites(), key=lambda x: x[0]):
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# Generate random routes to/from some pins
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routes = {}
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endpoints = {}
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pins = [
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# ('CLKIN1', 'up'),
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# ('CLKIN2', 'up'),
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('CLKFBIN', 'up'),
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('CLKFBOUT', 'down'),
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# ('CLKOUT0', 'down'),
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# ('CLKOUT1', 'down'),
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# ('CLKOUT2', 'down'),
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# ('CLKOUT3', 'down'),
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]
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occupied_wires = set()
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for pin, dir in pins:
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route = get_random_route_from_site_pin(db, tile, site, pin, dir, occupied_wires)
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if route is None:
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endpoints[pin] = ""
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continue
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routes[pin] = (route, dir,)
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endpoints[pin] = route[-1] if dir == 'down' else route[0]
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internal_feedback = endpoints['CLKFBOUT'].endswith('CLKFBIN')
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if internal_feedback:
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del routes['CLKFBIN']
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# Store them in random order so the TCL script will try to route
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# in random order.
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lines = []
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for pin, (route, dir,) in routes.items():
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route_str = " ".join(route)
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lines.append('{} {} {} {} {}\n'.format(tile, site, pin, dir, route_str))
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random.shuffle(lines)
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routes_file.writelines(lines)
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#clkfbin_src = random.choice(('BUFH', '0', '1', 'logic', None))
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clkfbin_src = random.choice(('BUFH', 'logic'))
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if internal_feedback:
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COMPENSATION = "INTERNAL"
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else:
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if clkfbin_src in ['0', '1']:
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if clkfbin_src == 'logic':
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COMPENSATION = 'EXTERNAL'
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else:
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COMPENSATION = "ZHOLD"
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@ -141,30 +235,12 @@ module top();
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.FREQREFCLK(clkout{idx}_{site})
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);""".format(idx=clkout, site=site, phaser_loc=phasers['OUT'][0]))
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drive_bufg = random.randint(0, 1) and bufg_count < 16
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if drive_bufg and clkfbin_src not in ['BUFH', 'BUFR']:
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bufg_count += 1
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print(
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"""
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(* KEEP, DONT_TOUCH *)
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BUFG (
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.I(clkfbout_mult_{site})
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);""".format(site=site))
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if drive_feedback:
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print(
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"""
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assign clkfbin_{site} = clkfbout_mult_{site};
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""".format(site=site))
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if internal_feedback:
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print("""
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assign clkfbin_{site} = clkfbout_mult_{site};
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""".format(site=site))
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else:
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# If CLKFBIN is not using CLKFBOUT feedback, can be connected to:
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# - BUFHCE/BUFR using dedicated path
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# - Switch box clock port
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if clkfbin_src is None:
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pass
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elif clkfbin_src == 'BUFH':
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if clkfbin_src == 'BUFH':
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print(
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"""
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(* KEEP, DONT_TOUCH *)
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@ -172,26 +248,25 @@ module top();
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.I(clkfbout_mult_{site}),
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.O(clkfbin_{site})
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);""".format(site=site))
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elif clkfbin_src == 'BUFR':
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print(
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"""
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(* KEEP, DONT_TOUCH *)
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BUFR (
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.I(clkfbout_mult_{site}),
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.O(clkfbin_{site})
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);""".format(site=site))
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elif clkfbin_src == '0':
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print(
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"""
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assign clkfbin_{site} = 0;
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print("""
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assign clkfbin_{site} = 1'b0;
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""".format(site=site))
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elif clkfbin_src == '1':
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print(
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"""
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assign clkfbin_{site} = 1;
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print("""
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assign clkfbin_{site} = 1'b1;
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""".format(site=site))
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elif clkfbin_src is None:
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pass
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elif clkfbin_src == 'logic':
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print("""
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(* KEEP, DONT_TOUCH *)
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LUT6 # (.INIT(64'h5555555555555555))
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clkfbin_logic_{site} (
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.I0(clkfbout_mult_{site}),
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.O(clkfbin_{site})
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);
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""".format(site=site))
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else:
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assert False, clkfbin_src
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clkin_is_none = False
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@ -199,9 +274,10 @@ module top();
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clkin_src = random.choice((
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'BUFH',
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'BUFR',
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'0',
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'1',
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None,
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# '0',
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# '1',
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'logic',
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# None,
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))
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if clkin == 1 and clkin_is_none and clkin_src is None:
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clkin_src = 'BUFH'
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@ -232,8 +308,16 @@ module top();
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"""
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assign clkin{idx}_{site} = 1;
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""".format(idx=clkin + 1, site=site))
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elif clkin_src == 'logic':
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print("""
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(* KEEP, DONT_TOUCH *)
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LUT6 # (.INIT(64'h5555555555555555))
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clkin{idx}_logic_{site} (
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.O(clkin{idx}_{site})
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);
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""".format(idx=clkin + 1, site=site))
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else:
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assert False, clkfbin_src
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assert False, clkin_src
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print("endmodule")
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@ -84,7 +84,7 @@ $(eval $(call fuzzer,028-fifo-config,005-tilegrid))
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$(eval $(call fuzzer,029-bram-fifo-config,005-tilegrid))
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$(eval $(call fuzzer,030-iob,005-tilegrid))
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$(eval $(call fuzzer,032-cmt-pll,005-tilegrid))
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$(eval $(call fuzzer,034-cmt-pll-pips,005-tilegrid))
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$(eval $(call fuzzer,034-cmt-pll-pips,005-tilegrid,071-ppips))
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$(eval $(call fuzzer,035-iob-ilogic,005-tilegrid))
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$(eval $(call fuzzer,035a-iob-idelay,005-tilegrid))
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$(eval $(call fuzzer,036-iob-ologic,005-tilegrid))
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