mirror of https://github.com/openXC7/prjxray.git
Initial IODELAY fuzzer
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc
parent
db785ed575
commit
bbc908d6d8
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@ -0,0 +1,20 @@
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N := 5
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include ../fuzzer.mk
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database: build/segbits_xiob33.db
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build/segbits_xiob33.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -m 2 -M 2 -o build/segbits_xiob33.rdb $$(find -name segdata_*.txt)
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build/segbits_xiob33.db: build/segbits_xiob33.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@
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${XRAY_MASKMERGE} build/mask_xiob33.db $$(find -name segdata_*.txt)
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pushdb:
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${XRAY_MERGEDB} liob33 build/segbits_xiob33.db
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${XRAY_MERGEDB} riob33 build/segbits_xiob33.db
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${XRAY_MERGEDB} mask_liob33 build/mask_xiob33.db
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${XRAY_MERGEDB} mask_riob33 build/mask_xiob33.db
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.PHONY: todo database pushdb
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#!/usr/bin/env python3
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import json
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from prjxray.segmaker import Segmaker
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from prjxray import util
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from prjxray import verilog
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segmk = Segmaker("design.bits", verbose=True)
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# Load tags
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with open("params.json", "r") as fp:
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data = json.load(fp)
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idelay_types = ["FIXED", "VARIABLE", "VAR_LOAD"]
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delay_srcs = ["IDATAIN", "DATAIN"]
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signal_patterns = ["DATA", "CLOCK"]
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# Output tags
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for params in data:
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loc = verilog.unquote(params["LOC"])
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# Delay type
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value = verilog.unquote(params["IDELAY_TYPE"])
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value = value.replace("_PIPE", "") # VAR_LOAD and VAR_LOAD_PIPE are the same
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for x in idelay_types:
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segmk.add_site_tag(loc, "IDELAY_TYPE_%s" % x, int(value == x))
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# Delay value
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value = int(params["IDELAY_VALUE"])
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for i in range(5):
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segmk.add_site_tag(loc, "IDELAY_VALUE[%01d]" % i, ((value >> i) & 1) != 0)
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# Delay source
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value = verilog.unquote(params["DELAY_SRC"])
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for x in delay_srcs:
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segmk.add_site_tag(loc, "DELAY_SRC_%s" % x, int(value == x))
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# # Signal pattern
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# value = verilog.unquote(params["SIGNAL_PATTERN"])
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# for x in signal_patterns:
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# segmk.add_site_tag(loc, "SIGNAL_PATTERN_%s" % x, int(value == x))
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value = verilog.unquote(params["HIGH_PERFORMANCE_MODE"])
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segmk.add_site_tag(loc, "HIGH_PERFORMANCE_MODE", int(value == "TRUE"))
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value = verilog.unquote(params["CINVCTRL_SEL"])
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segmk.add_site_tag(loc, "CINVCTRL_SEL", int(value == "TRUE"))
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value = verilog.unquote(params["PIPE_SEL"])
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segmk.add_site_tag(loc, "PIPE_SEL", int(value == "TRUE"))
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def bitfilter(frame_idx, bit_idx):
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return True
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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@ -0,0 +1,23 @@
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_param tcl.collectionResultDisplayLimit 0
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set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-79}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-81}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-84}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-85}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-87}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-85}]
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set_property IS_ENABLED 0 [get_drc_checks {AVAL-28}]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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@ -0,0 +1,216 @@
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#!/usr/bin/env python3
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import os, random
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random.seed(int(os.getenv("SEED"), 16))
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import re
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import json
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from prjxray import util
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from prjxray.db import Database
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# =============================================================================
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#todo_file_name = "../todo.txt"
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#def make_todo():
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# if os.path.isfile(file_name):
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# return
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# with open(file_name, "w") as fp:
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# fp.write("IDELAY_TYPE\n")
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# fp.write("IDELAY_VALUE\n")
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# fp.write("DELAY_SRC\n")
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# fp.write("HIGH_PERFORMANCE_MODE\n")
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# fp.write("SIGNAL_PATTERN\n")
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# fp.write("CINVCTRL_SEL\n")
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# fp.write("PIPE_SEL\n")
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def get_loc(name):
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m = re.match("^\S+_X([0-9]+)Y([0-9]+)$", name)
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assert m != None
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x = int(m.group(1))
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y = int(m.group(2))
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return (x, y,)
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def gen_sites():
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db = Database(util.get_db_root())
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grid = db.grid()
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tile_list = []
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for tile_name in sorted(grid.tiles()):
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if "IOB33" not in tile_name or "SING" in tile_name:
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continue
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tile_list.append(tile_name)
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def key(name):
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x, y = get_loc(name)
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return y + x * 10000
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tile_list.sort(key=key)
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for iob_tile_name in tile_list:
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iob_gridinfo = grid.gridinfo_at_loc(grid.loc_of_tilename(iob_tile_name))
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# Find IOI tile adjacent to IOB
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for suffix in ["IOI3", "IOI3_TBYTESRC", "IOI3_TBYTETERM"]:
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try:
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ioi_tile_name = iob_tile_name.replace("IOB33", suffix)
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ioi_gridinfo = grid.gridinfo_at_loc(grid.loc_of_tilename(ioi_tile_name))
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break
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except KeyError:
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pass
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#idelay = [k for k,v in ioi_gridinfo.sites.items() if v == "IDELAYE2"][0]
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iob33s = [k for k,v in iob_gridinfo.sites.items() if v == "IOB33S"][0]
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iob33m = [k for k,v in iob_gridinfo.sites.items() if v == "IOB33M"][0]
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idelay_s = iob33s.replace("IOB", "IDELAY")
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idelay_m = iob33m.replace("IOB", "IDELAY")
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yield iob33m, idelay_m, iob33s, idelay_s
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def run():
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# Get all [LR]IOI3 tiles
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tiles = list(gen_sites())
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# N = 1
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# tiles = tiles[:N] # HACK
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# for t in tiles:
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# print(t)
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# exit(-1)
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# Header
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print("// Tile count: %d" % len(tiles))
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print("// Seed: '%s'" % os.getenv("SEED"))
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print('''
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module top (
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input wire [{N}:0] di,
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output wire [{N}:0] do
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);
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wire [{N}:0] di_buf;
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wire [{N}:0] do_buf;
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'''.format(**{"N": len(tiles) - 1}))
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# LOCes IOBs
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data = []
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for i, sites in enumerate(tiles):
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if random.randint(0, 1):
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iob_i = sites[0]
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iob_o = sites[2]
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idelay = sites[1]
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else:
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iob_i = sites[2]
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iob_o = sites[0]
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idelay = sites[3]
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params = {
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"LOC": "\"" + idelay + "\"",
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"IDELAY_TYPE": "\"" + random.choice(["FIXED", "VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE"]) + "\"",
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"IDELAY_VALUE": random.randint(0, 31),
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"DELAY_SRC": "\"" + random.choice(["IDATAIN", "DATAIN"]) + "\"",
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"HIGH_PERFORMANCE_MODE": "\"" + random.choice(["TRUE", "FALSE"]) + "\"",
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"CINVCTRL_SEL": "\"" + random.choice(["TRUE", "FALSE"]) + "\"",
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"PIPE_SEL": "\"" + random.choice(["TRUE", "FALSE"]) + "\"",
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}
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if params["IDELAY_TYPE"] != "\"VAR_LOAD_PIPE\"":
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params["PIPE_SEL"] = "\"FALSE\""
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# The datasheet says that for these two modes the delay is set to 0
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if params["IDELAY_TYPE"] == "\"VAR_LOAD\"":
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params["IDELAY_VALUE"] = 0
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if params["IDELAY_TYPE"] == "\"VAR_LOAD_PIPE\"":
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params["IDELAY_VALUE"] = 0
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# SIGNAL_PATTERN and HIGH_PERFORMANCE_MODE have no bits
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param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items())
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print('')
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print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i)
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print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i))
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print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o)
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print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i))
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print('mod #(%s) mod_%03d (.I(di_buf[%3d]), .O(do_buf[%3d]));' %
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(param_str, i, i, i))
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data.append(params)
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# Store params
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with open("params.json", "w") as fp:
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json.dump(data, fp, sort_keys=True, indent=1)
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print('''
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// IDELAYCTRL
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(* KEEP, DONT_TOUCH *)
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IDELAYCTRL idelayctrl();
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endmodule
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module mod(
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input wire I,
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output wire O
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);
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parameter LOC = "";
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parameter IDELAY_TYPE = "FIXED";
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parameter IDELAY_VALUE = 0;
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parameter DELAY_SRC = "IDATAIN";
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parameter HIGH_PERFORMANCE_MODE = "TRUE";
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parameter SIGNAL_PATTERN = "DATA";
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parameter CINVCTRL_SEL = "FALSE";
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parameter PIPE_SEL = "FALSE";
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wire x;
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// IDELAY
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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IDELAYE2 #(
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.IDELAY_TYPE(IDELAY_TYPE),
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.IDELAY_VALUE(IDELAY_VALUE),
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.DELAY_SRC(DELAY_SRC),
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.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE),
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.SIGNAL_PATTERN(SIGNAL_PATTERN),
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.CINVCTRL_SEL(CINVCTRL_SEL),
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.PIPE_SEL(PIPE_SEL)
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)
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idelay
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(
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.C(),
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.REGRST(),
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.LD(),
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.CE(),
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.INC(),
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.CINVCTRL(),
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.CNTVALUEIN(),
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.IDATAIN(I),
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.DATAIN(),
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.LDPIPEEN(),
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.DATAOUT(x),
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.CNTVALUEOUT()
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);
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// A LUT
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(* KEEP, DONT_TOUCH *)
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LUT6 #(.INIT(32'hDEADBEEF)) lut (
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.I0(x),
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.I1(x),
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.I2(x),
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.I3(x),
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.I4(x),
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.I5(x),
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.O(O)
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);
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endmodule
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''')
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run()
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