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Added dumping of PPIPs for additional clock routing related tiles. 

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2019-10-23 15:54:57 +02:00
parent 9e77c8bcfd
commit a88e73f65e
1 changed files with 7 additions and 1 deletions
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8
fuzzers/071-ppips/generate.tcl
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@ -95,7 +95,13 @@ foreach tile_type {INT_L INT_R BRAM_INT_INTERFACE_L BRAM_INT_INTERFACE_R \
CLK_HROW_TOP_R CLK_HROW_BOT_R CLK_BUFG_TOP_R CLK_BUFG_BOT_R \
IO_INT_INTERFACE_R IO_INT_INTERFACE_L RIOI3 LIOI3 LIOI3_TBYTETERM \
RIOI3_TBYTETERM LIOI3_TBYTESRC RIOI3_TBYTESRC LIOI3_SING RIOI3_SING \
BRKH_INT HCLK_L HCLK_R} {
BRKH_INT HCLK_L HCLK_R HCLK_CMT \
CMT_TOP_L_UPPER_T CMT_TOP_L_UPPER_B \
CMT_TOP_L_LOWER_T CMT_TOP_L_LOWER_B \
CMT_TOP_R_UPPER_T CMT_TOP_R_UPPER_B \
CMT_TOP_R_LOWER_T CMT_TOP_R_LOWER_B \
INT_INTERFACE_L INT_INTERFACE_R \
HCLK_IOI3 CLK_BUFG_REBUF} {
set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
if {[llength $tiles] != 0} {
set tile [lindex $tiles 0]