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fuzzers: 038-cfg: Add always on bit for Zynq 

Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
This commit is contained in:
Tomasz Michalak 2019-09-09 14:56:11 +02:00
parent cd28a28077
commit f71956225a
2 changed files with 16 additions and 0 deletions
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5
fuzzers/038-cfg/Makefile
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@ -5,6 +5,11 @@ database: build/segbits_cfg.rdb
${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
--seg-fn-in build/segbits_cfg.rdb \
--seg-fn-out build/segbits_cfg.db
# Some of the bits in Zynq seem to be always set
# see https://github.com/SymbiFlow/prjxray/issues/746
ifeq (${XRAY_DATABASE}, zynq7)
python3 add_constant_bits.py build/segbits_cfg.db
endif
build/segbits_cfg.rdb: $(SPECIMENS_OK)

11
fuzzers/038-cfg/add_constant_bits.py Normal file
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@ -0,0 +1,11 @@
import sys
constant_bits = {
"CFG_CENTER_MID.ALWAYS_ON_PROP1": "26_2206",
"CFG_CENTER_MID.ALWAYS_ON_PROP2": "26_2207",
"CFG_CENTER_MID.ALWAYS_ON_PROP3": "27_2205"
}
with open(sys.argv[1], "a") as f:
for bit_name, bit_value in constant_bits.items():
f.write(bit_name + " " + bit_value + "\n")