mirror of https://github.com/openXC7/prjxray.git
Final fixes to the fuzzer.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
parent
c9ce06f688
commit
c880707d27
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@ -4,7 +4,7 @@ include ../fuzzer.mk
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database: build/segbits_xiob33.db
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build/segbits_xiob33.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -m 2 -M 2 -o build/segbits_xiob33.rdb $$(find -name segdata_*.txt)
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${XRAY_SEGMATCH} -m 1 -M 1 -o build/segbits_xiob33.rdb $$(find -name segdata_*.txt)
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build/segbits_xiob33.db: build/segbits_xiob33.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@
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@ -16,5 +16,5 @@ pushdb:
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${XRAY_MERGEDB} mask_liob33 build/mask_xiob33.db
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${XRAY_MERGEDB} mask_riob33 build/mask_xiob33.db
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.PHONY: todo database pushdb
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.PHONY: database pushdb
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@ -11,9 +11,8 @@ segmk = Segmaker("design.bits", verbose=True)
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with open("params.json", "r") as fp:
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data = json.load(fp)
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idelay_types = ["FIXED", "VARIABLE", "VAR_LOAD"]
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idelay_types = ["FIXED", "VARIABLE", "VAR_LOAD"]
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delay_srcs = ["IDATAIN", "DATAIN"]
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signal_patterns = ["DATA", "CLOCK"]
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# Output tags
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for params in data:
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@ -21,31 +20,35 @@ for params in data:
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# Delay type
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value = verilog.unquote(params["IDELAY_TYPE"])
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value = value.replace("_PIPE", "") # VAR_LOAD and VAR_LOAD_PIPE are the same
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value = value.replace(
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"_PIPE", "") # VAR_LOAD and VAR_LOAD_PIPE are the same
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for x in idelay_types:
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segmk.add_site_tag(loc, "IDELAY_TYPE_%s" % x, int(value == x))
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segmk.add_site_tag(loc, "IDELAY_TYPE_%s" % x, int(value == x))
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# Delay value
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value = int(params["IDELAY_VALUE"])
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for i in range(5):
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segmk.add_site_tag(loc, "IDELAY_VALUE[%01d]" % i, ((value >> i) & 1) != 0)
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segmk.add_site_tag(
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loc, "IDELAY_VALUE[%01d]" % i, ((value >> i) & 1) != 0)
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# Delay source
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value = verilog.unquote(params["DELAY_SRC"])
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for x in delay_srcs:
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segmk.add_site_tag(loc, "DELAY_SRC_%s" % x, int(value == x))
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segmk.add_site_tag(loc, "DELAY_SRC_%s" % x, int(value == x))
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value = verilog.unquote(params["HIGH_PERFORMANCE_MODE"])
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segmk.add_site_tag(loc, "HIGH_PERFORMANCE_MODE", int(value == "TRUE"))
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segmk.add_site_tag(loc, "HIGH_PERFORMANCE_MODE", int(value == "TRUE"))
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value = verilog.unquote(params["CINVCTRL_SEL"])
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segmk.add_site_tag(loc, "CINVCTRL_SEL", int(value == "TRUE"))
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segmk.add_site_tag(loc, "CINVCTRL_SEL", int(value == "TRUE"))
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value = verilog.unquote(params["PIPE_SEL"])
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segmk.add_site_tag(loc, "PIPE_SEL", int(value == "TRUE"))
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segmk.add_site_tag(loc, "PIPE_SEL", int(value == "TRUE"))
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def bitfilter(frame_idx, bit_idx):
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return True
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return True
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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@ -11,13 +11,18 @@ from prjxray.db import Database
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# =============================================================================
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def get_loc(name):
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m = re.match("^\S+_X([0-9]+)Y([0-9]+)$", name)
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assert m != None
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x = int(m.group(1))
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y = int(m.group(2))
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return (x, y,)
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return (
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x,
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y,
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)
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def gen_sites():
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db = Database(util.get_db_root())
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@ -36,20 +41,22 @@ def gen_sites():
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tile_list.sort(key=key)
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for iob_tile_name in tile_list:
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iob_gridinfo = grid.gridinfo_at_loc(grid.loc_of_tilename(iob_tile_name))
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iob_gridinfo = grid.gridinfo_at_loc(
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grid.loc_of_tilename(iob_tile_name))
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# Find IOI tile adjacent to IOB
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for suffix in ["IOI3", "IOI3_TBYTESRC", "IOI3_TBYTETERM"]:
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try:
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ioi_tile_name = iob_tile_name.replace("IOB33", suffix)
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ioi_gridinfo = grid.gridinfo_at_loc(grid.loc_of_tilename(ioi_tile_name))
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ioi_gridinfo = grid.gridinfo_at_loc(
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grid.loc_of_tilename(ioi_tile_name))
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break
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except KeyError:
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pass
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#idelay = [k for k,v in ioi_gridinfo.sites.items() if v == "IDELAYE2"][0]
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iob33s = [k for k,v in iob_gridinfo.sites.items() if v == "IOB33S"][0]
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iob33m = [k for k,v in iob_gridinfo.sites.items() if v == "IOB33M"][0]
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iob33s = [k for k, v in iob_gridinfo.sites.items() if v == "IOB33S"][0]
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iob33m = [k for k, v in iob_gridinfo.sites.items() if v == "IOB33M"][0]
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idelay_s = iob33s.replace("IOB", "IDELAY")
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idelay_m = iob33m.replace("IOB", "IDELAY")
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@ -57,14 +64,15 @@ def gen_sites():
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def run():
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# Get all [LR]IOI3 tiles
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tiles = list(gen_sites())
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# Header
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print("// Tile count: %d" % len(tiles))
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print("// Seed: '%s'" % os.getenv("SEED"))
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print('''
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print(
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'''
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module top (
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input wire [{N}:0] di,
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output wire [{N}:0] do
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@ -88,13 +96,21 @@ wire [{N}:0] do_buf;
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idelay = sites[3]
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params = {
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"LOC": "\"" + idelay + "\"",
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"IDELAY_TYPE": "\"" + random.choice(["FIXED", "VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE"]) + "\"",
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"IDELAY_VALUE": random.randint(0, 31),
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"DELAY_SRC": "\"" + random.choice(["IDATAIN", "DATAIN"]) + "\"",
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"HIGH_PERFORMANCE_MODE": "\"" + random.choice(["TRUE", "FALSE"]) + "\"",
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"CINVCTRL_SEL": "\"" + random.choice(["TRUE", "FALSE"]) + "\"",
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"PIPE_SEL": "\"" + random.choice(["TRUE", "FALSE"]) + "\"",
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"LOC":
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"\"" + idelay + "\"",
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"IDELAY_TYPE":
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"\"" + random.choice(
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["FIXED", "VARIABLE", "VAR_LOAD", "VAR_LOAD_PIPE"]) + "\"",
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"IDELAY_VALUE":
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random.randint(0, 31),
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"DELAY_SRC":
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"\"" + random.choice(["IDATAIN", "DATAIN"]) + "\"",
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"HIGH_PERFORMANCE_MODE":
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"\"" + random.choice(["TRUE", "FALSE"]) + "\"",
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"CINVCTRL_SEL":
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"\"" + random.choice(["TRUE", "FALSE"]) + "\"",
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"PIPE_SEL":
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"\"" + random.choice(["TRUE", "FALSE"]) + "\"",
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}
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if params["IDELAY_TYPE"] != "\"VAR_LOAD_PIPE\"":
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@ -115,7 +131,8 @@ wire [{N}:0] do_buf;
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print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i))
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print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o)
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print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i))
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print('mod #(%s) mod_%03d (.I(di_buf[%3d]), .O(do_buf[%3d]));' %
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print(
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'mod #(%s) mod_%03d (.I(di_buf[%3d]), .O(do_buf[%3d]));' %
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(param_str, i, i, i))
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data.append(params)
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@ -124,7 +141,8 @@ wire [{N}:0] do_buf;
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with open("params.json", "w") as fp:
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json.dump(data, fp, sort_keys=True, indent=1)
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print('''
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print(
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'''
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// IDELAYCTRL
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(* KEEP, DONT_TOUCH *)
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IDELAYCTRL idelayctrl();
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@ -190,4 +208,5 @@ LUT6 #(.INIT(32'hDEADBEEF)) lut (
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endmodule
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''')
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run()
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@ -86,6 +86,7 @@ $(eval $(call fuzzer,030-iob,005-tilegrid))
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$(eval $(call fuzzer,032-cmt-pll,005-tilegrid))
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$(eval $(call fuzzer,034-cmt-pll-pips,005-tilegrid))
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$(eval $(call fuzzer,035-iob-ilogic,005-tilegrid))
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$(eval $(call fuzzer,035a-iob-idelay,005-tilegrid))
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$(eval $(call fuzzer,036-iob-ologic,005-tilegrid))
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$(eval $(call fuzzer,038-cfg,005-tilegrid))
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$(eval $(call fuzzer,040-clk-hrow-config,005-tilegrid))
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