Merge pull request #1245 from antmicro/fix_1234

Fix for the lost IOB bits
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litghost 2020-02-18 09:58:46 -08:00 committed by GitHub
commit 66916fb787
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2 changed files with 26 additions and 15 deletions

View File

@ -5,6 +5,7 @@ from prjxray import segmaker
from prjxray import verilog
import os
import json
import csv
def bitfilter(frame, word):
@ -20,20 +21,6 @@ def mk_drive_opt(iostandard, drive):
return '{}.DRIVE.I{}'.format(iostandard, drive)
def skip_broken_tiles(d):
""" Skip tiles that appear to have bits always set.
This is likely caused by a defect?
"""
if os.getenv('XRAY_DATABASE') == 'artix7' and d['tile'] == 'LIOB33_X0Y43':
return True
if os.getenv('XRAY_DATABASE') == 'zynq7' and d['tile'] == 'RIOB33_X31Y43':
return True
return False
def drives_for_iostandard(iostandard):
if iostandard in ['LVTTL', 'LVCMOS18']:
drives = [4, 8, 12, 16, 24]
@ -71,6 +58,14 @@ def main():
for iobank in iobanks:
iobank_iostandards[iobank] = set()
# Load a list of PUDC_B pin function tiles. They are configured differently
# by the vendor tools so need to be skipped
pudc_tiles = set()
with open(os.path.join(os.getenv('FUZDIR'), 'build',
'pudc_sites.csv')) as f:
for l in csv.DictReader(f):
pudc_tiles.add(l["tile"])
print("Loading tags")
segmk = Segmaker("design.bits")
'''
@ -90,7 +85,7 @@ def main():
for d in design['tiles']:
site = d['site']
if skip_broken_tiles(d):
if d['tile'] in pudc_tiles:
continue
if site in diff_pairs:

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@ -17,3 +17,19 @@ foreach site_type { IOB33M IOB33S IDELAYCTRL} {
}
}
close $fp
set fp [open "pudc_sites.csv" "w"]
puts $fp "tile,site"
foreach tile [get_tiles *IOB33*] {
foreach site [get_sites -of_objects $tile] {
set site_type [get_property SITE_TYPE $site]
set pin [get_package_pins -of_objects $site]
set pin_func [get_property PIN_FUNC $pin]
if {[string first "PUDC_B" $pin_func] != -1} {
puts $fp "$tile,$site,$site_type"
}
}
}
close $fp