mirror of https://github.com/openXC7/prjxray.git
Merge pull request #1004 from litghost/ioi3_oclkm
Solve OCLKM pips in IOI3
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commit
c0bb3f5c0a
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@ -2,15 +2,15 @@ export FUZDIR=$(shell pwd)
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PIP_TYPE?=ioi3
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PIPLIST_TCL=$(FUZDIR)/ioi3_pip_list.tcl
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TODO_RE="[LR]IOI3\.(IOI_([IO]LOGIC[01]_CLK(DIV|B)?)|(IOI_OCLK_[01]))\..*"
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EXCLUDE_RE=".*\..*\.(?=IOI_((PHASER)|(OCLK)|(IMUX22_1))).*"
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TODO_RE=".*"
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EXCLUDE_RE=".*((PHASER)|(CLKDIVF)|(CLKDIVP)|(CLKDIVB)|(IOI_ILOGIC[01]_O)|(IOI_OLOGIC[01]_CLKB?\.)|(IOI_IMUX_RC)|(IOI_OLOGIC[01]_[OT]FB)).*"
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MAKETODO_FLAGS=--pip-type ${PIP_TYPE} --seg-type $(PIP_TYPE) --re $(TODO_RE) --sides "xr,xl" --exclude-re $(EXCLUDE_RE)
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N = 40
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A_PIPLIST=lioi3.txt
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SEGMATCH_FLAGS=-c -1 -m 20 -M 50
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SEGMATCH_FLAGS=-c 6 -m 20 -M 50
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SPECIMENS_DEPS=build/cmt_regions.csv
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include ../pip_loop.mk
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@ -69,10 +69,6 @@ def main():
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tiledata[tile]["srcs"].add(dst)
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tiledata[tile]["dsts"].add(src)
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if pnum == 1 or pdir == 0:
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print("Ignoring pip: {}".format(pip), file=log)
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ignpip.add((src, dst))
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for tile, pips_srcs_dsts in tiledata.items():
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tile_type = pips_srcs_dsts["type"]
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@ -81,8 +77,6 @@ def main():
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elif tile_type.startswith('RIOI3'):
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tile_type = 'RIOI3'
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pips = pips_srcs_dsts["pips"]
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for src, dst in pipdata[tile_type]:
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if (src, dst) in ignpip:
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pass
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@ -92,9 +86,18 @@ def main():
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elif (src, dst) in tiledata[tile]["pips"]:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
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elif dst not in tiledata[tile]["dsts"]:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
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disable_pip = True
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internal_feedback = False
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if dst == 'IOI_OCLKM_0' and 'IOI_OCLK_0' in tiledata[tile][
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"dsts"]:
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disable_pip = False
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if dst == 'IOI_OCLKM_1' and 'IOI_OCLK_1' in tiledata[tile][
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"dsts"]:
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disable_pip = False
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if disable_pip:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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@ -2,7 +2,6 @@ proc print_tile_pips {tile_type filename} {
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set fp [open $filename w]
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set pips [dict create]
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foreach tile [get_tiles -filter "TYPE == $tile_type"] {
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puts "Dumping PIPs for tile $tile ($tile_type) to $filename."
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foreach pip [lsort [get_pips -of_objects $tile]] {
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set src [get_wires -uphill -of_objects $pip]
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set dst [get_wires -downhill -of_objects $pip]
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@ -19,7 +18,10 @@ proc print_tile_pips {tile_type filename} {
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continue
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}
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if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} {
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set src_wire [regsub {.*/} $src ""]
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set src_match [regexp {IOI_OCLKM?_[01]} $src_wire]
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if { [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1 || $src_match } {
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set pip_string "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
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if ![dict exists $pips $pip_string] {
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puts $fp $pip_string
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@ -259,6 +259,8 @@ def run():
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.INTERFACE_TYPE({INTERFACE_TYPE}),
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.IS_CLK_INVERTED({IS_CLK_INVERTED}),
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.IS_CLKB_INVERTED({IS_CLKB_INVERTED}),
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.IS_OCLK_INVERTED({IS_OCLK_INVERTED}),
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.IS_OCLKB_INVERTED({IS_OCLKB_INVERTED}),
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.INIT_Q1({INIT_Q1}),
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.INIT_Q2({INIT_Q2}),
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.INIT_Q3({INIT_Q3}),
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@ -275,6 +277,8 @@ def run():
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INTERFACE_TYPE=verilog.quote(INTERFACE_TYPE),
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IS_CLK_INVERTED=random.randint(0, 1),
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IS_CLKB_INVERTED=random.randint(0, 1),
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IS_OCLK_INVERTED=random.randint(0, 1),
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IS_OCLKB_INVERTED=random.randint(0, 1),
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INIT_Q1=random.randint(0, 1),
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INIT_Q2=random.randint(0, 1),
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INIT_Q3=random.randint(0, 1),
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@ -324,10 +328,12 @@ def run():
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"""
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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OSERDESE2 #(
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.IS_CLK_INVERTED({IS_CLK_INVERTED}),
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.DATA_RATE_OQ("SDR"),
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.DATA_RATE_TQ("SDR")
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) oserdes_{site} (
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{ports});""".format(
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IS_CLK_INVERTED=random.randint(0, 1),
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site=ologic_site,
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ports=',\n'.join(ports),
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))
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