mirror of https://github.com/openXC7/prjxray.git
Refactor 037 to capture non-inverted pips.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
Alessandro Comodi
parent
e26a6432a4
commit
b1780e76a0
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@ -22,6 +22,8 @@ SEGBITS=\
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dsp \
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hclk \
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int \
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ioi \
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ioi3 \
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SEGBITS_R=\
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clk_bufg_top \
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@ -7,7 +7,7 @@ TODO_RE="[LR]IOI3\.(IOI_([IO]LOGIC[01]_CLK(DIV|B)?)|(IOI_OCLK_[01]))\.IOI_LEAF_G
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MAKETODO_FLAGS=--pip-type ${PIP_TYPE} --seg-type $(PIP_TYPE) --re $(TODO_RE)
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N = 40
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SEGMATCH_FLAGS=-c 2 -m 15 -M 30
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SEGMATCH_FLAGS=-c -1 -m 15 -M 30
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SPECIMENS_DEPS=build/cmt_regions.csv
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include ../pip_loop.mk
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@ -6,7 +6,7 @@ import os.path
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def bitfilter(frame, word):
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if frame < 26:
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if frame < 28:
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return False
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return True
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@ -91,7 +91,7 @@ def main():
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pass
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elif (src, dst) in tiledata[tile]["pips"]:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
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elif (src, dst) not in tiledata[tile]["pips"]:
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elif dst not in tiledata[tile]["dsts"]:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
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internal_feedback = False
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@ -217,32 +217,27 @@ proc run {} {
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property IS_ENABLED 0 [get_drc_checks {PDRC-25}]
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set_property IS_ENABLED 0 [get_drc_checks {PDRC-39}]
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set_property IS_ENABLED 0 [get_drc_checks {AVAL-74}]
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set_property IS_ENABLED 0 [get_drc_checks {PDRC-26}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-4}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-5}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-13}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-98}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-99}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-123}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-115}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-144}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-1576}]
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set_property IS_ENABLED 0 [get_drc_checks {AVAL-74}]
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set_property IS_ENABLED 0 [get_drc_checks {AVAL-81}]
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set_property IS_ENABLED 0 [get_drc_checks {DRC INBB-1}]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets]
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place_design
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write_checkpoint -force design_before_route.dcp
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route_design
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write_checkpoint -force design_before.dcp
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route_todo
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#route_todo
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route_design
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write_checkpoint -force design_after.dcp
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set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
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set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
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write_bitstream -force design.bit
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write_pip_txtdata design.txt
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}
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@ -1,22 +1,16 @@
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import json
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import io
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import os
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import random
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import math
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import lut_maker
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from prjxray import verilog
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from prjxray import lut_maker
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from prjxray.db import Database
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NOT_INCLUDED_TILES = ['LIOI3_SING', 'RIOI3_SING']
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SITE_TYPES = ['OLOGICE3', 'ILOGICE3']
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REGIONAL_CLOCK_BUFFERS = ['BUFHCE', 'BUFIO']
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GLOBAL_CLOCK_BUFFERS = ['BUFGCTRL']
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CLOCK_BUFFERS = REGIONAL_CLOCK_BUFFERS + GLOBAL_CLOCK_BUFFERS
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MAX_REG_CLK_BUF = 2
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MAX_GLB_CLK_BUF = 24
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CUR_CLK = 0
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@ -42,292 +36,267 @@ def read_site_to_cmt():
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yield (site, cmt)
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def gen_sites(site_types):
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'''
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Generates all sites belonging to `site_types` of
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a desired `tile`
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'''
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def gen_sites():
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''' Return dict of ISERDES/OSERDES locations. '''
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db = Database(util.get_db_root())
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grid = db.grid()
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xy_fun = util.create_xy_fun('\S+')
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tiles = grid.tiles()
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#Randomize tiles
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tiles_list = list(tiles)
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random.shuffle(tiles_list)
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for tile_name in tiles:
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for tile_name in sorted(tiles):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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tile_type = gridinfo.tile_type
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tile = {
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'tile': tile_name,
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'tile_type': tile_type,
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'ioi_sites': {}
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}
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for site_name, site_type in gridinfo.sites.items():
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if site_type in site_types:
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yield tile_type, tile_name, site_type, site_name
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if site_type in SITE_TYPES:
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xy = xy_fun(site_name)
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if xy not in tile['ioi_sites']:
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tile['ioi_sites'][xy] = {}
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tile['ioi_sites'][xy][site_type] = site_name
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yield tile
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def generate_mmcm(site_to_cmt, clock_region):
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mmcm_clocks = None
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class ClockSources(object):
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def __init__(self):
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self.site_to_cmt = dict(read_site_to_cmt())
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for _, _, _, site in gen_sites('MMCME2_ADV'):
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mmcm_region = site_to_cmt[site]
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self.leaf_gclks = {}
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self.ioclks = {}
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self.rclks = {}
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self.selected_leaf_gclks = {}
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self.lut_maker = lut_maker.LutMaker()
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if mmcm_region == clock_region:
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mmcm_clocks = [
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'mmcm_clock_{site}_{idx}'.format(site=site, idx=idx)
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for idx in range(3)
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]
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for cmt in set(self.site_to_cmt.values()):
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self.leaf_gclks[cmt] = []
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self.ioclks[cmt] = []
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self.rclks[cmt] = []
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print(
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"""
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wire {c0}, {c1}, {c2};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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MMCME2_ADV mmcm_{site} (
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.CLKOUT0({c0}),
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.CLKOUT1({c1}),
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.CLKOUT2({c2})
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);""".format(
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def init_clocks(self):
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""" Initialize all IOI clock sources. """
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for site, cmt in self.site_to_cmt.items():
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clk = 'clk_' + site
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if 'BUFHCE' in site:
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print("""
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wire {clk};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFH bufh_{site}(
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.O({clk})
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);
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""".format(
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clk=clk,
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site=site,
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c0=mmcm_clocks[0],
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c1=mmcm_clocks[1],
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c2=mmcm_clocks[2]))
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))
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if not mmcm_clocks:
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return None
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self.leaf_gclks[cmt].append(clk)
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return mmcm_clocks
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if 'BUFIO' in site:
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print("""
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wire {clk};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFIO bufio_{site}(
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.O({clk})
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);
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""".format(
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clk=clk,
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site=site,
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))
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self.ioclks[cmt].append(clk)
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if 'BUFR' in site:
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print("""
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wire {clk};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFR bufr_{site}(
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.O({clk})
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);
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""".format(
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clk=clk,
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site=site,
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))
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self.rclks[cmt].append(clk)
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def generate_glb_clk_buf(clock_regions, mmcm_clocks_dict):
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clk_buf_count = 0
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# Choose 6 leaf_gclks to be used in each CMT.
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for cmt in self.leaf_gclks:
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self.selected_leaf_gclks[cmt] = random.choices(self.leaf_gclks[cmt], k=6)
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clock_signals = []
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def get_clock(self, site, allow_ioclks, allow_rclks, allow_fabric=True, allow_empty=True):
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cmt = self.site_to_cmt[site]
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choices = []
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if allow_fabric:
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choices.append('lut')
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for tile_type, _, site_type, site_name in gen_sites(GLOBAL_CLOCK_BUFFERS):
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if allow_empty:
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choices.append('')
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if clk_buf_count >= MAX_GLB_CLK_BUF:
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break
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choices.extend(self.selected_leaf_gclks[cmt])
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if allow_ioclks:
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choices.extend(self.ioclks[cmt])
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clock_signal = "buf_clk_{site}".format(site=site_name)
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if allow_rclks:
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choices.extend(self.rclks[cmt])
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if site_type == 'BUFGCTRL':
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mmcm_clocks = []
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for clock_region in clock_regions:
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# BUFGCTRL must have the clock coming from the same fabric row
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if ('Y0' in clock_region and tile_type == 'CLK_BUFG_BOT_R'
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) or ('Y0' not in clock_region
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and tile_type == 'CLK_BUFG_TOP_R'):
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mmcm_clocks = mmcm_clocks_dict[clock_region]
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break
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assert mmcm_clocks, "No clock can be produced. Buffer not instantiated"
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print(
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'''
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wire {clk_out};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFG buf_{site} (.I({clk_in}), .O({clk_out}));'''.format(
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clk_in=random.choice(mmcm_clocks),
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clk_out=clock_signal,
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site=site_name))
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else:
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assert False, "The site is somehow corrupted"
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clk_buf_count += 1
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clock_signals.append(clock_signal)
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return clock_signals
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clock = random.choice(choices)
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is_lut = False
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if clock == "lut":
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clock = self.lut_maker.get_next_output_net()
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is_lut = True
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return clock, is_lut
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def generate_reg_clk_buf(site_to_cmt, clock_region, mmcm_clocks, buf_type):
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clk_buf_count = 0
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clock_signals = []
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for tile_type, _, site_type, site_name in gen_sites(
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REGIONAL_CLOCK_BUFFERS):
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buf_region = site_to_cmt[site_name]
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if clk_buf_count >= MAX_REG_CLK_BUF:
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break
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if buf_type != site_type:
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continue
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if buf_region != clock_region:
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continue
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clock_signal = "buf_clk_{site}".format(site=site_name)
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if site_type == 'BUFR':
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print(
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'''
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wire {clk_out};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFR buf_{site} (.I({clk_in}), .O({clk_out}));'''.format(
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clk_in=random.choice(mmcm_clocks),
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clk_out=clock_signal,
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site=site_name))
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elif site_type == 'BUFIO':
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print(
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'''
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wire {clk_out};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFIO buf_{site} (.I({clk_in}), .O({clk_out}));'''.format(
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clk_in=random.choice(mmcm_clocks),
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clk_out=clock_signal,
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site=site_name))
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elif site_type == 'BUFHCE':
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print(
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'''
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wire {clk_out};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFH buf_{site} (.I({clk_in}), .O({clk_out}));'''.format(
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clk_in=random.choice(mmcm_clocks),
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clk_out=clock_signal,
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site=site_name))
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else:
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assert False, "The site is somehow corrupted"
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clk_buf_count += 1
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clock_signals.append(clock_signal)
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return clock_signals
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def get_clock_signal(clock_signals, clock_types):
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'''
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Get a unique clock signals for a specific tile.
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'''
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global CUR_CLK
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clock_signal_string = ''
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is_first_clock = True
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for clock_type in clock_types:
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if random.choice([True, True, False]):
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continue
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clock_signal = clock_signals[CUR_CLK]
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if is_first_clock:
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clock_signal_string += '''
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.{}({})'''.format(clock_type, clock_signal)
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else:
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clock_signal_string += ''',
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.{}({})'''.format(clock_type, clock_signal)
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is_first_clock = False
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CUR_CLK = (CUR_CLK + 1) % MAX_GLB_CLK_BUF
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return clock_signal_string
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def add_port(ports, port, signal):
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ports.append('.{}({})'.format(port, signal))
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def run():
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global CUR_CLK
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# One buffer type for each specimen
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buf_type = random.choice(GLOBAL_CLOCK_BUFFERS)
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site_location = random.choice(['TOP', 'BOT'])
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site_to_cmt = dict(read_site_to_cmt())
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clock_regions = list(dict.fromkeys(site_to_cmt.values()))
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print("module top();")
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clock_mmcm_dict = {}
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clock_signals_dict = {}
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site_types_dict = {}
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clocks = ClockSources()
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clocks.init_clocks()
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# Generate MMCM Clock generator
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for clock_region in clock_regions:
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mmcm_clocks = generate_mmcm(site_to_cmt, clock_region)
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"""
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if mmcm_clocks:
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clock_mmcm_dict[clock_region] = mmcm_clocks
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clock_signals_dict[clock_region] = []
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ISERDESE2 clock sources:
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if buf_type in REGIONAL_CLOCK_BUFFERS:
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clock_signals_dict[clock_region] = generate_reg_clk_buf(
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site_to_cmt, clock_region, mmcm_clocks, buf_type)
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else:
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clock_regions.remove(clock_region)
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CLK/CLKB:
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- Allows LEAF_GCLK, IOCLKS, RCLKS and fabric
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- Dedicated pips
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if buf_type in GLOBAL_CLOCK_BUFFERS:
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clock_signals = generate_glb_clk_buf(clock_regions, clock_mmcm_dict)
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CLKDIV:
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- No dedicated pips, uses fabric clock in.
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for clock_region in clock_regions:
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clock_signals_dict[clock_region] = clock_signals
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site_types_dict[clock_region] = random.choice(SITE_TYPES)
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CLKDIVP:
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- Has pips, MIG only, PHASER or fabric.
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half_column_used_clocks = {}
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OCLK/OCLKB:
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- Allows LEAF_GCLK, IOCLKS, RCLKS and fabric
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- Must match OSERDESE2:CLK/CLKB
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for tile_type, tile_name, site_type, site_name in gen_sites(SITE_TYPES):
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if tile_type in NOT_INCLUDED_TILES:
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OSERDESE2 clock sources:
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CLKDIV/CLKDIVB:
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- Allows LEAF_GCLK and RCLKS and fabric
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- Dedicated pips
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CLKDIVF/CLKDIVFB:
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- Allows LEAF_GCLK and RCLKS and fabric
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- No explicit port, follows CLKDIV/CLKDIVB?
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"""
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output = []
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for tile in gen_sites():
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if tile['tile_type'] in NOT_INCLUDED_TILES:
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continue
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if random.choice([True, True, False]):
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continue
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site_region = site_to_cmt[site_name]
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for xy in tile['ioi_sites']:
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use_iserdes = random.randint(0, 1)
|
||||
use_oserdes = random.randint(0, 1)
|
||||
|
||||
if site_type != site_types_dict[site_region]:
|
||||
continue
|
||||
ilogic_site = tile['ioi_sites'][xy]['ILOGICE3']
|
||||
ologic_site = tile['ioi_sites'][xy]['OLOGICE3']
|
||||
|
||||
clock_signals = clock_signals_dict[site_region]
|
||||
if use_oserdes:
|
||||
oclk, _ = clocks.get_clock(
|
||||
ologic_site,
|
||||
allow_ioclks=True,
|
||||
allow_rclks=True)
|
||||
|
||||
bot_or_top = get_location(site_name, 1)
|
||||
oclkb = oclk
|
||||
else:
|
||||
oclk, is_lut = clocks.get_clock(
|
||||
ilogic_site,
|
||||
allow_ioclks=True,
|
||||
allow_rclks=True)
|
||||
|
||||
half_column = '{}_{}'.format(site_region, get_location(tile_name, 25))
|
||||
if random.randint(0, 1):
|
||||
oclkb = oclk
|
||||
else:
|
||||
oclkb, _ = clocks.get_clock(
|
||||
ilogic_site,
|
||||
allow_ioclks=True,
|
||||
allow_rclks=True,
|
||||
allow_fabric=not is_lut)
|
||||
|
||||
if half_column not in half_column_used_clocks:
|
||||
half_column_used_clocks[half_column] = {
|
||||
'TOP': {
|
||||
'ILOGIC':
|
||||
get_clock_signal(clock_signals, ['CLK', 'CLKB', 'CLKDIV']),
|
||||
'OLOGIC':
|
||||
get_clock_signal(clock_signals, ['CLK', 'CLKDIV'])
|
||||
},
|
||||
'BOT': {
|
||||
'ILOGIC':
|
||||
get_clock_signal(clock_signals, ['CLK', 'CLKB', 'CLKDIV']),
|
||||
'OLOGIC':
|
||||
get_clock_signal(clock_signals, ['CLK', 'CLKDIV'])
|
||||
}
|
||||
}
|
||||
if use_iserdes:
|
||||
DATA_RATE = random.choice(['DDR', 'SDR'])
|
||||
ports = []
|
||||
|
||||
if site_type == 'ILOGICE3':
|
||||
print(
|
||||
'''
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site_name}" *)
|
||||
ISERDESE2 #(
|
||||
.DATA_RATE("SDR")
|
||||
) iserdes_{site_name} ({clk});'''.format(
|
||||
site_name=site_name,
|
||||
clk=half_column_used_clocks[half_column][bot_or_top]
|
||||
['ILOGIC']))
|
||||
elif site_type == 'OLOGICE3':
|
||||
print(
|
||||
'''
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site_name}" *)
|
||||
OSERDESE2 #(
|
||||
.DATA_RATE_OQ("SDR"),
|
||||
.DATA_RATE_TQ("SDR")
|
||||
) oserdes_{site_name} ({clk});'''.format(
|
||||
site_name=site_name,
|
||||
clk=half_column_used_clocks[half_column][bot_or_top]
|
||||
['OLOGIC']))
|
||||
clk, is_lut = clocks.get_clock(
|
||||
ilogic_site,
|
||||
allow_ioclks=True,
|
||||
allow_rclks=True,
|
||||
allow_empty=DATA_RATE=='SDR')
|
||||
if random.randint(0, 1):
|
||||
clkb = clk
|
||||
else:
|
||||
clkb, _ = clocks.get_clock(
|
||||
ilogic_site,
|
||||
allow_ioclks=True,
|
||||
allow_rclks=True,
|
||||
allow_empty=DATA_RATE=='SDR')
|
||||
|
||||
add_port(ports, 'CLK', clk)
|
||||
add_port(ports, 'CLKB', clkb)
|
||||
add_port(ports, 'OCLK', oclk)
|
||||
add_port(ports, 'OCLKB', oclkb)
|
||||
|
||||
output.append("""
|
||||
(* KEEP, DONT_TOUCH, LOC="{site}" *)
|
||||
ISERDESE2 #(
|
||||
.DATA_RATE({DATA_RATE}),
|
||||
.INTERFACE_TYPE("MEMORY_QDR"),
|
||||
.IS_CLK_INVERTED({IS_CLK_INVERTED}),
|
||||
.IS_CLKB_INVERTED({IS_CLKB_INVERTED})
|
||||
) iserdes_{site}(
|
||||
{ports});""".format(
|
||||
site=ilogic_site,
|
||||
ports=',\n'.join(ports),
|
||||
DATA_RATE=verilog.quote(DATA_RATE),
|
||||
IS_CLK_INVERTED=random.randint(0, 1),
|
||||
IS_CLKB_INVERTED=random.randint(0, 1),
|
||||
))
|
||||
|
||||
if use_oserdes:
|
||||
ports = []
|
||||
|
||||
add_port(ports, 'CLKDIV', clocks.get_clock(
|
||||
ologic_site,
|
||||
allow_ioclks=False,
|
||||
allow_rclks=True,
|
||||
)[0])
|
||||
|
||||
add_port(ports, 'CLK', oclk)
|
||||
|
||||
output.append("""
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
OSERDESE2 #(
|
||||
.DATA_RATE_OQ("SDR"),
|
||||
.DATA_RATE_TQ("SDR")
|
||||
) oserdes_{site} (
|
||||
{ports});""".format(
|
||||
site=ologic_site,
|
||||
ports=',\n'.join(ports),
|
||||
))
|
||||
|
||||
for s in clocks.lut_maker.create_wires_and_luts():
|
||||
print(s)
|
||||
|
||||
for s in output:
|
||||
print(s)
|
||||
|
||||
print("endmodule")
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue