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036-ologic: add IN_USE oserdes 

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi 2019-07-25 18:46:42 +02:00
parent 4fd53f65a8
commit fec82e9818
3 changed files with 19 additions and 7 deletions
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9
fuzzers/036-iob-ologic/generate.py
View File

@ -37,6 +37,8 @@ def main():
handle_data_width(segmk, d)
segmk.add_site_tag(site, 'OSERDESE.IN_USE', d['use_oserdese2'])
if d['use_oserdese2']:
segmk.add_site_tag(site, 'OQUSED', 1)
if 'SRTYPE' in d:
@ -60,9 +62,10 @@ def main():
segmk.add_site_tag(site, 'Z' + opt, 1 ^ d[opt])
for opt in ['CLK', 'CLKDIV']:
k = 'IS_{}_INVERTED'.format(opt)
segmk.add_site_tag(site, k, d[k])
segmk.add_site_tag(site, 'ZINV_{}'.format(opt), 1 ^ d[k])
if d['{}_USED'.format(opt)]:
k = 'IS_{}_INVERTED'.format(opt)
segmk.add_site_tag(site, k, d[k])
segmk.add_site_tag(site, 'ZINV_{}'.format(opt), 1 ^ d[k])
for idx in range(4):
k = 'IS_T{}_INVERTED'.format(idx + 1)

1
fuzzers/036-iob-ologic/generate.tcl
View File

@ -86,6 +86,7 @@ proc run {} {
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
set_property IS_ENABLED 0 [get_drc_checks {REQP-79}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-144}]
write_checkpoint -force design_pre_place.dcp

16
fuzzers/036-iob-ologic/top.py
View File

@ -103,6 +103,16 @@ def use_oserdese2(p, luts, connects):
p['IS_CLK_INVERTED'] = random.randint(0, 1)
p['IS_CLKDIV_INVERTED'] = random.randint(0, 1)
clk_connections = ''
p['CLK_USED'] = random.randint(0, 1)
p['CLKDIV_USED'] = random.randint(0, 1)
if p['CLK_USED']:
clk_connections += '''
.CLK({}),'''.format(luts.get_next_output_net())
if p['CLKDIV_USED']:
clk_connections += '''
.CLKDIV({}),'''.format(luts.get_next_output_net())
print(
'''
(* KEEP, DONT_TOUCH, LOC = "{ologic_loc}" *)
@ -134,8 +144,7 @@ def use_oserdese2(p, luts, connects):
.OQ({owire}),
{TFB}
{TQ}
.CLK({clknet}),
.CLKDIV({clkdivnet}),
{clk_connections}
.D1({d1net}),
.D2({d2net}),
.D3({d3net}),
@ -152,8 +161,7 @@ def use_oserdese2(p, luts, connects):
.T4({t4net}),
.TCE({tcenet})
);'''.format(
clknet=luts.get_next_output_net(),
clkdivnet=luts.get_next_output_net(),
clk_connections=clk_connections,
rstnet=luts.get_next_output_net(),
d1net=luts.get_next_output_net(),
d2net=luts.get_next_output_net(),