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Refactor 037 to remove some unstable pips. 

This does lose the IMUX->OCLKM pip, but I believe that is okay. That pip
was returning an incorrect solution anyways.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2019-08-02 10:34:21 -07:00
parent ae80db55ad
commit a08cd04aa5
3 changed files with 32 additions and 14 deletions
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13
fuzzers/037-iob-pips/Makefile
View File

@ -3,21 +3,28 @@ PIP_TYPE?=ioi3
PIPLIST_TCL=$(FUZDIR)/ioi3_pip_list.tcl
TODO_RE=".*"
EXCLUDE_RE=".*((PHASER)|(CLKDIVF)|(CLKDIVP)|(CLKDIVB)|(IOI_ILOGIC[01]_O)|(IOI_OLOGIC[01]_CLKB?\.)|(IOI_IMUX_RC)|(IOI_OLOGIC[01]_[OT]FB)).*"
EXCLUDE_RE=".*((PHASER)|(CLKDIVF)|(CLKDIVP)|(CLKDIVB)|(IOI_ILOGIC[01]_O)|(IOI_OLOGIC[01]_CLKB?\.)|(IOI_IMUX_RC)|(IOI_OLOGIC[01]_[OT]FB)|(OCLKM.*IMUX31)|(IOI_ILOGIC0_CLKB\.IOI_IMUX22_1)).*"
MAKETODO_FLAGS=--pip-type ${PIP_TYPE} --seg-type $(PIP_TYPE) --re $(TODO_RE) --sides "xr,xl" --exclude-re $(EXCLUDE_RE)
N = 40
A_PIPLIST=lioi3.txt
SEGMATCH_FLAGS=-c 6 -m 20 -M 50
SPECIMENS_DEPS=build/cmt_regions.csv
include ../pip_loop.mk
SIX_BIT_PIPS="OLOGIC[01]_CLKDIV"
build/segbits_ioi3_x.rdb: $(SPECIMENS_OK)
${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o build/segbits_ioi3_x.rdb \
# Most pips are 3 bits, force a 3 bit solution
${XRAY_SEGMATCH} -c 3 -m 20 -M 50 -o build/segbits_ioi3_x_match_3.rdb \
$(shell find build -name segdata_lioi3*.txt) $(shell find build -name segdata_rioi3*.txt)
# Some are 6 bit solutions, solve for 6 bits and merge respectively
${XRAY_SEGMATCH} -c 6 -m 20 -M 50 -o build/segbits_ioi3_x_match_6.rdb \
$(shell find build -name segdata_lioi3*.txt) $(shell find build -name segdata_rioi3*.txt)
grep -v ${SIX_BIT_PIPS} build/segbits_ioi3_x_match_3.rdb > build/segbits_ioi3_x.rdb
grep ${SIX_BIT_PIPS} build/segbits_ioi3_x_match_6.rdb >> build/segbits_ioi3_x.rdb
RDBS = build/segbits_ioi3_x.rdb

1
fuzzers/037-iob-pips/generate.tcl
View File

@ -38,6 +38,7 @@ proc run {} {
set_property IS_ENABLED 0 [get_drc_checks {REQP-13}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-98}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-99}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-105}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-115}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-144}]

32
fuzzers/037-iob-pips/top.py
View File

@ -210,11 +210,16 @@ def run():
if random.randint(0, 1):
oclkb = oclk
else:
oclkb, _ = clocks.get_clock(
ilogic_site,
allow_ioclks=True,
allow_rclks=True,
allow_fabric=not is_lut)
if random.randint(0, 1):
oclkb, _ = clocks.get_clock(
ilogic_site,
allow_ioclks=True,
allow_rclks=True,
allow_fabric=not is_lut)
else:
# Explicitly provide IMUX stimulus to resolve IMUX pips
oclk = random.randint(0, 1)
oclkb = random.randint(0, 1)
DATA_RATE = random.choice(['DDR', 'SDR'])
clk, is_lut = clocks.get_clock(
@ -226,12 +231,17 @@ def run():
clkb = clk
else:
clkb = clk
while clkb == clk:
clkb, _ = clocks.get_clock(
ilogic_site,
allow_ioclks=True,
allow_rclks=True,
allow_empty=False)
if random.randint(0, 1):
while clkb == clk:
clkb, _ = clocks.get_clock(
ilogic_site,
allow_ioclks=True,
allow_rclks=True,
allow_empty=False)
else:
# Explicitly provide IMUX stimulus to resolve IMUX pips
clk = random.randint(0, 1)
clkb = random.randint(0, 1)
if ilogic_site_type is None:
pass