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240
.github/kokoro/ctest2junit.xsl vendored
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@ -1,120 +1,120 @@
<xsl:stylesheet xmlns:xsl="http://www.w3.org/1999/XSL/Transform" version="1.0">
<xsl:output method="xml" indent="yes"/>
<xsl:template match="/Site">
<xsl:variable name="Name"><xsl:value-of select="@Name"/></xsl:variable>
<xsl:variable name="Hostname"><xsl:value-of select="@Hostname"/></xsl:variable>
<xsl:variable name="TestCount"><xsl:value-of select="count(//TestList/Test)"/> </xsl:variable>
<xsl:variable name="ErrorCount"><xsl:value-of select="count(//TestList/Test[@Status='error'])"/> </xsl:variable>
<xsl:variable name="FailureCount"><xsl:value-of select="count(//Testing/Test[@Status='failed'])"/> </xsl:variable>
<testsuite name="{$Name}" hostname="{$Hostname}" errors="0" failures="{$FailureCount}" tests="{$TestCount}">
<xsl:variable name="BuildName"><xsl:value-of select="@BuildName"/></xsl:variable>
<xsl:variable name="BuildStamp"><xsl:value-of select="@BuildStamp"/></xsl:variable>
<xsl:variable name="Generator"><xsl:value-of select="@Generator"/></xsl:variable>
<xsl:variable name="CompilerName"><xsl:value-of select="@CompilerName"/></xsl:variable>
<xsl:variable name="OSName"><xsl:value-of select="@OSName"/></xsl:variable>
<xsl:variable name="OSRelease"><xsl:value-of select="@OSRelease"/></xsl:variable>
<xsl:variable name="OSVersion"><xsl:value-of select="@OSVersion"/></xsl:variable>
<xsl:variable name="OSPlatform"><xsl:value-of select="@OSPlatform"/></xsl:variable>
<xsl:variable name="Is64Bits"><xsl:value-of select="@Is64Bits"/></xsl:variable>
<xsl:variable name="VendorString"><xsl:value-of select="@VendorString"/></xsl:variable>
<xsl:variable name="VendorID"><xsl:value-of select="@VendorID"/></xsl:variable>
<xsl:variable name="FamilyID"><xsl:value-of select="@FamilyID"/></xsl:variable>
<xsl:variable name="ModelID"><xsl:value-of select="@ModelID"/></xsl:variable>
<xsl:variable name="ProcessorCacheSize"><xsl:value-of select="@ProcessorCacheSize"/></xsl:variable>
<xsl:variable name="NumberOfLogicalCPU"><xsl:value-of select="@NumberOfLogicalCPU"/></xsl:variable>
<xsl:variable name="NumberOfPhysicalCPU"><xsl:value-of select="@NumberOfPhysicalCPU"/></xsl:variable>
<xsl:variable name="TotalVirtualMemory"><xsl:value-of select="@TotalVirtualMemory"/></xsl:variable>
<xsl:variable name="TotalPhysicalMemory"><xsl:value-of select="@TotalPhysicalMemory"/></xsl:variable>
<xsl:variable name="LogicalProcessorsPerPhysical"><xsl:value-of select="@LogicalProcessorsPerPhysical"/></xsl:variable>
<xsl:variable name="ProcessorClockFrequency"><xsl:value-of select="@ProcessorClockFrequency"/></xsl:variable>
<properties>
<property name="BuildName" value="{$BuildName}" />
<property name="BuildStamp" value="{$BuildStamp}" />
<property name="Name" value="{$Name}" />
<property name="Generator" value="{$Generator}" />
<property name="CompilerName" value="{$CompilerName}" />
<property name="OSName" value="{$OSName}" />
<property name="Hostname" value="{$Hostname}" />
<property name="OSRelease" value="{$OSRelease}" />
<property name="OSVersion" value="{$OSVersion}" />
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<property name="Is64Bits" value="{$Is64Bits}" />
<property name="VendorString" value="{$VendorString}" />
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<property name="ModelID" value="{$ModelID}" />
<property name="ProcessorCacheSize" value="{$ProcessorCacheSize}" />
<property name="NumberOfLogicalCPU" value="{$NumberOfLogicalCPU}" />
<property name="NumberOfPhysicalCPU" value="{$NumberOfPhysicalCPU}" />
<property name="TotalVirtualMemory" value="{$TotalVirtualMemory}" />
<property name="TotalPhysicalMemory" value="{$TotalPhysicalMemory}" />
<property name="LogicalProcessorsPerPhysical" value="{$LogicalProcessorsPerPhysical}" />
<property name="ProcessorClockFrequency" value="{$ProcessorClockFrequency}" />
</properties>
<xsl:apply-templates select="Testing/Test"/>
<system-out>
BuildName: <xsl:value-of select="$BuildName" />
BuildStamp: <xsl:value-of select="$BuildStamp" />
Name: <xsl:value-of select="$Name" />
Generator: <xsl:value-of select="$Generator" />
CompilerName: <xsl:value-of select="$CompilerName" />
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Hostname: <xsl:value-of select="$Hostname" />
OSRelease: <xsl:value-of select="$OSRelease" />
OSVersion: <xsl:value-of select="$OSVersion" />
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Is64Bits: <xsl:value-of select="$Is64Bits" />
VendorString: <xsl:value-of select="$VendorString" />
VendorID: <xsl:value-of select="$VendorID" />
FamilyID: <xsl:value-of select="$FamilyID" />
ModelID: <xsl:value-of select="$ModelID" />
ProcessorCacheSize: <xsl:value-of select="$ProcessorCacheSize" />
NumberOfLogicalCPU: <xsl:value-of select="$NumberOfLogicalCPU" />
NumberOfPhysicalCPU: <xsl:value-of select="$NumberOfPhysicalCPU" />
TotalVirtualMemory: <xsl:value-of select="$TotalVirtualMemory" />
TotalPhysicalMemory: <xsl:value-of select="$TotalPhysicalMemory" />
LogicalProcessorsPerPhysical: <xsl:value-of select="$LogicalProcessorsPerPhysical" />
ProcessorClockFrequency: <xsl:value-of select="$ProcessorClockFrequency" />
</system-out>
</testsuite>
</xsl:template>
<xsl:template match="Testing/Test">
<xsl:variable name="testcasename"><xsl:value-of select= "Name"/></xsl:variable>
<xsl:variable name="testclassname"><xsl:value-of select= " concat('this', substring(Path,2))"/></xsl:variable>
<xsl:variable name="exectime">
<xsl:for-each select="Results/NamedMeasurement">
<xsl:if test="@name = 'Execution Time'">
<xsl:value-of select="."/>
</xsl:if>
</xsl:for-each>
</xsl:variable>
<testcase name="{$testcasename}" classname="{$testclassname}" time="{$exectime}">
<xsl:if test="@Status = 'passed'">
</xsl:if>
<xsl:if test="@Status = 'failed'">
<xsl:variable name="failtype">
<xsl:for-each select="Results/NamedMeasurement">
<xsl:if test="@name = 'Exit Code'">
<xsl:value-of select="."/>
</xsl:if>
</xsl:for-each>
</xsl:variable>
<xsl:variable name="failcode">
<xsl:for-each select="Results/NamedMeasurement">
<xsl:if test="@name = 'Exit Value'">
<xsl:value-of select="."/>
</xsl:if>
</xsl:for-each>
</xsl:variable>
<failure message="{$failtype} ({$failcode})"><xsl:value-of select="Results/Measurement/Value/text()" /></failure>
</xsl:if>
<xsl:if test="@Status = 'notrun'">
<skipped><xsl:value-of select="Results/Measurement/Value/text()" /></skipped>
</xsl:if>
</testcase>
</xsl:template>
</xsl:stylesheet>
<xsl:stylesheet xmlns:xsl="http://www.w3.org/1999/XSL/Transform" version="1.0">
<xsl:output method="xml" indent="yes"/>
<xsl:template match="/Site">
<xsl:variable name="Name"><xsl:value-of select="@Name"/></xsl:variable>
<xsl:variable name="Hostname"><xsl:value-of select="@Hostname"/></xsl:variable>
<xsl:variable name="TestCount"><xsl:value-of select="count(//TestList/Test)"/> </xsl:variable>
<xsl:variable name="ErrorCount"><xsl:value-of select="count(//TestList/Test[@Status='error'])"/> </xsl:variable>
<xsl:variable name="FailureCount"><xsl:value-of select="count(//Testing/Test[@Status='failed'])"/> </xsl:variable>
<testsuite name="{$Name}" hostname="{$Hostname}" errors="0" failures="{$FailureCount}" tests="{$TestCount}">
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<xsl:variable name="BuildStamp"><xsl:value-of select="@BuildStamp"/></xsl:variable>
<xsl:variable name="Generator"><xsl:value-of select="@Generator"/></xsl:variable>
<xsl:variable name="CompilerName"><xsl:value-of select="@CompilerName"/></xsl:variable>
<xsl:variable name="OSName"><xsl:value-of select="@OSName"/></xsl:variable>
<xsl:variable name="OSRelease"><xsl:value-of select="@OSRelease"/></xsl:variable>
<xsl:variable name="OSVersion"><xsl:value-of select="@OSVersion"/></xsl:variable>
<xsl:variable name="OSPlatform"><xsl:value-of select="@OSPlatform"/></xsl:variable>
<xsl:variable name="Is64Bits"><xsl:value-of select="@Is64Bits"/></xsl:variable>
<xsl:variable name="VendorString"><xsl:value-of select="@VendorString"/></xsl:variable>
<xsl:variable name="VendorID"><xsl:value-of select="@VendorID"/></xsl:variable>
<xsl:variable name="FamilyID"><xsl:value-of select="@FamilyID"/></xsl:variable>
<xsl:variable name="ModelID"><xsl:value-of select="@ModelID"/></xsl:variable>
<xsl:variable name="ProcessorCacheSize"><xsl:value-of select="@ProcessorCacheSize"/></xsl:variable>
<xsl:variable name="NumberOfLogicalCPU"><xsl:value-of select="@NumberOfLogicalCPU"/></xsl:variable>
<xsl:variable name="NumberOfPhysicalCPU"><xsl:value-of select="@NumberOfPhysicalCPU"/></xsl:variable>
<xsl:variable name="TotalVirtualMemory"><xsl:value-of select="@TotalVirtualMemory"/></xsl:variable>
<xsl:variable name="TotalPhysicalMemory"><xsl:value-of select="@TotalPhysicalMemory"/></xsl:variable>
<xsl:variable name="LogicalProcessorsPerPhysical"><xsl:value-of select="@LogicalProcessorsPerPhysical"/></xsl:variable>
<xsl:variable name="ProcessorClockFrequency"><xsl:value-of select="@ProcessorClockFrequency"/></xsl:variable>
<properties>
<property name="BuildName" value="{$BuildName}" />
<property name="BuildStamp" value="{$BuildStamp}" />
<property name="Name" value="{$Name}" />
<property name="Generator" value="{$Generator}" />
<property name="CompilerName" value="{$CompilerName}" />
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<property name="Hostname" value="{$Hostname}" />
<property name="OSRelease" value="{$OSRelease}" />
<property name="OSVersion" value="{$OSVersion}" />
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<property name="Is64Bits" value="{$Is64Bits}" />
<property name="VendorString" value="{$VendorString}" />
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<property name="FamilyID" value="{$FamilyID}" />
<property name="ModelID" value="{$ModelID}" />
<property name="ProcessorCacheSize" value="{$ProcessorCacheSize}" />
<property name="NumberOfLogicalCPU" value="{$NumberOfLogicalCPU}" />
<property name="NumberOfPhysicalCPU" value="{$NumberOfPhysicalCPU}" />
<property name="TotalVirtualMemory" value="{$TotalVirtualMemory}" />
<property name="TotalPhysicalMemory" value="{$TotalPhysicalMemory}" />
<property name="LogicalProcessorsPerPhysical" value="{$LogicalProcessorsPerPhysical}" />
<property name="ProcessorClockFrequency" value="{$ProcessorClockFrequency}" />
</properties>
<xsl:apply-templates select="Testing/Test"/>
<system-out>
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BuildStamp: <xsl:value-of select="$BuildStamp" />
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Generator: <xsl:value-of select="$Generator" />
CompilerName: <xsl:value-of select="$CompilerName" />
OSName: <xsl:value-of select="$OSName" />
Hostname: <xsl:value-of select="$Hostname" />
OSRelease: <xsl:value-of select="$OSRelease" />
OSVersion: <xsl:value-of select="$OSVersion" />
OSPlatform: <xsl:value-of select="$OSPlatform" />
Is64Bits: <xsl:value-of select="$Is64Bits" />
VendorString: <xsl:value-of select="$VendorString" />
VendorID: <xsl:value-of select="$VendorID" />
FamilyID: <xsl:value-of select="$FamilyID" />
ModelID: <xsl:value-of select="$ModelID" />
ProcessorCacheSize: <xsl:value-of select="$ProcessorCacheSize" />
NumberOfLogicalCPU: <xsl:value-of select="$NumberOfLogicalCPU" />
NumberOfPhysicalCPU: <xsl:value-of select="$NumberOfPhysicalCPU" />
TotalVirtualMemory: <xsl:value-of select="$TotalVirtualMemory" />
TotalPhysicalMemory: <xsl:value-of select="$TotalPhysicalMemory" />
LogicalProcessorsPerPhysical: <xsl:value-of select="$LogicalProcessorsPerPhysical" />
ProcessorClockFrequency: <xsl:value-of select="$ProcessorClockFrequency" />
</system-out>
</testsuite>
</xsl:template>
<xsl:template match="Testing/Test">
<xsl:variable name="testcasename"><xsl:value-of select= "Name"/></xsl:variable>
<xsl:variable name="testclassname"><xsl:value-of select= " concat('this', substring(Path,2))"/></xsl:variable>
<xsl:variable name="exectime">
<xsl:for-each select="Results/NamedMeasurement">
<xsl:if test="@name = 'Execution Time'">
<xsl:value-of select="."/>
</xsl:if>
</xsl:for-each>
</xsl:variable>
<testcase name="{$testcasename}" classname="{$testclassname}" time="{$exectime}">
<xsl:if test="@Status = 'passed'">
</xsl:if>
<xsl:if test="@Status = 'failed'">
<xsl:variable name="failtype">
<xsl:for-each select="Results/NamedMeasurement">
<xsl:if test="@name = 'Exit Code'">
<xsl:value-of select="."/>
</xsl:if>
</xsl:for-each>
</xsl:variable>
<xsl:variable name="failcode">
<xsl:for-each select="Results/NamedMeasurement">
<xsl:if test="@name = 'Exit Value'">
<xsl:value-of select="."/>
</xsl:if>
</xsl:for-each>
</xsl:variable>
<failure message="{$failtype} ({$failcode})"><xsl:value-of select="Results/Measurement/Value/text()" /></failure>
</xsl:if>
<xsl:if test="@Status = 'notrun'">
<skipped><xsl:value-of select="Results/Measurement/Value/text()" /></skipped>
</xsl:if>
</testcase>
</xsl:template>
</xsl:stylesheet>

9
Makefile
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@ -58,7 +58,7 @@ test-cpp:
# Auto formatting of code.
# ------------------------
FORMAT_EXCLUDE = $(foreach x,$(ALL_EXCLUDE),-and -not -path './$(x)/*') -and -not -name *.bit
FORMAT_EXCLUDE = $(foreach x,$(ALL_EXCLUDE),-and -not -path './$(x)/*')
CLANG_FORMAT ?= clang-format-5.0
format-cpp:
@ -76,13 +76,10 @@ TCL_FORMAT ?= utils//tcl-reformat.sh
format-tcl:
find . -name \*.tcl $(FORMAT_EXCLUDE) -print0 | xargs -0 -P $$(nproc) -n 1 $(TCL_FORMAT)
format-trailing-ws:
find . -type f $(FORMAT_EXCLUDE) | xargs sed -i 's@\s\+$$@@g'
format: format-cpp format-docs format-py format-tcl format-trailing-ws
format: format-cpp format-docs format-py format-tcl
@true
.PHONY: format format-cpp format-py format-tcl format-trailing-ws
.PHONY: format format-cpp format-py format-tcl
# Targets related to Project X-Ray databases
# ------------------------

2
fuzzers/011-clb-ffconfig/README.md
View File

@ -34,7 +34,7 @@ Configures whether a storage element is synchronous or asynchronous.
Scope: entire site (not individual FFs)
| FFSYNC | Reset | Applicable prims |
| FFSYNC | Reset | Applicable prims |
|--------|--------------|---------------------------|
|0 | Synchronous | FDPE, FDCE, LDCE, LDPE |
|1 | Asynchronous | FDSE, FDRE |

2
fuzzers/011-clb-ffconfig/generate.py
View File

@ -58,7 +58,7 @@ with open("design.txt", "r") as f:
puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr"
CLBLM_L CLBLM_L_X10Y137 30 13 SLICE_X13Y137/AFF REG_INIT 1 FDRE
CLBLM_L CLBLM_L_X10Y137 30 13 SLICE_X12Y137/D5FF FF_INIT 0
CLBLM_L CLBLM_L_X10Y137 30 13 SLICE_X12Y137/D5FF FF_INIT 0
'''
line = line.split()
tile_type = line[0]

2
fuzzers/013-clb-ncy0/minitest/top.v
View File

@ -94,7 +94,7 @@ module clb_NCY0_O5 (input clk, input [7:0] din, output [7:0] dout);
always @(*) begin
s = din[7:4];
s[N] = o6;
di = {din[3:0]};
di[N] = o5;
end

4
fuzzers/015-clb-nffmux/top.py
View File

@ -143,7 +143,7 @@ module myLUT8 (input clk, input [7:0] din,
.O6(lutno6[1]));
generate if (ALUT_SRL != 0) begin
(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
SRLC32E #(
.INIT(64'h8000_1CE0_0000_0001)
@ -158,7 +158,7 @@ module myLUT8 (input clk, input [7:0] din,
assign lutno5[0] = din[6];
end else begin
(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_1CE0_0000_0001)

2
fuzzers/016-clb-noutmux/minitest/top.v
View File

@ -51,7 +51,7 @@ module roi(input clk, input [255:0] din, output [255:0] dout);
clb_NOUTMUX_XOR (.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8 ]));
//ok
clb_NOUTMUX_B5Q #(.LOC("SLICE_X18Y105"), .N(N))
clb_NOUTMUX_B5Q (.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8 ]));
clb_NOUTMUX_B5Q (.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8 ]));
endmodule
module myLUT8 (input clk, input [7:0] din,

4
fuzzers/016-clb-noutmux/top.py
View File

@ -147,7 +147,7 @@ module myLUT8 (input clk, input [7:0] din,
.O6(lutno6[1]));
generate if (ALUT_SRL != 0) begin
(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
SRLC32E #(
.INIT(64'h8000_1CE0_0000_0001)
@ -162,7 +162,7 @@ module myLUT8 (input clk, input [7:0] din,
assign lutno5[0] = din[6];
end else begin
(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_1CE0_0000_0001)

12
fuzzers/018-clb-ram/minitest/README.md
View File

@ -1,12 +1,12 @@
# CLB_RAM Minitest
## Purpose
SLICEM RAM test
LUT6 => 64 bits
Focus on 64 bit
32 probably uses same O5/O6 stuff
128 probably uses same MUX stuff
Why isn't there a 256?
SLICEM RAM test
LUT6 => 64 bits
Focus on 64 bit
32 probably uses same O5/O6 stuff
128 probably uses same MUX stuff
Why isn't there a 256?
## Result
```

14
fuzzers/019-clb-ndi1mux/minitest/README.md
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@ -1,18 +1,18 @@
# CLB_nDI1MUX Minitest
## Purpose
Trying to set SLICEM LUT DI1 inputs
These exist for LUTA, LUTB, and LUTC only
Can either be an external signal, another LUT's data input, or another LUT's carry
Note: mux input pattern is irregular
Trying to set SLICEM LUT DI1 inputs
These exist for LUTA, LUTB, and LUTC only
Can either be an external signal, another LUT's data input, or another LUT's carry
Note: mux input pattern is irregular
## Result
The following bits are set for NI but not NMC31:
The following bits are set for NI but not NMC31:
```
bit 00_00 ADI1MUX.AI
bit 00_20 BDI1MUX.BI
bit 01_43 BDI1MUX.CI
```
Additionally, test with unknown DI mux bits don't appear near NI bits
There is something strange going on
Additionally, test with unknown DI mux bits don't appear near NI bits
There is something strange going on

4
fuzzers/030-iob/minitest/README.md
View File

@ -22,8 +22,8 @@ DRIVE 38_64 38_66 38_72 38_74 39_65 39_73
LVCMOS25
DRIVE 38_64 38_66 38_72 38_74 39_65 39_73
4 X X X
8 X
12
8 X
12
16 X X X
LVCMOS33

2
fuzzers/030-iob/minitest/top.v
View File

@ -145,7 +145,7 @@ endmodule
*/
/*
ERROR: [DRC REQP-1581] obuf_loaded: OBUFT roi/dut pin O drives one or more invalid loads. The loads are: dout_shr[1]_i_1
ERROR: [DRC REQP-1581] obuf_loaded: OBUFT roi/dut pin O drives one or more invalid loads. The loads are: dout_shr[1]_i_1
ERROR: [Place 30-69] Instance roi/dut (OBUFT) is unplaced after IO placer
hmm
Abandoning verilog approach

2
fuzzers/059-pip-byp-bounce/README.md
View File

@ -1,4 +1,4 @@
Fuzzer for the FAN_ALT*.BYP_BOUNCE PIPs
Fuzzer for the FAN_ALT*.BYP_BOUNCE PIPs
---------------------------------------
This fuzzer solves the FAN_ALT.BYP_BOUNCE PIPs which were occasionally solved incorrectly in 050-pip-seed or 056-pip-rem.

2
fuzzers/074-dump_all/cleanup_site_pins.py
View File

@ -51,7 +51,7 @@ def find_origin_coordinate(sites):
def create_site_pin_to_wire_maps(tile_name, nodes):
""" Create a map from site_pin names to nodes.
Create a mapping from site pins to tile local wires. For each node that is
Create a mapping from site pins to tile local wires. For each node that is
attached to a site pin, there should only be 1 tile local wire.
"""

12
gridinfo/runme.sh
View File

@ -22,12 +22,12 @@ EOT
cat > design.v << EOT
module top(input [5:0] I, output O);
LUT6 #(.INIT(64'h8000000000000000)) lut (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.I4(I[4]),
.I5(I[5]),
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.I4(I[4]),
.I5(I[5]),
.O(O)
);
endmodule

2
lib/segbits_file_reader.cc
View File

@ -23,7 +23,7 @@ SegbitsFileReader::iterator SegbitsFileReader::end() {
}
SegbitsFileReader::value_type::value_type(const absl::string_view& view) {
size_t separator_start = view.find_first_of(" \t\n");
size_t separator_start = view.find_first_of(" \t");
if (separator_start == absl::string_view::npos) {
tag_ = view;
bit_ = absl::string_view();

2
lib/test_data/one_entry_missing_bit.segbits
View File

@ -1 +1 @@
CLBLL_L.SLICEL_X0.A5FF.ZINI
CLBLL_L.SLICEL_X0.A5FF.ZINI

2
minitests/clb-bused/README.md
View File

@ -4,7 +4,7 @@
Tests for BUSED bit
## Result
However got this
However got this
```
seg SEG_CLBLL_R_X13Y101
bit 30_24

14
minitests/clb-muxf8/README.md
View File

@ -1,13 +1,13 @@
# CLB_MUXF8 Minitest
## Purpose
This tests an issue related to Vivado 2017.2 vs 2017.3 changing MUXF8 behavior
The general issue is the LUT6_2 cannot be used with a MUXF8 (even if O5 is unused)
This tests an issue related to Vivado 2017.2 vs 2017.3 changing MUXF8 behavior
The general issue is the LUT6_2 cannot be used with a MUXF8 (even if O5 is unused)
## General notes:
- 2017.2: LUT6_2 works with MUXF8
- 2017.3: LUT6_2 does not work with MUXF8
- All: LUT6 works with MUXF8
- All: MUXF8 (even with MUXF7) can be instantiated unconnected
- 2017.4 seems to behave like 2017.3
- 2017.2: LUT6_2 works with MUXF8
- 2017.3: LUT6_2 does not work with MUXF8
- All: LUT6 works with MUXF8
- All: MUXF8 (even with MUXF7) can be instantiated unconnected
- 2017.4 seems to behave like 2017.3

2
minitests/fixedpnr/README.md
View File

@ -3,7 +3,7 @@
## Purpose
## Result
Preliminary result
Preliminary result
| |00_48|30_12|31_03|
|----|-----|-----|-----|

4
minitests/fixedpnr/top_fdce_inv.v
View File

@ -3,7 +3,7 @@ module top(input clk, ce, sr, d, output q);
/*
IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b1, IS_CLR_INVERTED=1'b1,
ERROR: [Place 30-1008] Instance ff has an inverted D pin which is expected to be used as an I/O flop.
However, it is used as a regular flop.
However, it is used as a regular flop.
cliff didn't have constrained, also got annoyed
he is using slightly later version
@ -30,7 +30,7 @@ module top(input clk, ce, sr, d, output q);
IS_C_INVERTED=1'b0, IS_D_INVERTED=1'b1, IS_CLR_INVERTED=1'b0,
ERROR: [Place 30-1008] Instance ff has an inverted D pin which is expected to be used as an I/O flop.
However, it is used as a regular flop.
However, it is used as a regular flop.
ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer stopped due to earlier errors.
Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'
*/

16
minitests/iserdes.idelay/src/iserdes_idelay_histogram.v
View File

@ -116,15 +116,15 @@ assign ser_rst = ser_rst_sr[0];
// BUFR - generation of CLKDIV
localparam DIVIDE = (ISERDES_MODE == "SDR" && ISERDES_WIDTH == 2) ? "2" :
(ISERDES_MODE == "SDR" && ISERDES_WIDTH == 3) ? "3" :
(ISERDES_MODE == "SDR" && ISERDES_WIDTH == 4) ? "4" :
(ISERDES_MODE == "SDR" && ISERDES_WIDTH == 5) ? "5" :
(ISERDES_MODE == "SDR" && ISERDES_WIDTH == 6) ? "6" :
(ISERDES_MODE == "SDR" && ISERDES_WIDTH == 7) ? "7" :
(ISERDES_MODE == "SDR" && ISERDES_WIDTH == 8) ? "8" :
(ISERDES_MODE == "SDR" && ISERDES_WIDTH == 3) ? "3" :
(ISERDES_MODE == "SDR" && ISERDES_WIDTH == 4) ? "4" :
(ISERDES_MODE == "SDR" && ISERDES_WIDTH == 5) ? "5" :
(ISERDES_MODE == "SDR" && ISERDES_WIDTH == 6) ? "6" :
(ISERDES_MODE == "SDR" && ISERDES_WIDTH == 7) ? "7" :
(ISERDES_MODE == "SDR" && ISERDES_WIDTH == 8) ? "8" :
(ISERDES_MODE == "DDR" && ISERDES_WIDTH == 4) ? "2" :
(ISERDES_MODE == "DDR" && ISERDES_WIDTH == 6) ? "3" :
(ISERDES_MODE == "DDR" && ISERDES_WIDTH == 4) ? "2" :
(ISERDES_MODE == "DDR" && ISERDES_WIDTH == 6) ? "3" :
(ISERDES_MODE == "DDR" && ISERDES_WIDTH == 8) ? "4" : "BYPASS";
BUFR #
(

12
minitests/iserdes.idelay/src/message_formatter.v
View File

@ -58,10 +58,10 @@ always @(posedge CLK)
tx_req <= 1'b0;
else case (fsm)
FSM_TX_HEX: tx_req <= 1'b1;
FSM_TX_SEP: tx_req <= 1'b1;
FSM_TX_CR: tx_req <= 1'b1;
FSM_TX_LF: tx_req <= 1'b1;
FSM_TX_HEX: tx_req <= 1'b1;
FSM_TX_SEP: tx_req <= 1'b1;
FSM_TX_CR: tx_req <= 1'b1;
FSM_TX_LF: tx_req <= 1'b1;
default: tx_req <= 1'b0;
@ -106,7 +106,7 @@ always @(posedge CLK)
FSM_IDLE: if (I_STB) fsm <= FSM_TX_HEX;
FSM_TX_HEX:
FSM_TX_HEX:
if (tx_rdy && (char_cnt == 0) && (word_cnt == 0))
fsm <= FSM_TX_CR;
else if (tx_rdy && (char_cnt == 0)) fsm <= FSM_TX_SEP;
@ -115,7 +115,7 @@ always @(posedge CLK)
FSM_TX_SEP: if (tx_rdy) fsm <= FSM_TX_HEX;
FSM_TX_CR: if (tx_rdy) fsm <= FSM_TX_LF;
FSM_TX_LF: if (tx_rdy) fsm <= FSM_IDLE;
endcase
// ============================================================================

22
minitests/iserdes.sdr_ddr/basys3_iserdes_sdr_ddr.v
View File

@ -44,16 +44,16 @@ wire [9:0] error;
genvar i;
generate for (i=0; i<10; i=i+1) begin
localparam DATA_WIDTH = (i == 0) ? 2 :
(i == 1) ? 3 :
(i == 2) ? 4 :
(i == 3) ? 5 :
(i == 4) ? 6 :
(i == 5) ? 7 :
(i == 6) ? 8 :
(i == 7) ? 4 :
(i == 8) ? 6 :
/*(i == 9) ?*/ 8;
localparam DATA_WIDTH = (i == 0) ? 2 :
(i == 1) ? 3 :
(i == 2) ? 4 :
(i == 3) ? 5 :
(i == 4) ? 6 :
(i == 5) ? 7 :
(i == 6) ? 8 :
(i == 7) ? 4 :
(i == 8) ? 6 :
/*(i == 9) ?*/ 8;
localparam DATA_RATE = (i < 7) ? "SDR" : "DDR";
@ -66,7 +66,7 @@ generate for (i=0; i<10; i=i+1) begin
(
.CLK (CLK),
.RST (RST),
.IO_DAT (io[i]),
.O_ERROR (error[i])
);

4
minitests/iserdes.sdr_ddr/src/comparator.v
View File

@ -88,12 +88,12 @@ always @(posedge CLK)
count_err <= count_err + 1;
else if (o_bitslip)
count_err <= 0;
always @(posedge CLK)
if (RST)
o_bitslip <= 1'b0;
else if (!o_bitslip && (count_err >= ERROR_COUNT))
o_bitslip <= 1'b1;
o_bitslip <= 1'b1;
else if ( o_bitslip)
o_bitslip <= 1'b0;

16
minitests/iserdes.sdr_ddr/src/receiver.v
View File

@ -26,15 +26,15 @@ wire i_rstdiv;
// Divider for BUFR
localparam DIVIDE = (MODE == "SDR" && WIDTH == 2) ? "2" :
(MODE == "SDR" && WIDTH == 3) ? "3" :
(MODE == "SDR" && WIDTH == 4) ? "4" :
(MODE == "SDR" && WIDTH == 5) ? "5" :
(MODE == "SDR" && WIDTH == 6) ? "6" :
(MODE == "SDR" && WIDTH == 7) ? "7" :
(MODE == "SDR" && WIDTH == 8) ? "8" :
(MODE == "SDR" && WIDTH == 3) ? "3" :
(MODE == "SDR" && WIDTH == 4) ? "4" :
(MODE == "SDR" && WIDTH == 5) ? "5" :
(MODE == "SDR" && WIDTH == 6) ? "6" :
(MODE == "SDR" && WIDTH == 7) ? "7" :
(MODE == "SDR" && WIDTH == 8) ? "8" :
(MODE == "DDR" && WIDTH == 4) ? "2" :
(MODE == "DDR" && WIDTH == 6) ? "3" :
(MODE == "DDR" && WIDTH == 4) ? "2" :
(MODE == "DDR" && WIDTH == 6) ? "3" :
(MODE == "DDR" && WIDTH == 8) ? "4" : "BYPASS";
// BUFR
BUFR #

8
minitests/litex/src.vivado/VexRiscv_Linux.v
View File

@ -3188,7 +3188,7 @@ module VexRiscv (
end
end
InstructionCache IBusCachedPlugin_cache (
InstructionCache IBusCachedPlugin_cache (
.io_flush(_zz_239_),
.io_cpu_prefetch_isValid(_zz_240_),
.io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt),
@ -3234,9 +3234,9 @@ module VexRiscv (
.io_mem_rsp_payload_data(iBus_rsp_payload_data),
.io_mem_rsp_payload_error(iBus_rsp_payload_error),
.clk(clk),
.reset(reset)
.reset(reset)
);
DataCache dataCache_1_ (
DataCache dataCache_1_ (
.io_cpu_execute_isValid(_zz_249_),
.io_cpu_execute_address(_zz_250_),
.io_cpu_execute_args_wr(_zz_251_),
@ -3289,7 +3289,7 @@ module VexRiscv (
.io_mem_rsp_payload_data(dBus_rsp_payload_data),
.io_mem_rsp_payload_error(dBus_rsp_payload_error),
.clk(clk),
.reset(reset)
.reset(reset)
);
always @(*) begin
case(_zz_498_)

8
minitests/litex/src.yosys/VexRiscv_Linux.v
View File

@ -3188,7 +3188,7 @@ module VexRiscv (
end
end
InstructionCache IBusCachedPlugin_cache (
InstructionCache IBusCachedPlugin_cache (
.io_flush(_zz_239_),
.io_cpu_prefetch_isValid(_zz_240_),
.io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt),
@ -3234,9 +3234,9 @@ module VexRiscv (
.io_mem_rsp_payload_data(iBus_rsp_payload_data),
.io_mem_rsp_payload_error(iBus_rsp_payload_error),
.clk(clk),
.reset(reset)
.reset(reset)
);
DataCache dataCache_1_ (
DataCache dataCache_1_ (
.io_cpu_execute_isValid(_zz_249_),
.io_cpu_execute_address(_zz_250_),
.io_cpu_execute_args_wr(_zz_251_),
@ -3289,7 +3289,7 @@ module VexRiscv (
.io_mem_rsp_payload_data(dBus_rsp_payload_data),
.io_mem_rsp_payload_error(dBus_rsp_payload_error),
.clk(clk),
.reset(reset)
.reset(reset)
);
always @(*) begin
case(_zz_498_)

2
minitests/litex/src.yosys/missing_bit_report.py
View File

@ -1,7 +1,7 @@
""" Generates a missing feature/bit report for LiteX design.
This script is fairly fragile, because it depends on the specific observation
that all of the remaining bits appear to either belong to HCLK_IOI or IOI3
that all of the remaining bits appear to either belong to HCLK_IOI or IOI3
tiles. A more general version of this script could be created, but that was
not the point of this script.

20
minitests/oserdes/basys3_oserdes_rates.v
View File

@ -67,16 +67,16 @@ wire [9:0] error;
genvar i;
generate for (i=0; i<10; i=i+1) begin
localparam DATA_WIDTH = (i == 0) ? 2 :
(i == 1) ? 3 :
(i == 2) ? 4 :
(i == 3) ? 5 :
(i == 4) ? 6 :
(i == 5) ? 7 :
(i == 6) ? 8 :
(i == 7) ? 4 :
(i == 8) ? 6 :
/*(i == 9) ?*/ 8;
localparam DATA_WIDTH = (i == 0) ? 2 :
(i == 1) ? 3 :
(i == 2) ? 4 :
(i == 3) ? 5 :
(i == 4) ? 6 :
(i == 5) ? 7 :
(i == 6) ? 8 :
(i == 7) ? 4 :
(i == 8) ? 6 :
/*(i == 9) ?*/ 8;
localparam DATA_RATE = (i < 7) ? "SDR" : "DDR";

20
minitests/oserdes/src/oserdes_test.v
View File

@ -27,17 +27,17 @@ output wire O_ERROR
// ============================================================================
// Generate CLK2 and CLKDIV for OSERDES using BUFRs
localparam CLKDIV_DIVIDE =
localparam CLKDIV_DIVIDE =
(DATA_RATE == "SDR" && DATA_WIDTH == 2) ? "2" :
(DATA_RATE == "SDR" && DATA_WIDTH == 3) ? "3" :
(DATA_RATE == "SDR" && DATA_WIDTH == 4) ? "4" :
(DATA_RATE == "SDR" && DATA_WIDTH == 5) ? "5" :
(DATA_RATE == "SDR" && DATA_WIDTH == 6) ? "6" :
(DATA_RATE == "SDR" && DATA_WIDTH == 7) ? "7" :
(DATA_RATE == "SDR" && DATA_WIDTH == 8) ? "8" :
(DATA_RATE == "SDR" && DATA_WIDTH == 3) ? "3" :
(DATA_RATE == "SDR" && DATA_WIDTH == 4) ? "4" :
(DATA_RATE == "SDR" && DATA_WIDTH == 5) ? "5" :
(DATA_RATE == "SDR" && DATA_WIDTH == 6) ? "6" :
(DATA_RATE == "SDR" && DATA_WIDTH == 7) ? "7" :
(DATA_RATE == "SDR" && DATA_WIDTH == 8) ? "8" :
(DATA_RATE == "DDR" && DATA_WIDTH == 4) ? "4" :
(DATA_RATE == "DDR" && DATA_WIDTH == 6) ? "6" :
(DATA_RATE == "DDR" && DATA_WIDTH == 4) ? "4" :
(DATA_RATE == "DDR" && DATA_WIDTH == 6) ? "6" :
(DATA_RATE == "DDR" && DATA_WIDTH == 8) ? "8" : "BYPASS";
wire CLKX;
@ -93,7 +93,7 @@ always @(posedge CLKDIV)
ser_dat <= lfsr_dat;
// ============================================================================
// OSERDES
// OSERDES
// OSERDES reset generator (required for it to work properly!)
reg [3:0] ser_rst_sr;

2
minitests/partial_reconfig_flow/Makefile
View File

@ -5,7 +5,7 @@
# will generate a bitstream that includes both the harness and the .fasm design
# ready for programming to a board. For example,
# 'make inv_hand_crafted.bit' will generate a bitstream that includes the
# design from roi_noninv.fasm.
# design from roi_noninv.fasm.
%_hand_crafted.bit: %_roi_partial.frm harness.bit
${XRAY_TOOLS_DIR}/xc7patch \
--part_name "${XRAY_PART}" \

2
minitests/plle2_adv/src/plle2_test.v
View File

@ -87,7 +87,7 @@ wire rst = RST || !O_LOCKED;
genvar i;
generate for (i=0; i<6; i=i+1) begin
reg [23:0] counter;
always @(posedge clk[i] or posedge rst)

8
minitests/timing/picosoc_noflash.v
View File

@ -94,11 +94,11 @@ module picosoc_noflash (
wire [31:0] simpleuart_reg_dat_do;
wire simpleuart_reg_dat_wait;
assign mem_ready =
assign mem_ready =
(iomem_valid && iomem_ready) || progmem_ready || ram_ready || spimemio_cfgreg_sel ||
simpleuart_reg_div_sel || (simpleuart_reg_dat_sel && !simpleuart_reg_dat_wait);
assign mem_rdata =
assign mem_rdata =
(iomem_valid && iomem_ready) ? iomem_rdata :
progmem_ready ? progmem_rdata :
ram_ready ? ram_rdata :
@ -106,7 +106,7 @@ module picosoc_noflash (
simpleuart_reg_div_sel ? simpleuart_reg_div_do :
simpleuart_reg_dat_sel ? simpleuart_reg_dat_do : 32'h 0000_0000;
`ifdef SIMULATION
`ifdef SIMULATION
wire trace_valid;
wire [35:0] trace_data;
integer trace_file;
@ -121,7 +121,7 @@ module picosoc_noflash (
.ENABLE_MUL(1),
.ENABLE_DIV(1),
.ENABLE_IRQ(1),
`ifdef SIMULATION
`ifdef SIMULATION
.ENABLE_IRQ_QREGS(0),
.ENABLE_TRACE(1)
`else

2
prjxray/bitstream.py
View File

@ -17,7 +17,7 @@ bit_0002000f_079_06
Where:
-0002000f: FDRI address
-079: FDIR word number (0-100)
-06: bit index (0-31)
-06: bit index (0-31)
'''

10
prjxray/lms_solver.py
View File

@ -19,7 +19,7 @@ solved all at once (not recommended).
For each tag a vector of weights is calculated. Each weight corresponds to one
bit. Positive values indicate positive correlation and negative values negative
correlation.
correlation.
Each weight vector is normalized so that maximum absolute weight is equal to
one.
@ -557,7 +557,7 @@ def detect_candidates(X, th, norm=None):
def compute_bit_correlations(tags_to_solve, bits_to_solve, segdata, W):
"""
Basing on solution given in the matrix W returns a matrix C with
Basing on solution given in the matrix W returns a matrix C with
correlation coefficients of each bit.
Also returns a dict of dicts indexed by tag names and bit names with
@ -635,7 +635,7 @@ def compute_tag_stats(all_tags, segdata):
Returns
-------
A dict indexed by tag name with tuples containing 0 and 1 occurrence count.
"""
@ -681,11 +681,11 @@ def build_address_map(tilegrid_file):
----------
tilegrid_file:
The tilegrid.json file/
The tilegrid.json file/
Returns
-------
A dict with lists of tile names.
"""

2
utils/blockwidth.py
View File

@ -37,7 +37,7 @@ def gen_frame_writes(f):
[Write Type=1 Address= 1 Length= 1 Reg="Frame Address"]
Data in hex:
1d
1d
'''
while True:

4
utils/vtemplate
View File

@ -26,7 +26,7 @@ for l in txt.split('\n'):
if m:
names = m.group(5)
aio = m.group(1)
for name in names.split(','):
name = name.strip()
if not name:
@ -66,7 +66,7 @@ for l in txt.split('\n'):
# input A0, A1, A2, A3, A4, A5, D, WCLK, WE;
modinst = modname
print '''\

2
vagrant/Vagrantfile vendored
View File

@ -51,7 +51,7 @@ Vagrant.configure("2") do |config|
s.inline = <<-SHELL
export DISPLAY=:0
dconf write /org/gnome/desktop/screensaver/idle-activation-enabled false
dconf write /org/gnome/desktop/screensaver/lock-enabled false
dconf write /org/gnome/desktop/screensaver/lock-enabled false
SHELL
end