mirror of https://github.com/openXC7/prjxray.git
Reworked fuzzer, added README.md
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc
parent
73c8652858
commit
4a6930694f
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@ -8,7 +8,9 @@ MAKETODO_FLAGS=--sides "r_upper_t,l_upper_t" --pip-type ${PIP_TYPE} --seg-type c
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else
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MAKETODO_FLAGS=--sides "l_upper_t" --pip-type ${PIP_TYPE} --seg-type cmt_top --re $(TODO_RE)
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endif
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N = 100
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N = 80
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SEGMATCH_FLAGS=-m 10 -M 20 -c 170
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A_PIPLIST=cmt_top_l_upper_t.txt
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@ -30,14 +32,14 @@ RDBS += build/segbits_cmt_top_r_upper_t.rdb
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endif
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database: ${RDBS}
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
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--seg-fn-in build/segbits_cmt_top_l_upper_t.rdb \
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--seg-fn-out build/segbits_cmt_top_l_upper_t.db
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python3 ${FUZDIR}/fixup_and_group.py -g tag_groups.txt \
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-i build/segbits_cmt_top_l_upper_t.rdb \
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-o build/segbits_cmt_top_l_upper_t.db
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ifneq (${XRAY_DATABASE}, zynq7)
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
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--seg-fn-in build/segbits_cmt_top_r_upper_t.rdb \
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--seg-fn-out build/segbits_cmt_top_r_upper_t.db
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python3 ${FUZDIR}/fixup_and_group.py -g tag_groups.txt \
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-i build/segbits_cmt_top_r_upper_t.rdb \
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-o build/segbits_cmt_top_r_upper_t.db
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endif
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# Keep a copy to track iter progress
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@ -0,0 +1,20 @@
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# Fuzzer for the PIPs of CMT_TOP_[LR]_UPPER_T tiles.
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The fuzzer instantiates a PLL in each available site with 2/3 probability of using it. Once used it is connected randomly to various clock and logic resources.
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For some nets a randomized "manual" route is chosen to cover as many routing scenarios as possible.
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The information whether a PLL is used or not is stored in a file (`"design.txt"`) along with the randomized route (`route.txt`)
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After the design synthesis the `generate.py` sets fixed routes on some nets which is read from the `route.txt` file. The rest of the design is routed in the regular way. The script also dumps all used PIPs (as reported by Vivado) to the `design_pips.txt`.
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The tag generation is done in the following way:
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- If a PLL site is occupied then tags for all active PIPs are emitted as 1s. No tags are emitted for inactive PIPs.
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- When a PLL site is not occupied (IN_USE=0) then tags for all PIPs for the CMT tile are emitted as 0s.
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- The IN_USE tag is emitted directly.
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The raw solution of tag bits is postprocessed via the custom script `fixup_and_group.py`. The script does two things:
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- Clears all bits found for the IN_USE tag in all other tags. Those bits are common to all of them.
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- Groups tags according to the group definitions read from the `tag_groups.txt` file. Bits that are common to the group are set as 0 in each tag that belongs to it (tags within a group are exclusive).
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@ -1,9 +0,0 @@
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CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT ^ CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1
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CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT ^ CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2
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CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT ^ CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN
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CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT ^ CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1
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CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT ^ CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2
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CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT ^ CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_CLKFBIN
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28_43 29_42 29_43 28_44
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@ -0,0 +1,222 @@
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#!/usr/bin/env python3
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"""
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This is a db fixup script that does two things:
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1. Clears (removes) all bits found in "IN_USE" tag(s) and removes the IN_USE
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tag itself
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2. Reads tag group definition from a file and applies the tag grouping. First
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a set of common bits for each group is found (logical OR among all tags
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belonging to the group). Then in each tag belonging to the group those
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bits are set to 0 but only if they are not already present there.
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The resulting data is written into a segbits file.
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"""
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import argparse
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import re
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import itertools
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# =============================================================================
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def load_tag_groups(file_name):
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"""
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Loads tag groups from a text file.
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A tag group is defined by specifying a space separated list of tags within
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a single line. Lines that are empty or start with '#' are ignored.
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"""
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tag_groups = []
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# Load tag group specifications
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with open(file_name, "r") as fp:
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for line in fp:
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line = line.strip()
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if len(line) == 0 or line.startswith("#"):
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continue
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group = set(line.split())
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if len(group):
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tag_groups.append(group)
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# Check if all tag groups are exclusive
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for tag_group_a, tag_group_b in itertools.combinations(tag_groups, 2):
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tags = tag_group_a & tag_group_b
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if len(tags):
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raise RuntimeError(
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"Tag(s) {} are present in multiple groups".format(
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" ".join(tags)))
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return tag_groups
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# =============================================================================
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def parse_bit(bit):
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"""
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Decodes string describing a bit. Returns a tuple (frame, bit, value)
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"""
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match = re.match("^(!?)([0-9]+)_([0-9]+)$", bit)
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assert match != None, bit
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val = int(match.group(1) != "!")
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frm = int(match.group(2))
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bit = int(match.group(3))
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return frm, bit, val
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def bit_to_str(bit):
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"""
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Converts a tuple (frame, bit, value) to its string representation.
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"""
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s = "!" if not bit[2] else ""
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return "{}{}_{}".format(s, bit[0], bit[1])
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def load_segbits(file_name):
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"""
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Loads a segbits file.
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"""
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segbits = {}
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with open(file_name, "r") as fp:
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for line in fp:
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line = line.strip()
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fields = line.split()
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if len(fields) < 2:
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raise RuntimeError("Malformed line: '%s'" % line)
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tag = fields[0]
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if "<" in line or ">" in line:
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segbits[tag] = set()
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else:
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bits = set([parse_bit(bit) for bit in fields[1:]])
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segbits[tag] = bits
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return segbits
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def save_segbits(file_name, segbits):
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"""
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Save segbits to a .db or .rdb file
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"""
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with open(file_name, "w") as fp:
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for tag, bits in segbits.items():
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if not len(bits):
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continue
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line = tag + " "
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line += " ".join([bit_to_str(bit) for bit in sorted(list(bits))])
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fp.write(line + "\n")
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# =============================================================================
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def mask_out_bits(segbits, mask, tags_to_mask=None):
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"""
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Given a set of bits and a list of tags to affect (optional) removes all
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the bits from each tag that are present (and equal) in the masking set.
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"""
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if tags_to_mask is None:
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tags_to_mask = segbits.keys()
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# Mask out matching bits
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for tag in tags_to_mask:
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bits = segbits[tag]
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bits = set(bits) - set(mask)
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segbits[tag] = bits
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return segbits
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def find_common_bits_for_tag_groups(segbits, tag_groups):
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"""
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For each tag group finds a common set of bits that have value of one.
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"""
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bit_groups = []
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for tag_group in tag_groups:
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bit_group = set()
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for tag, bits in segbits.items():
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if tag in tag_group:
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ones = set([b for b in bits if b[2]])
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bit_group |= ones
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bit_groups.append(bit_group)
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return bit_groups
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def group_tags(segbits, tag_groups, bit_groups):
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"""
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Implements tag grouping. If a tag belongs to a group then the common bits
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of that group are added to is as zeros.
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"""
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for tag_group, bit_group in zip(tag_groups, bit_groups):
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zeros = set([(b[0], b[1], 0) for b in bit_group])
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for tag in tag_group:
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# Insert zero bits
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if tag in segbits.keys():
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bits = segbits[tag]
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for z in zeros:
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if not (z[0], z[1], 1) in bits:
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bits.add(z)
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return segbits
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# =============================================================================
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def main():
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# Parse arguments
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parser = argparse.ArgumentParser()
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parser.add_argument("-i", required=True, type=str, help="Input .rdb file")
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parser.add_argument(
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"-g", required=True, type=str, help="Input tag group definition file")
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parser.add_argument("-o", required=True, type=str, help="Output .rdb file")
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args = parser.parse_args()
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# Load tag groups
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tag_groups = load_tag_groups(args.g)
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# Load raw database file
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segbits = load_segbits(args.i)
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# Mask out bits present in "IN_USE" tag(s) as they are common to other tags
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for tag in segbits.keys():
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if tag.endswith("IN_USE"):
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prefix = tag[:tag.index("IN_USE")]
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tags_to_mask = [t for t in segbits.keys() if t.startswith(prefix)]
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mask_out_bits(segbits, segbits[tag], tags_to_mask)
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# Find common bits
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bit_groups = find_common_bits_for_tag_groups(segbits, tag_groups)
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# Apply tag grouping
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segbits = group_tags(segbits, tag_groups, bit_groups)
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# Save fixed database file
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save_segbits(args.o, segbits)
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if __name__ == "__main__":
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main()
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@ -4,11 +4,10 @@ from prjxray.segmaker import Segmaker
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import os
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import os.path
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import itertools
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import random
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def bitfilter(frame, word):
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if frame <= 1:
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if frame < 28 or frame > 29:
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return False
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return True
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@ -17,12 +16,14 @@ def bitfilter(frame, word):
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def main():
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segmk = Segmaker("design.bits")
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designdata = {}
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tiledata = {}
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pipdata = {}
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ppipdata = {}
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ignpip = set()
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# Load PIP lists
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print("Loading PIP lists...")
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piplists = ['cmt_top_l_upper_t.txt', 'cmt_top_r_upper_t.txt']
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for piplist in piplists:
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
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@ -35,6 +36,7 @@ def main():
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pipdata[tile_type].append((src, dst))
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# Load PPIP lists (to exclude them)
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print("Loading PPIP lists...")
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ppiplists = ['ppips_cmt_top_l_upper_t.db', 'ppips_cmt_top_r_upper_t.db']
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for ppiplist in ppiplists:
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fname = os.path.join(
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@ -43,7 +45,6 @@ def main():
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for l in f:
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pip_data, pip_type = l.strip().split()
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print(pip_data, pip_type)
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if pip_type != 'always':
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continue
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@ -53,8 +54,14 @@ def main():
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ppipdata[tile_type].append((src, dst))
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print("Loading tags from design.txt.")
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# Load desgin data
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print("Loading design data...")
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with open("design.txt", "r") as f:
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for line in f:
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fields = line.strip().split(",")
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designdata[fields[0]] = fields[1:]
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with open("design_pips.txt", "r") as f:
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for line in f:
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tile, pip, src, dst, pnum, pdir = line.split()
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@ -94,63 +101,50 @@ def main():
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dst.startswith('CMT_TOP_L_UPPER_T_CLK'):
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ignpip.add((src, dst))
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# Ignore pseudo pips
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for ppip in ppipdata[tile_type]:
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if ppip == (src, dst):
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ignpip.add((
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src,
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dst,
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))
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tags = {}
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for tile, pips_srcs_dsts in tiledata.items():
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tile_type = pips_srcs_dsts["type"]
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pips = pips_srcs_dsts["pips"]
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# Populate IN_USE tags
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for tile, (site, in_use) in designdata.items():
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if tile not in tags:
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tags[tile] = {}
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for src, dst in pipdata[tile_type]:
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if (src, dst) in ignpip:
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pass
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elif (src, dst) in pips:
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tags[tile]["%s.%s" % (dst, src)] = 1
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elif (src, dst) not in tiledata[tile]["pips"]:
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tags[tile]["%s.%s" % (dst, src)] = 0
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internal_feedback = False
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for src, dst in [
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('CMT_TOP_L_CLKFBOUT2IN', 'CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN'),
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('CMT_TOP_R_CLKFBOUT2IN', 'CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN'),
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]:
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if (src, dst) in pips:
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internal_feedback = True
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tags[tile]["EXTERNAL_FEEDBACK"] = int(not internal_feedback)
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# Those tags are exclusive. This is due to the fact that Vivado sometimes
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# report routes that does not correspond to underlying bit configuration.
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xored_tags = [
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(
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"CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_CLKFBIN",
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"CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT"
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),
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(
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"CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN",
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"CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT"
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),
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]
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tags[tile]["IN_USE"] = int(in_use)
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# Populate PIPs
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for tile in tags.keys():
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for pair in xored_tags:
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for tag_a, tag_b in itertools.permutations(pair, 2):
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tile_type = tile.rsplit("_", maxsplit=1)[0]
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if tag_a in tags[tile] and tag_b in tags[tile]:
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if tags[tile][tag_a] == tags[tile][tag_b]:
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d = tags[tile]
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del d[tag_a]
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del d[tag_b]
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in_use = tags[tile]["IN_USE"]
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internal_feedback = False
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if not in_use:
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active_pips = []
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else:
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active_pips = tiledata[tile]["pips"]
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for src, dst in pipdata[tile_type]:
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if (src, dst) in ignpip:
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continue
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if (src, dst) in ppipdata[tile_type]:
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continue
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tag = "{}.{}".format(dst, src)
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val = in_use if (src, dst) in active_pips else False
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if not (in_use and not val):
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tags[tile][tag] = int(val)
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for s, d in [
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('CMT_TOP_L_CLKFBOUT2IN', 'CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN'),
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('CMT_TOP_R_CLKFBOUT2IN', 'CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN'),
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]:
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if (s, d) in active_pips:
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internal_feedback = in_use
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|
||||
tags[tile]["INTERNAL_FEEDBACK"] = int(internal_feedback)
|
||||
|
||||
# Output tags
|
||||
for tile, tile_tags in tags.items():
|
||||
for t, v in tile_tags.items():
|
||||
segmk.add_tile_tag(tile, t, v)
|
||||
|
|
|
|||
|
|
@ -92,7 +92,7 @@ proc load_routes {filename} {
|
|||
|
||||
# Route the single net. Needed to detect conflicts when evaluating
|
||||
# other ones
|
||||
route_design -quiet -nets $net
|
||||
route_design -quiet -directive Quick -nets $net
|
||||
|
||||
# Check for conflicts.
|
||||
set status [get_property ROUTE_STATUS $net]
|
||||
|
|
@ -138,11 +138,11 @@ proc run {} {
|
|||
load_routes routes.txt
|
||||
write_checkpoint -force design_pre_route.dcp
|
||||
|
||||
route_design -preserve
|
||||
route_design -directive Quick -preserve
|
||||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
write_pip_txtdata design.txt
|
||||
write_pip_txtdata design_pips.txt
|
||||
}
|
||||
|
||||
run
|
||||
|
|
|
|||
|
|
@ -0,0 +1,13 @@
|
|||
CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_CLKFBOUT2IN CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_CLKFBIN CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB0 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB1 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB2 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB3 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT
|
||||
|
||||
CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB0 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB1 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB2 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB3 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT
|
||||
|
||||
CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB0 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB1 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB2 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB3 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT
|
||||
|
||||
CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_CLKFBOUT2IN CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB0 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB1 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB2 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB3 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT
|
||||
|
||||
CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB0 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB1 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB2 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB3 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT
|
||||
|
||||
CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB0 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB1 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB2 CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB3
|
||||
CMT_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT
|
||||
|
||||
|
|
@ -51,8 +51,9 @@ def get_random_route_from_site_pin(
|
|||
site_type = tile["sites"][site_name]
|
||||
|
||||
tile = db.get_tile_type(tile_type)
|
||||
site = [s for s in tile.get_sites() if s.type == site_type
|
||||
][0] # FIXME: find correct site by vivado loc
|
||||
|
||||
# Assumption: there is only one PLL per tile.
|
||||
site = [s for s in tile.get_sites() if s.type == site_type][0]
|
||||
|
||||
# Find site wire
|
||||
wire = None
|
||||
|
|
@ -62,7 +63,7 @@ def get_random_route_from_site_pin(
|
|||
break
|
||||
assert wire is not None
|
||||
|
||||
# Walk randomly over not occupied wires.
|
||||
# Walk randomly.
|
||||
route = []
|
||||
while True:
|
||||
route.append(wire)
|
||||
|
|
@ -94,40 +95,47 @@ def get_random_route_from_site_pin(
|
|||
|
||||
|
||||
def main():
|
||||
|
||||
# 8 inputs per clock region
|
||||
# 5 clock regions for device
|
||||
max_clk_inputs = 8 * 5
|
||||
clkin_idx = 0
|
||||
|
||||
print(
|
||||
'''
|
||||
module top();
|
||||
module top(
|
||||
input wire [{nclkin}:0] clkin
|
||||
);
|
||||
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
LUT6 dummy();
|
||||
''')
|
||||
'''.format(nclkin=max_clk_inputs - 1))
|
||||
|
||||
db = Database(util.get_db_root())
|
||||
bufg_count = 0
|
||||
|
||||
design_file = open('design.txt', 'w')
|
||||
routes_file = open('routes.txt', 'w')
|
||||
|
||||
for tile, site, phasers in sorted(gen_sites(), key=lambda x: x[0]):
|
||||
in_use = random.randint(0, 2) > 0
|
||||
|
||||
design_file.write("{},{},{}\n".format(tile, site, int(in_use)))
|
||||
|
||||
if not in_use:
|
||||
continue
|
||||
|
||||
# Generate random routes to/from some pins
|
||||
routes = {}
|
||||
endpoints = {}
|
||||
|
||||
pins = [
|
||||
# Enabling random manual routing for CLKINx breaks solution for
|
||||
# tags:
|
||||
# - CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT
|
||||
# - CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT
|
||||
|
||||
#('CLKIN1', 'up'),
|
||||
#('CLKIN2', 'up'),
|
||||
|
||||
# This works:
|
||||
('CLKIN1', 'up'),
|
||||
('CLKIN2', 'up'),
|
||||
('CLKFBIN', 'up'),
|
||||
('CLKFBOUT', 'down'),
|
||||
|
||||
# Sometimes manually randomized route for CLKOUTx conflicts with
|
||||
# the verilog design. Need to fix that in the future.
|
||||
|
||||
# the verilog design.
|
||||
#('CLKOUT0', 'down'),
|
||||
#('CLKOUT1', 'down'),
|
||||
#('CLKOUT2', 'down'),
|
||||
|
|
@ -149,12 +157,10 @@ module top();
|
|||
)
|
||||
endpoints[pin] = route[-1] if dir == 'down' else route[0]
|
||||
|
||||
internal_feedback = endpoints['CLKFBOUT'].endswith('CLKFBIN')
|
||||
if internal_feedback:
|
||||
del routes['CLKFBIN']
|
||||
internal_feedback = endpoints['CLKFBIN'].endswith('CLKFBOUT')
|
||||
|
||||
# Store them in random order so the TCL script will try to route
|
||||
# in random order.
|
||||
# Store them in a random order so the TCL script will try to route
|
||||
# them also in the random order.
|
||||
lines = []
|
||||
for pin, (
|
||||
route,
|
||||
|
|
@ -168,7 +174,6 @@ module top();
|
|||
random.shuffle(lines)
|
||||
routes_file.writelines(lines)
|
||||
|
||||
#clkfbin_src = random.choice(('BUFH', '0', '1', 'logic', None))
|
||||
clkfbin_src = random.choice(('BUFH', 'logic'))
|
||||
|
||||
if internal_feedback:
|
||||
|
|
@ -236,7 +241,7 @@ module top();
|
|||
# - Global drivers (e.g. BUFG)
|
||||
# - PHASER_[IN|OUT]_[CA|DB]_FREQREFCLK via BB_[0-3]
|
||||
drive_bufg = random.randint(0, 1) and bufg_count < 16
|
||||
drive_phaser = random.randint(0, 1)
|
||||
drive_phaser = 0 #random.randint(0, 1)
|
||||
|
||||
if drive_bufg:
|
||||
bufg_count += 1
|
||||
|
|
@ -270,18 +275,6 @@ module top();
|
|||
.I(clkfbout_mult_{site}),
|
||||
.O(clkfbin_{site})
|
||||
);""".format(site=site))
|
||||
elif clkfbin_src == '0':
|
||||
print(
|
||||
"""
|
||||
assign clkfbin_{site} = 1'b0;
|
||||
""".format(site=site))
|
||||
elif clkfbin_src == '1':
|
||||
print(
|
||||
"""
|
||||
assign clkfbin_{site} = 1'b1;
|
||||
""".format(site=site))
|
||||
elif clkfbin_src is None:
|
||||
pass
|
||||
elif clkfbin_src == 'logic':
|
||||
print(
|
||||
"""
|
||||
|
|
@ -292,59 +285,46 @@ module top();
|
|||
.O(clkfbin_{site})
|
||||
);
|
||||
""".format(site=site))
|
||||
|
||||
clkin_is_none = False
|
||||
else:
|
||||
assert False, clkfb_src
|
||||
|
||||
for clkin in range(2):
|
||||
clkin_src = random.choice(
|
||||
(
|
||||
'BUFH',
|
||||
'BUFR',
|
||||
# '0',
|
||||
# '1',
|
||||
'logic',
|
||||
# None,
|
||||
))
|
||||
if clkin == 1 and clkin_is_none and clkin_src is None:
|
||||
clkin_src = 'BUFH'
|
||||
clkin_src = random.choice((
|
||||
'BUFH',
|
||||
'BUFR',
|
||||
'logic',
|
||||
))
|
||||
|
||||
if clkin_src is None:
|
||||
pass
|
||||
elif clkin_src == 'BUFH':
|
||||
if clkin_src == 'BUFH':
|
||||
print(
|
||||
"""
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
BUFH (
|
||||
.O(clkin{idx}_{site})
|
||||
);""".format(idx=clkin + 1, site=site))
|
||||
.O(clkin{idx}_{site}),
|
||||
.I(clkin{idx2})
|
||||
);""".format(idx=clkin + 1, idx2=clkin_idx, site=site))
|
||||
elif clkin_src == 'BUFR':
|
||||
print(
|
||||
"""
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
BUFR (
|
||||
.O(clkin{idx}_{site})
|
||||
);""".format(idx=clkin + 1, site=site))
|
||||
elif clkin_src == '0':
|
||||
print(
|
||||
"""
|
||||
assign clkin{idx}_{site} = 0;
|
||||
""".format(idx=clkin + 1, site=site))
|
||||
elif clkin_src == '1':
|
||||
print(
|
||||
"""
|
||||
assign clkin{idx}_{site} = 1;
|
||||
""".format(idx=clkin + 1, site=site))
|
||||
.O(clkin{idx}_{site}),
|
||||
.I(clkin{idx2})
|
||||
);""".format(idx=clkin + 1, idx2=clkin_idx, site=site))
|
||||
elif clkin_src == 'logic':
|
||||
print(
|
||||
"""
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
LUT6 # (.INIT(64'h5555555555555555))
|
||||
clkin{idx}_logic_{site} (
|
||||
.I0(clkin{idx2}),
|
||||
.O(clkin{idx}_{site})
|
||||
);
|
||||
""".format(idx=clkin + 1, site=site))
|
||||
""".format(idx=clkin + 1, idx2=clkin_idx, site=site))
|
||||
else:
|
||||
assert False, clkin_src
|
||||
assert False, (clkin, clkin_src)
|
||||
|
||||
clkin_idx += 1
|
||||
|
||||
print("endmodule")
|
||||
|
||||
|
|
|
|||
|
|
@ -15,6 +15,10 @@ input wire [15:0] sw,
|
|||
output wire [15:0] led
|
||||
);
|
||||
|
||||
// ============================================================================
|
||||
|
||||
assign tx = rx;
|
||||
|
||||
// ============================================================================
|
||||
// Clock & reset
|
||||
reg [3:0] rst_sr;
|
||||
|
|
@ -44,7 +48,8 @@ plle2_test plle2_test
|
|||
.O_CNT (led[5:0])
|
||||
);
|
||||
|
||||
assign led [14:6] = 0;
|
||||
assign led [14] = |sw;
|
||||
assign led [13:6] = 0;
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -22,12 +22,16 @@ always @(posedge clk100)
|
|||
|
||||
// ============================================================================
|
||||
// The PLL
|
||||
wire clk_fb;
|
||||
wire clk_fb_o;
|
||||
wire clk_fb_i;
|
||||
|
||||
wire [5:0] clk;
|
||||
|
||||
PLLE2_ADV #
|
||||
(
|
||||
.BANDWIDTH ("HIGH"),
|
||||
.COMPENSATION ("BUF_IN"),
|
||||
|
||||
.CLKIN1_PERIOD (20.0), // 50MHz
|
||||
.CLKIN2_PERIOD (10.0), // 100MHz
|
||||
|
||||
|
|
@ -35,7 +39,7 @@ PLLE2_ADV #
|
|||
.CLKFBOUT_PHASE (0.0),
|
||||
|
||||
.CLKOUT0_DIVIDE (16),
|
||||
.CLKOUT0_DUTY_CYCLE (0.5),
|
||||
.CLKOUT0_DUTY_CYCLE (0.53125),
|
||||
.CLKOUT0_PHASE (45.0),
|
||||
|
||||
.CLKOUT1_DIVIDE (32),
|
||||
|
|
@ -69,8 +73,8 @@ pll
|
|||
.RST (RST),
|
||||
.LOCKED (O_LOCKED),
|
||||
|
||||
.CLKFBIN (clk_fb),
|
||||
.CLKFBOUT (clk_fb),
|
||||
.CLKFBIN (clk_fb_i),
|
||||
.CLKFBOUT (clk_fb_o),
|
||||
|
||||
.CLKOUT0 (clk[0]),
|
||||
.CLKOUT1 (clk[1]),
|
||||
|
|
@ -80,6 +84,8 @@ pll
|
|||
.CLKOUT5 (clk[5])
|
||||
);
|
||||
|
||||
BUFG clk_fb_buf (.I(clk_fb_o), .O(clk_fb_i));
|
||||
|
||||
// ============================================================================
|
||||
// Counters
|
||||
|
||||
|
|
|
|||
|
|
@ -13,4 +13,4 @@ route_design
|
|||
|
||||
write_checkpoint -force ../$env(PROJECT_NAME).dcp
|
||||
|
||||
write_bitstream -force ../$env(PROJECT_NAME).bit
|
||||
write_bitstream -force -logic_location_file ../$env(PROJECT_NAME).bit
|
||||
|
|
|
|||
Loading…
Reference in New Issue