mirror of https://github.com/openXC7/prjxray.git
037-ioi-pips: fixed and cleaned fuzzer
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi
parent
e3b5fe97f4
commit
089b2c447e
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@ -22,8 +22,6 @@ SEGBITS=\
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dsp \
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hclk \
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int \
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ioi \
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ioi3 \
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SEGBITS_R=\
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clk_bufg_top \
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@ -41,6 +39,10 @@ DB_SIMPLE=\
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$(addsuffix _r, $(DB_SIMPLE_LR) $(DB_SIMPLE_R)) \
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segbits_cmt_top_l_upper_t \
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segbits_cmt_top_r_upper_t \
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segbits_lioi3 \
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segbits_rioi3 \
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segbits_liob33 \
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segbits_riob33
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BLOCK_RAM_EXTRA_FOR=\
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mask_bram \
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@ -2,12 +2,15 @@ export FUZDIR=$(shell pwd)
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PIP_TYPE?=ioi3
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PIPLIST_TCL=$(FUZDIR)/ioi3_pip_list.tcl
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TODO_RE="[LR]IOI3\.(IOI_([IO]LOGIC[01]_CLK(DIV|B)?)|(IOI_OCLK_[01]))\.IOI_LEAF_GCLK[0-9]"
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TODO_RE="[LR]IOI3\.(IOI_([IO]LOGIC[01]_CLK(DIV|B)?)|(IOI_OCLK_[01]))\..*"
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EXCLUDE_RE=".*\..*\.(?=IOI_((PHASER)|(OCLK)|(IMUX22_1))).*"
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MAKETODO_FLAGS=--pip-type ${PIP_TYPE} --seg-type $(PIP_TYPE) --re $(TODO_RE)
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MAKETODO_FLAGS=--pip-type ${PIP_TYPE} --seg-type $(PIP_TYPE) --re $(TODO_RE) --sides "xr,xl" --exclude-re $(EXCLUDE_RE)
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N = 40
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SEGMATCH_FLAGS=-c -1 -m 15 -M 30
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A_PIPLIST=lioi3.txt
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SEGMATCH_FLAGS=-c -1 -m 20 -M 50
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SPECIMENS_DEPS=build/cmt_regions.csv
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include ../pip_loop.mk
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@ -27,22 +30,21 @@ database: ${RDBS}
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cp build/segbits_ioi3_x.rdb build/$(ITER)/segbits_ioi3_x.rdb
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cp build/segbits_ioi3_x.db build/$(ITER)/segbits_ioi3_x.db
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${XRAY_MASKMERGE} build/mask_xioi3.db \
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$(shell find build -name segdata_ioi3_l.txt) \
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$(shell find build -name segdata_ioi3_r.txt)
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# Clobber existing .db to eliminate potential conflicts
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cp ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/segbits*.db build/database/${XRAY_DATABASE}
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XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} ioi3_l build/segbits_ioi3_x.db
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XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} ioi3_r build/segbits_ioi3_x.db
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XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} lioi3 build/segbits_ioi3_x.db
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XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} rioi3 build/segbits_ioi3_x.db
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build/cmt_regions.csv: output_cmt.tcl
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mkdir -p build
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cd build/ && ${XRAY_VIVADO} -mode batch -source ${FUZDIR}/output_cmt.tcl
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pushdb:
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pushdb: database
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${XRAY_MERGEDB} lioi3 build/segbits_ioi3_x.db
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${XRAY_MERGEDB} rioi3 build/segbits_ioi3_x.db
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${XRAY_MERGEDB} lioi3_tbytesrc build/segbits_ioi3_x.db
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${XRAY_MERGEDB} rioi3_tbytesrc build/segbits_ioi3_x.db
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${XRAY_MERGEDB} lioi3_tbyteterm build/segbits_ioi3_x.db
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${XRAY_MERGEDB} rioi3_tbyteterm build/segbits_ioi3_x.db
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.PHONY: database pushdb
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@ -19,7 +19,7 @@ def main():
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ignpip = set()
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
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'ioi3', 'ioi3_l.txt')) as f:
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'ioi3', 'lioi3.txt')) as f:
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for l in f:
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tile_type, dst, src = l.strip().split('.')
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if tile_type not in pipdata:
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@ -28,7 +28,7 @@ def main():
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pipdata[tile_type].append((src, dst))
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
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'ioi3', 'ioi3_r.txt')) as f:
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'ioi3', 'rioi3.txt')) as f:
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for l in f:
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tile_type, dst, src = l.strip().split('.')
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if tile_type not in pipdata:
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@ -23,192 +23,6 @@ proc write_pip_txtdata {filename} {
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close $fp
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}
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proc load_todo {} {
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set fp [open "../todo.txt" r]
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# Create map of pip source to remaining destinations for that pip
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set todo_map [dict create]
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for {gets $fp line} {$line != ""} {gets $fp line} {
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set parts [split $line .]
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dict lappend todo_map [lindex $parts 1] [list [lindex $parts 0] [lindex $parts 2]]
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}
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close $fp
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return $todo_map
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}
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proc route_todo {} {
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puts "Checking TODO's"
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set todo_map [load_todo]
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puts $todo_map
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set nets [get_nets]
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set todo_nets [dict create]
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set used_sources [dict create]
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foreach net $nets {
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# Check to see if this net is one we are interested in
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set wires [get_wires -of_objects $net -filter {TILE_NAME =~ *IOI3*}]
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set is_gclk_net 0
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foreach wire $wires {
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if [regexp "IOI_\[IO\]LOGIC\[01\]_CLKB?" $wire] {
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set is_gclk_net 1
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break
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}
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if [regexp "IOI_OCLK_\[01\]" $wire] {
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set is_gclk_net 1
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break
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}
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if [regexp "IOI_\[IO\]LOGIC\[01\]_CLKDIV" $wire] {
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set is_gclk_net 1
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break
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}
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}
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if {$is_gclk_net == 0} {
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puts "$net not going to a IOI3 port, skipping."
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continue
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}
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foreach wire $wires {
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set tile [lindex [split $wire /] 0]
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set wire [lindex [split $wire /] 1]
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set tile_type [get_property TILE_TYPE [get_tiles $tile]]
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if { ![dict exists $todo_map $wire] } {
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continue
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}
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set srcs [dict get $todo_map $wire]
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# This net is interesting, see if it is already going somewhere we
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# want.
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set found_target 0
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foreach other_wire $wires {
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if { $found_target == 1 } {
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break
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}
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set other_wire [lindex [split $other_wire /] 1]
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if { $wire == $other_wire } {
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continue
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}
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foreach src $srcs {
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set src_tile_type [lindex $src 0]
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if {$src_tile_type != $tile_type} {
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continue
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}
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set src_wire [lindex $src 1]
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if { $other_wire == $src } {
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set found_target 1
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puts "Interesting net $net already going from $wire to $other_wire."
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break
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}
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}
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}
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if { $found_target == 1 } {
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# Net has an interesting
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continue
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}
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dict set todo_nets $net [list $tile $wire]
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puts "Interesting net $net (including $wire) is being rerouted."
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}
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}
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dict for {net tile_wire} $todo_nets {
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set tile [lindex $tile_wire 0]
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set wire [lindex $tile_wire 1]
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set srcs [dict get $todo_map $wire]
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set site [lindex [get_sites -of_objects [get_tiles $tile]] 0]
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set region [get_clock_regions -of_objects [get_sites $site]]
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puts "Rerouting net $net at $tile / $wire (type $tile_type)"
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set tile_type [get_property TILE_TYPE [get_tiles $tile]]
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set todos {}
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foreach src $srcs {
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set src_tile_type [lindex $src 0]
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if {$src_tile_type != $tile_type} {
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continue
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}
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set src_wire [lindex $src 1]
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set is_gclk_net 0
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if [regexp "IOI_LEAF_GCLK\[0-9\]+" $src_wire] {
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set is_gclk_net 1
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}
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if {$is_gclk_net == 0} {
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continue
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}
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lappend todos $src_wire
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}
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puts "All todos for $tile_type / $wire"
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foreach src_wire $todos {
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puts " - $src_wire"
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}
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route_design -unroute -nets $net
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# Find an input in the todo list that this can can drive.
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foreach src_wire $todos {
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puts "Attempting to route to $src_wire for net $net."
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set target_wire [get_wires "$tile/$src_wire"]
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set target_node [get_nodes -of_objects $target_wire]
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if {[llength $target_node] == 0} {
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error "Failed to find node for $tile/$src_wire."
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}
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if { [regexp ".*TOP.*" $target_node match group] } {
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set loc TOP
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} elseif { [regexp ".*BOT.*" $target_node match group] } {
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set loc BOT
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}
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if { [dict exists $used_sources "$region/$loc/$src_wire"] } {
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puts "Not routing to $tile / $src_wire, in use."
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continue
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}
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set old_nets [get_nets -of_objects $target_node]
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if { $old_nets != {} } {
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set old_nets_property [get_property IS_ROUTE_FIXED [get_nets -of_objects $target_node]]
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if { $old_nets_property == 0 } {
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route_design -unroute -nets $old_nets
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}
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}
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set origin_node [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]]
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set new_route [find_routing_path -to $target_node -from $origin_node]
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puts "Origin node: $origin_node"
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puts "Target wire: $target_wire"
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puts "Target node: $target_node"
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# Only need to set route to one of the destinations.
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# Router will handle the rest.
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set_property FIXED_ROUTE $new_route $net
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dict set used_sources "$region/$loc/$src_wire" 1
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break
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}
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}
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}
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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@ -232,11 +46,7 @@ proc run {} {
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place_design
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write_checkpoint -force design_before_route.dcp
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route_design
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write_checkpoint -force design_before.dcp
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#route_todo
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route_design
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write_checkpoint -force design_after.dcp
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_pip_txtdata design.txt
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@ -35,9 +35,5 @@ create_project -force -part $::env(XRAY_PART) design design
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set_property design_mode PinPlanning [current_fileset]
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open_io_design -name io_1
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# Cleaning ioi3.txt pip file
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set fp [open ioi3.txt w]
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close $fp
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print_tile_pips LIOI3 ioi3_l.txt
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print_tile_pips RIOI3 ioi3_r.txt
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print_tile_pips LIOI3 lioi3.txt
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print_tile_pips RIOI3 rioi3.txt
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@ -11,21 +11,6 @@ NOT_INCLUDED_TILES = ['LIOI3_SING', 'RIOI3_SING']
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SITE_TYPES = ['OLOGICE3', 'ILOGICE3']
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MAX_REG_CLK_BUF = 2
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MAX_GLB_CLK_BUF = 24
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CUR_CLK = 0
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MAX_ATTEMPTS = 50
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def get_location(tile_name, divisor):
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y_location = int(tile_name.split("Y")[-1])
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if math.floor(y_location / divisor) % 2 == 0:
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# Location is on the bottom of the row/tile
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return "BOT"
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else:
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return "TOP"
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def read_site_to_cmt():
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""" Yields clock sources and which CMT they route within. """
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@ -50,11 +35,7 @@ def gen_sites():
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gridinfo = grid.gridinfo_at_loc(loc)
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tile_type = gridinfo.tile_type
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tile = {
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'tile': tile_name,
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'tile_type': tile_type,
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'ioi_sites': {}
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}
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tile = {'tile': tile_name, 'tile_type': tile_type, 'ioi_sites': {}}
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for site_name, site_type in gridinfo.sites.items():
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if site_type in SITE_TYPES:
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@ -87,53 +68,62 @@ class ClockSources(object):
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for site, cmt in self.site_to_cmt.items():
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clk = 'clk_' + site
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if 'BUFHCE' in site:
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print("""
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print(
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"""
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wire {clk};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFH bufh_{site}(
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.O({clk})
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);
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""".format(
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clk=clk,
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site=site,
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clk=clk,
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site=site,
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))
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self.leaf_gclks[cmt].append(clk)
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if 'BUFIO' in site:
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print("""
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print(
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"""
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wire {clk};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFIO bufio_{site}(
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.O({clk})
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);
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""".format(
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clk=clk,
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site=site,
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clk=clk,
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site=site,
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))
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self.ioclks[cmt].append(clk)
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if 'BUFR' in site:
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print("""
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print(
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"""
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wire {clk};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFR bufr_{site}(
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.O({clk})
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);
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""".format(
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clk=clk,
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site=site,
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clk=clk,
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site=site,
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))
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self.rclks[cmt].append(clk)
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# Choose 6 leaf_gclks to be used in each CMT.
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for cmt in self.leaf_gclks:
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self.selected_leaf_gclks[cmt] = random.choices(self.leaf_gclks[cmt], k=6)
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self.selected_leaf_gclks[cmt] = random.sample(
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self.leaf_gclks[cmt], 6)
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def get_clock(self, site, allow_ioclks, allow_rclks, allow_fabric=True, allow_empty=True):
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def get_clock(
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self,
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site,
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allow_ioclks,
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allow_rclks,
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allow_fabric=True,
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allow_empty=True):
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cmt = self.site_to_cmt[site]
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choices = []
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if allow_fabric:
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@ -160,12 +150,12 @@ class ClockSources(object):
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def add_port(ports, port, signal):
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ports.append('.{}({})'.format(port, signal))
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def run():
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print("module top();")
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clocks = ClockSources()
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clocks.init_clocks()
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"""
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ISERDESE2 clock sources:
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@ -201,7 +191,6 @@ def run():
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if tile['tile_type'] in NOT_INCLUDED_TILES:
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continue
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for xy in tile['ioi_sites']:
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ilogic_site_type = random.choice([None, 'ISERDESE2', 'IDDR'])
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use_oserdes = random.randint(0, 1)
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@ -211,62 +200,59 @@ def run():
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if use_oserdes:
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oclk, _ = clocks.get_clock(
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ologic_site,
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allow_ioclks=True,
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allow_rclks=True)
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ologic_site, allow_ioclks=True, allow_rclks=True)
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oclkb = oclk
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else:
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oclk, is_lut = clocks.get_clock(
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ilogic_site,
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allow_ioclks=True,
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allow_rclks=True)
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ilogic_site, allow_ioclks=True, allow_rclks=True)
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if random.randint(0, 1):
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oclkb = oclk
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else:
|
||||
oclkb, _ = clocks.get_clock(
|
||||
ilogic_site,
|
||||
allow_ioclks=True,
|
||||
allow_rclks=True,
|
||||
allow_fabric=not is_lut)
|
||||
ilogic_site,
|
||||
allow_ioclks=True,
|
||||
allow_rclks=True,
|
||||
allow_fabric=not is_lut)
|
||||
|
||||
DATA_RATE = random.choice(['DDR', 'SDR'])
|
||||
clk, is_lut = clocks.get_clock(
|
||||
ilogic_site,
|
||||
allow_ioclks=True,
|
||||
allow_rclks=True,
|
||||
allow_empty=DATA_RATE=='SDR')
|
||||
allow_empty=DATA_RATE == 'SDR')
|
||||
if False:
|
||||
clkb = clk
|
||||
else:
|
||||
clkb = clk
|
||||
while clkb == clk:
|
||||
clkb, _ = clocks.get_clock(
|
||||
ilogic_site,
|
||||
allow_ioclks=True,
|
||||
allow_rclks=True,
|
||||
allow_empty=False)
|
||||
ilogic_site,
|
||||
allow_ioclks=True,
|
||||
allow_rclks=True,
|
||||
allow_empty=False)
|
||||
|
||||
if ilogic_site_type is None:
|
||||
pass
|
||||
elif ilogic_site_type == 'ISERDESE2':
|
||||
INTERFACE_TYPE = random.choice([
|
||||
'MEMORY',
|
||||
'MEMORY_DDR3',
|
||||
'MEMORY_QDR',
|
||||
'NETWORKING',
|
||||
'OVERSAMPLE',
|
||||
INTERFACE_TYPE = random.choice(
|
||||
[
|
||||
'MEMORY',
|
||||
'MEMORY_DDR3',
|
||||
'MEMORY_QDR',
|
||||
'NETWORKING',
|
||||
'OVERSAMPLE',
|
||||
])
|
||||
ports = []
|
||||
|
||||
|
||||
add_port(ports, 'CLK', clk)
|
||||
add_port(ports, 'CLKB', clkb)
|
||||
add_port(ports, 'OCLK', oclk)
|
||||
add_port(ports, 'OCLKB', oclkb)
|
||||
|
||||
output.append("""
|
||||
output.append(
|
||||
"""
|
||||
(* KEEP, DONT_TOUCH, LOC="{site}" *)
|
||||
ISERDESE2 #(
|
||||
.DATA_RATE({DATA_RATE}),
|
||||
|
|
@ -283,27 +269,28 @@ def run():
|
|||
.SRVAL_Q4({SRVAL_Q4})
|
||||
) iserdes_{site}(
|
||||
{ports});""".format(
|
||||
site=ilogic_site,
|
||||
ports=',\n'.join(ports),
|
||||
DATA_RATE=verilog.quote(DATA_RATE),
|
||||
INTERFACE_TYPE=verilog.quote(INTERFACE_TYPE),
|
||||
IS_CLK_INVERTED=random.randint(0, 1),
|
||||
IS_CLKB_INVERTED=random.randint(0, 1),
|
||||
INIT_Q1=random.randint(0, 1),
|
||||
INIT_Q2=random.randint(0, 1),
|
||||
INIT_Q3=random.randint(0, 1),
|
||||
INIT_Q4=random.randint(0, 1),
|
||||
SRVAL_Q1=random.randint(0, 1),
|
||||
SRVAL_Q2=random.randint(0, 1),
|
||||
SRVAL_Q3=random.randint(0, 1),
|
||||
SRVAL_Q4=random.randint(0, 1),
|
||||
site=ilogic_site,
|
||||
ports=',\n'.join(ports),
|
||||
DATA_RATE=verilog.quote(DATA_RATE),
|
||||
INTERFACE_TYPE=verilog.quote(INTERFACE_TYPE),
|
||||
IS_CLK_INVERTED=random.randint(0, 1),
|
||||
IS_CLKB_INVERTED=random.randint(0, 1),
|
||||
INIT_Q1=random.randint(0, 1),
|
||||
INIT_Q2=random.randint(0, 1),
|
||||
INIT_Q3=random.randint(0, 1),
|
||||
INIT_Q4=random.randint(0, 1),
|
||||
SRVAL_Q1=random.randint(0, 1),
|
||||
SRVAL_Q2=random.randint(0, 1),
|
||||
SRVAL_Q3=random.randint(0, 1),
|
||||
SRVAL_Q4=random.randint(0, 1),
|
||||
))
|
||||
elif ilogic_site_type == 'IDDR':
|
||||
ports = []
|
||||
add_port(ports, 'C', clk)
|
||||
add_port(ports, 'CB', clkb)
|
||||
|
||||
output.append("""
|
||||
output.append(
|
||||
"""
|
||||
(* KEEP, DONT_TOUCH, LOC="{site}" *)
|
||||
IDDR_2CLK #(
|
||||
.INIT_Q1({INIT_Q1}),
|
||||
|
|
@ -311,11 +298,11 @@ def run():
|
|||
.SRTYPE({SRTYPE})
|
||||
) iserdes_{site}(
|
||||
{ports});""".format(
|
||||
site=ilogic_site,
|
||||
ports=',\n'.join(ports),
|
||||
INIT_Q1=random.randint(0, 1),
|
||||
INIT_Q2=random.randint(0, 1),
|
||||
SRTYPE=verilog.quote(random.choice(['ASYNC','SYNC'])),
|
||||
site=ilogic_site,
|
||||
ports=',\n'.join(ports),
|
||||
INIT_Q1=random.randint(0, 1),
|
||||
INIT_Q2=random.randint(0, 1),
|
||||
SRTYPE=verilog.quote(random.choice(['ASYNC', 'SYNC'])),
|
||||
))
|
||||
else:
|
||||
assert False, ilogic_site_type
|
||||
|
|
@ -323,23 +310,26 @@ def run():
|
|||
if use_oserdes:
|
||||
ports = []
|
||||
|
||||
add_port(ports, 'CLKDIV', clocks.get_clock(
|
||||
add_port(
|
||||
ports, 'CLKDIV',
|
||||
clocks.get_clock(
|
||||
ologic_site,
|
||||
allow_ioclks=False,
|
||||
allow_rclks=True,
|
||||
)[0])
|
||||
)[0])
|
||||
|
||||
add_port(ports, 'CLK', oclk)
|
||||
|
||||
output.append("""
|
||||
output.append(
|
||||
"""
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
OSERDESE2 #(
|
||||
.DATA_RATE_OQ("SDR"),
|
||||
.DATA_RATE_TQ("SDR")
|
||||
) oserdes_{site} (
|
||||
{ports});""".format(
|
||||
site=ologic_site,
|
||||
ports=',\n'.join(ports),
|
||||
site=ologic_site,
|
||||
ports=',\n'.join(ports),
|
||||
))
|
||||
|
||||
for s in clocks.lut_maker.create_wires_and_luts():
|
||||
|
|
|
|||
|
|
@ -209,12 +209,18 @@ def run(
|
|||
if side == "r" and not r:
|
||||
continue
|
||||
|
||||
if side != "":
|
||||
side = "_" + side
|
||||
if side == "xl":
|
||||
filename = "l{}".format(pip_type)
|
||||
elif side == "xr":
|
||||
filename = "r{}".format(pip_type)
|
||||
elif side == "l" or side == "r":
|
||||
filename = "{}_{}".format(pip_type, side)
|
||||
else:
|
||||
filename = "{}".format(pip_type)
|
||||
|
||||
maketodo(
|
||||
"%s/%s%s.txt" % (pip_dir, pip_type, side),
|
||||
"%s/segbits_%s%s.db" % (db_dir, seg_type, side),
|
||||
"%s/%s.txt" % (pip_dir, filename),
|
||||
"%s/segbits_%s.db" % (db_dir, filename),
|
||||
intre,
|
||||
exclude_re=exclude_re,
|
||||
balance_wire_re=balance_wire_re,
|
||||
|
|
|
|||
|
|
@ -144,12 +144,6 @@ case "$1" in
|
|||
hclk_ioi3)
|
||||
cp "$2" "$tmp1" ;;
|
||||
|
||||
ioi3_l)
|
||||
sed < "$2" > "$tmp1" -e 's/^IOI3\./LIOI3./' ;;
|
||||
|
||||
ioi3_r)
|
||||
sed < "$2" > "$tmp1" -e 's/^IOI3\./RIOI3./' ;;
|
||||
|
||||
mask_*)
|
||||
db=$XRAY_DATABASE_DIR/$XRAY_DATABASE/$1.db
|
||||
ismask=true
|
||||
|
|
|
|||
Loading…
Reference in New Issue