mirror of https://github.com/openXC7/prjxray.git
hclk-ioi: re-added whole top.py file to avoid having const1
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi
parent
1ad84b2b44
commit
0cf48f337a
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@ -284,7 +284,7 @@ module top();
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for cmt in site_to_cmt.values():
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idelayctrl_in_clock_region[cmt] = False
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for _, site in gen_sites('IDELAYCTRL'):
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if random.random() < 0.8:
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if random.random() < 0.5:
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wire_name = global_clock_sources.get_random_source(
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site_to_cmt[site], no_repeats=False)
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if wire_name is None:
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@ -305,8 +305,163 @@ module top();
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.RST()
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);""".format(site=site, clock_source=wire_name))
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# Add SERDES driven by BUFH or MMCM
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for tile, site in gen_sites('ILOGICE3'):
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wire_name = None
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clock_region = site_to_cmt[site]
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if clock_region not in clock_region_limit:
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# Select serdes limit and relative location per clock region
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serdes_location = random.choice(["TOP", "BOTTOM", "ANY"])
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if serdes_location in "ANY":
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#We want TOP and BOTTOM IGCLK PIPs occupied but leave one slot for IDELAYCTRL
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if idelayctrl_in_clock_region[clock_region]:
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clock_region_limit[clock_region] = 0 if random.random(
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) < 0.2 else 11
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else:
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clock_region_limit[clock_region] = 0 if random.random(
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) < 0.2 else 12
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else:
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if idelayctrl_in_clock_region[clock_region]:
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clock_region_limit[clock_region] = 0 if random.random(
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) < 0.2 else 5
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else:
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clock_region_limit[clock_region] = 0 if random.random(
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) < 0.2 else 6
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clock_region_serdes_location[clock_region] = serdes_location
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# We reached the limit of hclks in this clock region
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if clock_region_limit[clock_region] == 0:
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continue
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# Add a serdes if it's located at the correct side from the HCLK_IOI tile
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if clock_region_serdes_location[clock_region] not in "ANY" and \
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serdes_relative_location(tile, site) != clock_region_serdes_location[clock_region]:
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continue
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if random.random() > 0.1:
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wire_name = global_clock_sources.get_random_source(
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site_to_cmt[site], no_repeats=True)
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if wire_name is None:
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continue
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src_cmt = global_clock_sources.source_to_cmt[wire_name]
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wire_name = check_hclk_src(wire_name, src_cmt)
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if wire_name is None:
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print("//wire is None")
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continue
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clock_region_limit[clock_region] -= 1
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print(
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"""
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assign serdes_clk_{site} = {clock_source};""".format(
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site=site, clock_source=wire_name))
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else:
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wire_name = cmt_fast_clock_sources.get_random_source(
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site_to_cmt[site], no_repeats=False)
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if wire_name is None:
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continue
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src_cmt = cmt_fast_clock_sources.source_to_cmt[wire_name]
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wire_name = check_cmt_clk_src(wire_name, src_cmt)
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if wire_name is None:
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continue
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bufio_site = get_clock_region_site("BUFIO", clock_region)
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if bufio_site is None:
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continue
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print(
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"""
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assign serdes_clk_{serdes_loc} = O_{site};
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assign I_{site} = {clock_source};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFIO bufio_{site} (
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.O(O_{site}),
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.I(I_{site})
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);""".format(site=bufio_site, clock_source=wire_name, serdes_loc=site))
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print(
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"// clock_region: {} {}".format(
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clock_region, clock_region_serdes_location[clock_region]))
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print(
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"""
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(* KEEP, DONT_TOUCH, LOC = "{loc}" *)
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ISERDESE2 #(
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.DATA_RATE("SDR"),
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.DATA_WIDTH(4),
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.DYN_CLKDIV_INV_EN("FALSE"),
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.DYN_CLK_INV_EN("FALSE"),
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.INIT_Q1(1'b0),
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.INIT_Q2(1'b0),
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.INIT_Q3(1'b0),
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.INIT_Q4(1'b0),
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.INTERFACE_TYPE("OVERSAMPLE"),
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.IOBDELAY("NONE"),
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.NUM_CE(2),
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.OFB_USED("FALSE"),
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.SERDES_MODE("MASTER"),
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.SRVAL_Q1(1'b0),
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.SRVAL_Q2(1'b0),
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.SRVAL_Q3(1'b0),
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.SRVAL_Q4(1'b0)
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)
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ISERDESE2_inst_{loc} (
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.CLK(serdes_clk_{loc}),
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.CLKB(),
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.CLKDIV(),
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.D(1'b0),
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.DDLY(),
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.OFB(),
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.OCLKB(),
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.RST(),
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.SHIFTIN1(),
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.SHIFTIN2()
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);
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""".format(loc=site, clock_source=wire_name))
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# BUFRs
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for _, site in gen_sites('BUFR'):
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if random.random() < 0.6:
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if random.random() < 0.5:
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wire_name = luts.get_next_output_net()
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else:
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wire_name = cmt_fast_clock_sources.get_random_source(
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site_to_cmt[site], no_repeats=False)
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if wire_name is None:
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continue
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src_cmt = cmt_fast_clock_sources.source_to_cmt[wire_name]
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wire_name = check_cmt_clk_src(wire_name, src_cmt)
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if wire_name is None:
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continue
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bufr_clock_sources.add_clock_source(
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'O_{site}'.format(site=site), site_to_cmt[site])
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# Add DIVIDE
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divide = "BYPASS"
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if random.random() < 0.5:
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divide = "".format(random.randint(2, 8))
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print(
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"""
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assign I_{site} = {clock_source};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFR #(.BUFR_DIVIDE("{divide}")) bufr_{site} (
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.O(O_{site}),
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.I(I_{site})
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);""".format(site=site, clock_source=wire_name, divide=divide),
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file=bufs)
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for _, site in gen_sites('MMCME2_ADV'):
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wire_name = bufr_clock_sources.get_random_source(
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site_to_cmt[site], no_repeats=True)
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if wire_name is None:
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continue
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print(
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"""
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assign cin1_{site} = {wire_name};""".format(
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site=site, wire_name=wire_name))
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print(bufs.getvalue())
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for l in luts.create_wires_and_luts():
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print(l)
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print("endmodule")
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