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Update 035a using knowledge from #954 tool. 

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2019-07-22 10:30:12 -07:00
parent ae526981a2
commit ff4425b91a
2 changed files with 20 additions and 3 deletions
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14
fuzzers/035a-iob-idelay/bits.dbf
View File

@ -0,0 +1,14 @@
34_08 34_14 ,IOI3.IDELAY_Y1.IDELAY_TYPE_FIXED
35_113 35_119 ,IOI3.IDELAY_Y0.IDELAY_TYPE_FIXED
34_120 34_122
34_114 34_116
34_108 34_110
34_100 34_102
34_94 34_96
35_05 35_07
35_11 35_13
35_17 35_19
35_25 35_27
35_31 35_33
34_72 35_69
34_58 35_55

9
fuzzers/035a-iob-idelay/generate.py
View File

@ -1,7 +1,7 @@
#!/usr/bin/env python3
import json
from prjxray.segmaker import Segmaker
from prjxray.segmaker import Segmaker, add_site_group_zero
from prjxray import util
from prjxray import verilog
@ -22,14 +22,16 @@ for params in data:
value = verilog.unquote(params["IDELAY_TYPE"])
value = value.replace(
"_PIPE", "") # VAR_LOAD and VAR_LOAD_PIPE are the same
for x in idelay_types:
segmk.add_site_tag(loc, "IDELAY_TYPE_%s" % x, int(value == x))
add_site_group_zero(
segmk, loc, "IDELAY_TYPE_", idelay_types, "FIXED", value)
# Delay value
value = int(params["IDELAY_VALUE"])
for i in range(5):
segmk.add_site_tag(
loc, "IDELAY_VALUE[%01d]" % i, ((value >> i) & 1) != 0)
segmk.add_site_tag(
loc, "ZIDELAY_VALUE[%01d]" % i, ((value >> i) & 1) == 0)
# Delay source
value = verilog.unquote(params["DELAY_SRC"])
@ -47,6 +49,7 @@ for params in data:
if "IS_C_INVERTED" in params:
segmk.add_site_tag(loc, "IS_C_INVERTED", int(params["IS_C_INVERTED"]))
segmk.add_site_tag(loc, "ZINV_C", 1 ^ int(params["IS_C_INVERTED"]))
segmk.add_site_tag(
loc, "IS_DATAIN_INVERTED", int(params["IS_DATAIN_INVERTED"]))