mirror of https://github.com/openXC7/prjxray.git
Merge pull request #1229 from litghost/serdes_timing
I/OSERDES BEL timing
This commit is contained in:
litghost
GitHub
commit
541d88c999
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@ -19,6 +19,7 @@ build/fixup_timings: build/run.ok
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python3 fixup_timings_txt.py --txtin build/bel_pins.txt --txtout build/bel_pins.txt --site RAMBFIFO36E1 --slice BRAM_R --type pins
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python3 fixup_timings_txt.py --txtin build/bel_properties.txt --txtout build/bel_properties.txt --site RAMBFIFO36E1 --slice BRAM_L --type properties
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python3 fixup_timings_txt.py --txtin build/bel_properties.txt --txtout build/bel_properties.txt --site RAMBFIFO36E1 --slice BRAM_R --type properties
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touch build/fixup_timings
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build/bel_timings.json: build/fixup_timings
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python3 tim2json.py --timings=build/bel_timings.txt --json=build/bel_timings.json --properties=build/bel_properties.txt --propertiesmap=properties_map.json --pinaliasmap=pin_alias_map.json --belpins=build/bel_pins.txt --sitepins=build/tile_pins.txt --debug true
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@ -56,7 +56,7 @@ def fix_line(line, site, filetype):
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entries.append(line[loc])
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loc += 1
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elif filetype == 'pins':
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for pin_word in range(0, 3):
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for pin_word in range(0, 4):
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entries.append(line[loc])
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loc += 1
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elif filetype == 'properties':
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@ -56,8 +56,9 @@ proc dump_tile_timings {tile timing_fp config_fp pins_fp tile_pins_fp} {
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foreach pin $site_pins {
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set direction [get_property DIRECTION $pin]
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set is_part_of_bus [get_property IS_PART_OF_BUS $pin]
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regexp {\/(.*)$} $pin -> pin
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lappend tile_pins_line $pin $direction
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lappend tile_pins_line $pin $direction $is_part_of_bus
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}
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# dump bel pins, speed_models and configs
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@ -78,8 +79,9 @@ proc dump_tile_timings {tile timing_fp config_fp pins_fp tile_pins_fp} {
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foreach pin $bel_pins {
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set direction [get_property DIRECTION $pin]
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set is_clock [get_property IS_CLOCK $pin]
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set is_part_of_bus [get_property IS_PART_OF_BUS $pin]
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regexp {\/.*\/(.*)$} $pin -> pin
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lappend pins_line $pin $direction $is_clock
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lappend pins_line $pin $direction $is_clock $is_part_of_bus
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}
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lappend config_line $bel_type
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@ -123,6 +125,17 @@ proc dump {} {
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set tile [randsample_list 1 [get_tiles -filter "TYPE == $type"]]
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dump_tile_timings $tile $timing_fp $property_fp $pins_fp $tile_pins_fp
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}
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set other_site_types [list ISERDESE2 OSERDESE2]
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foreach site_type $other_site_types {
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set cell [create_cell -reference $site_type test]
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place_design
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set tile [get_tiles -of [get_sites -of $cell]]
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dump_tile_timings $tile $timing_fp $property_fp $pins_fp $tile_pins_fp
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unplace_cell $cell
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remove_cell $cell
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}
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close $pins_fp
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close $timing_fp
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close $property_fp
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@ -1,7 +1,11 @@
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#!/usr/bin/env python3
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import re
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import argparse
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import json
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import functools
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NUMBER_RE = re.compile(r'\d+$')
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def check_sequential(speed_model):
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@ -120,7 +124,7 @@ def instance_in_model(instance, model):
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return instance in model
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def pin_in_model(pin, pin_aliases, model, direction=None):
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def create_pin_in_model(pin_aliases):
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"""
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Checks if a given pin belongs to the model.
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@ -145,45 +149,50 @@ def pin_in_model(pin, pin_aliases, model, direction=None):
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The second returned value contains found pin name. If the
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pin is not found, None is returned.
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>>> pin_in_model("d", None, "ff_init_din_q", "in")
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>>> create_pin_in_model(None)("d", "ff_init_din_q", "in")
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(True, 'din')
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>>> pin_in_model("q", None, "ff_init_clk_q", None)
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>>> create_pin_in_model(None)("q", "ff_init_clk_q", None)
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(True, 'q')
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>>> pin_in_model("q", {"Q": {"names" : ["QL", "QH"], "is_property_related" : True}}, "ff_init_clk_ql", None)
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>>> create_pin_in_model({"Q": {"names" : ["QL", "QH"], "is_property_related" : True}})("q", "ff_init_clk_ql", None)
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(True, 'q')
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>>> pin_in_model("logic_out", None, "my_cell_i_logic_out", None)
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>>> create_pin_in_model(None)("logic_out", "my_cell_i_logic_out", None)
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(True, 'logic_out')
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>>> pin_in_model("logic_out", {"LOGIC_OUT": {"names" : ["LOGIC_O", "O"], "is_property_related" : False}}, "my_cell_i_logic_o", None)
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>>> create_pin_in_model({"LOGIC_OUT": {"names" : ["LOGIC_O", "O"], "is_property_related" : False}})("logic_out", "my_cell_i_logic_o", None)
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(True, 'logic_o')
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>>> pin_in_model("logic_out", {"LOGIC_OUT": {"names" : ["LOGIC_O", "O"], "is_property_related" : False}}, "my_cell_i_o", None)
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>>> create_pin_in_model({"LOGIC_OUT": {"names" : ["LOGIC_O", "O"], "is_property_related" : False}})("logic_out", "my_cell_i_o", None)
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(True, 'o')
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"""
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# strip site location
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model = model.split(':')[0]
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extended_pin_name = pin
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aliased_pin, aliased_pin_name = find_aliased_pin(
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pin.upper(), model, pin_aliases)
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@functools.lru_cache(maxsize=10000)
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def pin_in_model(pin, model, direction=None):
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# strip site location
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model = model.split(':')[0]
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# some timings reports pins with their directions
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# this happens for e.g. CLB reg_init D pin, which
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# timing is reported as DIN
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if direction is not None:
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extended_pin_name = pin + direction
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extended_pin_name = pin
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aliased_pin, aliased_pin_name = find_aliased_pin(
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pin.upper(), model, pin_aliases)
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if instance_in_model(pin, model):
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return True, pin
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elif instance_in_model(extended_pin_name, model):
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return True, extended_pin_name
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elif aliased_pin:
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return True, aliased_pin_name
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else:
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return False, None
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# some timings reports pins with their directions
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# this happens for e.g. CLB reg_init D pin, which
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# timing is reported as DIN
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if direction is not None:
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extended_pin_name = pin + direction
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if instance_in_model(pin, model):
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return True, pin
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elif instance_in_model(extended_pin_name, model):
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return True, extended_pin_name
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elif aliased_pin:
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return True, aliased_pin_name
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else:
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return False, None
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return pin_in_model
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def remove_pin_from_model(pin, model):
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@ -227,6 +236,43 @@ def remove_pin_from_model(pin, model):
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return "_".join(list(filter(None, model.replace(pin, '').split('_'))))
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def merged_dict(itr):
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""" Create a merged dict of dict (of dict) based on input.
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Input is an iteratable of (keys, value).
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Return value is root dictionary
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Keys are successive dictionaries indicies. For example:
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(('a', 'b', 'c'), 1)
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would set:
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output['a']['b']['c'] = 1
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This function returns an error if two values conflict.
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>>> merged_dict(((('a', 'b', 'c'), 1), (('a', 'b', 'd'), 2)))
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{'a': {'b': {'c': 1, 'd': 2}}}
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"""
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output = {}
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for keys, value in itr:
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target = output
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for key in keys[:-1]:
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if key not in target:
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target[key] = {}
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target = target[key]
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if keys[-1] in target:
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assert target[keys[-1]] == value, (keys, value, target[keys[-1]])
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else:
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target[keys[-1]] = value
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return output
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def extract_properties(tile, site, bel, properties, model):
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if tile not in properties:
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@ -254,379 +300,417 @@ def extract_properties(tile, site, bel, properties, model):
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return model_properties
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def read_raw_timings(fin, properties, pins, site_pins, pin_alias_map):
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timings = dict()
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def parse_raw_timing(fin):
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with open(fin, "r") as f:
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for line in f:
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raw_data = line.split()
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slice = raw_data[0]
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#XXX: debug
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if slice.startswith('DSP'):
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continue
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sites_count = int(raw_data[1])
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loc = 2
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for site in range(0, sites_count):
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site_name = raw_data[loc]
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bels_count = int(raw_data[loc + 1])
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print(slice, site_name)
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# read all BELs data within
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loc += 2
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for bel in range(0, bels_count):
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btype = (raw_data[loc]).lower()
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bel = raw_data[loc]
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delay_count = int(raw_data[loc + 1])
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# get all the delays
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loc += 2
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for delay in range(0, delay_count):
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speed_model = raw_data[loc]
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delay_btype = clean_bname(btype)
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delay_btype_orig = delay_btype
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# all the bel names seem to start with "bel_d_"
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# let's get rid of it
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if speed_model.startswith('bel_d_'):
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speed_model = speed_model[6:]
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# keep original speed model string to use as unique dict entry
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speed_model_orig = speed_model
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# if more than one BEL type exists in the slice
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# location is added at the end of the name
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tmp = speed_model.split(':')
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speed_model = tmp[0]
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bel_location = site_name
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if len(tmp) > 2:
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bel_location += "/" + "/".join(tmp[2:])
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bel_location = bel_location.upper()
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sequential = check_sequential(speed_model)
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if sequential is not None:
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tmp = speed_model.split('_')
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tmp.remove(sequential[0])
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speed_model = '_'.join(tmp)
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bel_input = None
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bel_output = None
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bel_clock = None
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# strip btype from speed model so we can search for pins
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speed_model_clean = speed_model
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if speed_model.startswith(delay_btype):
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speed_model_clean = speed_model[len(delay_btype):]
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# remove properties from the model
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speed_model_properties = extract_properties(
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slice, site_name, delay_btype_orig, properties,
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speed_model_clean)
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if speed_model_properties is not None:
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for prop in speed_model_properties:
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# properties values in the model always follow properties name
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prop_string = "_".join(
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[prop, speed_model_properties[prop]])
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speed_model_clean = remove_pin_from_model(
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prop_string.lower(), speed_model_clean)
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# Get pin alias map
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pin_aliases = pin_alias_map.get(delay_btype, None)
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# locate pins
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for pin in pins[slice][site_name][delay_btype_orig]:
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orig_pin = pin
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pim, pin = pin_in_model(
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pin.lower(), pin_aliases, speed_model_clean,
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'in')
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if pim:
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if pins[slice][site_name][delay_btype_orig][
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orig_pin]['is_clock']:
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bel_clock = pin
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bel_clock_orig_pin = orig_pin
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elif pins[slice][site_name][delay_btype_orig][
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orig_pin]['direction'] == 'IN':
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bel_input = pin
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elif pins[slice][site_name][delay_btype_orig][
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orig_pin]['direction'] == 'OUT':
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bel_output = pin
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speed_model_clean = remove_pin_from_model(
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pin.lower(), speed_model_clean)
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# Some speed models describe delays from/to site pins instead of BEL pins
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if bel_clock is None:
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for pin in site_pins[slice][site_name.lower()]:
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orig_pin = pin
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pim, pin = pin_in_model(
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pin.lower(), pin_aliases,
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speed_model_clean)
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if pim:
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if site_pins[slice][site_name.lower(
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)][orig_pin]['is_clock']:
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bel_clock = pin
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bel_clock_orig_pin = orig_pin
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speed_model_clean = remove_pin_from_model(
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pin.lower(), speed_model_clean)
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if bel_input is None:
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# search site inputs
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for pin in site_pins[slice][site_name.lower()]:
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orig_pin = pin
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pim, pin = pin_in_model(
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pin.lower(), pin_aliases,
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speed_model_clean, 'in')
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if pim:
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if site_pins[slice][site_name.lower(
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)][orig_pin]['direction'] == 'IN':
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bel_input = pin
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speed_model_clean = remove_pin_from_model(
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pin.lower(), speed_model_clean)
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if bel_output is None:
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for pin in site_pins[slice][site_name.lower()]:
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orig_pin = pin
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pim, pin = pin_in_model(
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pin.lower(), pin_aliases,
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speed_model_clean)
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if pim:
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if site_pins[slice][site_name.lower(
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)][orig_pin]['direction'] == 'OUT':
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bel_output = pin
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speed_model_clean = remove_pin_from_model(
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pin.lower(), speed_model_clean)
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# if we couldn't find input, check if the clock is the
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# only input. This applies only to combinational paths
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if (sequential is None) and (bel_input is None) and (
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bel_clock is not None):
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if bel_clock_orig_pin in site_pins[slice][site_name.lower()] and \
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site_pins[slice][site_name.lower(
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)][bel_clock_orig_pin]['direction'] == 'IN':
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bel_input = bel_clock
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# if we still don't have the input check if the input
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# is wider than 1 bit and timing defined for the whole
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# port
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import re
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if (bel_input is None) or (bel_output is None):
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for pin in pins[slice][site_name][
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delay_btype_orig]:
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number = re.search(r'\d+$', pin)
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if number is not None:
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orig_pin = pin[:-(
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len(str(number.group())))]
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orig_pin_full = pin
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pim, pin = pin_in_model(
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orig_pin.lower(), pin_aliases,
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speed_model_clean)
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if not pim:
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# some inputs pins are named with unsignificant zeros
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# remove ti and try again
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orig_pin = orig_pin + str(
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int(number.group()))
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pim, pin = pin_in_model(
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orig_pin.lower(), pin_aliases,
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speed_model_clean)
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if pim:
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if pins[slice][site_name][delay_btype_orig][orig_pin_full]['direction'] == 'IN' \
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and bel_input is None:
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bel_input = pin
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if pins[slice][site_name][delay_btype_orig][orig_pin_full]['direction'] == 'OUT' \
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and bel_output is None:
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bel_output = pin
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speed_model_clean = remove_pin_from_model(
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orig_pin.lower(),
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speed_model_clean)
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# check if the input is not a BEL property
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if bel_input is None:
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# if there is anything not yet decoded
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if len(speed_model_clean.split("_")) > 1:
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if len(speed_model_properties.keys()) == 1:
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bel_input = list(
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speed_model_properties.keys())[0]
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# if we still don't have input, give up
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if bel_input is None:
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loc += 6
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continue
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# restore speed model name
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speed_model = delay_btype + speed_model_clean
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if sequential is not None:
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if bel_output is None and bel_clock is None or \
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bel_output is None and bel_clock == bel_input:
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loc += 6
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continue
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else:
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if bel_input is None or bel_output is None:
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loc += 6
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continue
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delay_btype = speed_model
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# add properties to the delay_btype
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for prop in sorted(speed_model_properties):
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prop_string = "_".join(
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[prop, speed_model_properties[prop]])
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delay_btype += "_" + prop_string
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extra_ports = None
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if slice not in timings:
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timings[slice] = dict()
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if bel_location not in timings[slice]:
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timings[slice][bel_location] = dict()
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if delay_btype not in timings[slice][bel_location]:
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timings[slice][bel_location][delay_btype] = dict()
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timings[slice][bel_location][delay_btype][
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speed_model_orig] = dict()
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timings[slice][bel_location][delay_btype][
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speed_model_orig]['type'] = btype.upper()
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timings[slice][bel_location][delay_btype][
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speed_model_orig]['input'] = bel_input.upper()
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||||
if bel_output is not None:
|
||||
timings[slice][bel_location][delay_btype][
|
||||
speed_model_orig]['output'] = bel_output.upper(
|
||||
)
|
||||
if bel_clock is not None:
|
||||
timings[slice][bel_location][delay_btype][
|
||||
speed_model_orig]['clock'] = bel_clock.upper()
|
||||
timings[slice][bel_location][delay_btype][
|
||||
speed_model_orig]['location'] = bel_location.upper(
|
||||
)
|
||||
|
||||
#XXX: debug
|
||||
timings[slice][bel_location][delay_btype][
|
||||
speed_model_orig]['model'] = speed_model_orig
|
||||
if sequential is not None:
|
||||
timings[slice][bel_location][delay_btype][
|
||||
speed_model_orig]['sequential'] = sequential[1]
|
||||
if extra_ports is not None:
|
||||
timings[slice][bel_location][delay_btype][
|
||||
speed_model_orig]['extra_ports'] = extra_ports
|
||||
|
||||
# each timing entry reports 5 delays
|
||||
for d in range(0, 5):
|
||||
(t, v) = raw_data[d + 1 + loc].split(':')
|
||||
timings[slice][bel_location][delay_btype][
|
||||
speed_model_orig][t] = v
|
||||
timing = [
|
||||
raw_data[d + 1 + loc].split(':')
|
||||
for d in range(0, 5)
|
||||
]
|
||||
|
||||
yield slice, site_name, bel, speed_model, timing
|
||||
|
||||
# 5 delay values + name
|
||||
loc += 6
|
||||
return timings
|
||||
|
||||
|
||||
def read_raw_timings(fin, properties, pins, site_pins, pin_alias_map):
|
||||
def inner():
|
||||
raw = list(parse_raw_timing(fin))
|
||||
|
||||
pin_in_models = {}
|
||||
|
||||
for slice, site_name, bel, speed_model, timing in raw:
|
||||
btype = bel.lower()
|
||||
delay_btype = clean_bname(btype)
|
||||
delay_btype_orig = delay_btype
|
||||
|
||||
# all the bel names seem to start with "bel_d_"
|
||||
# let's get rid of it
|
||||
if speed_model.startswith('bel_d_'):
|
||||
speed_model = speed_model[6:]
|
||||
|
||||
# keep original speed model string to use as unique dict entry
|
||||
speed_model_orig = speed_model
|
||||
|
||||
# if more than one BEL type exists in the slice
|
||||
# location is added at the end of the name
|
||||
tmp = speed_model.split(':')
|
||||
speed_model = tmp[0]
|
||||
|
||||
bel_location = site_name
|
||||
if len(tmp) > 2:
|
||||
bel_location += "/" + "/".join(tmp[2:])
|
||||
|
||||
bel_location = bel_location.upper()
|
||||
|
||||
sequential = check_sequential(speed_model)
|
||||
if sequential is not None:
|
||||
tmp = speed_model.split('_')
|
||||
tmp.remove(sequential[0])
|
||||
speed_model = '_'.join(tmp)
|
||||
|
||||
bel_input = None
|
||||
bel_output = None
|
||||
bel_clock = None
|
||||
|
||||
# strip btype from speed model so we can search for pins
|
||||
speed_model_clean = speed_model
|
||||
if speed_model.startswith(delay_btype):
|
||||
speed_model_clean = speed_model[len(delay_btype):]
|
||||
|
||||
# remove properties from the model
|
||||
speed_model_properties = extract_properties(
|
||||
slice, site_name, delay_btype_orig, properties,
|
||||
speed_model_clean)
|
||||
if speed_model_properties is not None:
|
||||
for prop in speed_model_properties:
|
||||
# properties values in the model always follow properties name
|
||||
prop_string = "_".join(
|
||||
[prop, speed_model_properties[prop]])
|
||||
speed_model_clean = remove_pin_from_model(
|
||||
prop_string.lower(), speed_model_clean)
|
||||
|
||||
# Get pin alias map
|
||||
if delay_btype not in pin_in_models:
|
||||
pin_aliases = pin_alias_map.get(delay_btype, None)
|
||||
pin_in_models[delay_btype] = create_pin_in_model(pin_aliases)
|
||||
|
||||
pin_in_model = pin_in_models[delay_btype]
|
||||
|
||||
# locate pins
|
||||
for pin in pins[slice][site_name][delay_btype_orig]:
|
||||
orig_pin = pin
|
||||
pim, pin = pin_in_model(pin.lower(), speed_model_clean, 'in')
|
||||
|
||||
if pim:
|
||||
if pins[slice][site_name][delay_btype_orig][orig_pin][
|
||||
'is_clock'] and not pins[slice][site_name][
|
||||
delay_btype_orig][orig_pin]['is_part_of_bus']:
|
||||
bel_clock = pin
|
||||
bel_clock_orig_pin = orig_pin
|
||||
elif pins[slice][site_name][delay_btype_orig][orig_pin][
|
||||
'direction'] == 'IN':
|
||||
bel_input = pin
|
||||
elif pins[slice][site_name][delay_btype_orig][orig_pin][
|
||||
'direction'] == 'OUT':
|
||||
bel_output = pin
|
||||
speed_model_clean = remove_pin_from_model(
|
||||
pin.lower(), speed_model_clean)
|
||||
|
||||
# Some speed models describe delays from/to site pins instead of BEL pins
|
||||
if bel_clock is None:
|
||||
for pin in site_pins[slice][site_name.lower()]:
|
||||
orig_pin = pin
|
||||
pim, pin = pin_in_model(pin.lower(), speed_model_clean)
|
||||
if pim:
|
||||
if site_pins[slice][site_name.lower(
|
||||
)][orig_pin]['is_clock'] and not site_pins[slice][
|
||||
site_name.lower()][orig_pin]['is_part_of_bus']:
|
||||
bel_clock = pin
|
||||
bel_clock_orig_pin = orig_pin
|
||||
speed_model_clean = remove_pin_from_model(
|
||||
pin.lower(), speed_model_clean)
|
||||
|
||||
if bel_input is None:
|
||||
# search site inputs
|
||||
for pin in site_pins[slice][site_name.lower()]:
|
||||
orig_pin = pin
|
||||
pim, pin = pin_in_model(
|
||||
pin.lower(), speed_model_clean, 'in')
|
||||
if pim:
|
||||
if site_pins[slice][site_name.lower(
|
||||
)][orig_pin]['direction'] == 'IN':
|
||||
bel_input = pin
|
||||
speed_model_clean = remove_pin_from_model(
|
||||
pin.lower(), speed_model_clean)
|
||||
|
||||
if bel_output is None:
|
||||
for pin in site_pins[slice][site_name.lower()]:
|
||||
orig_pin = pin
|
||||
pim, pin = pin_in_model(pin.lower(), speed_model_clean)
|
||||
if pim:
|
||||
if site_pins[slice][site_name.lower(
|
||||
)][orig_pin]['direction'] == 'OUT':
|
||||
bel_output = pin
|
||||
speed_model_clean = remove_pin_from_model(
|
||||
pin.lower(), speed_model_clean)
|
||||
|
||||
# if we couldn't find input, check if the clock is the
|
||||
# only input. This applies only to combinational paths
|
||||
if (sequential is None) and (bel_input is None) and (bel_clock is
|
||||
not None):
|
||||
if bel_clock_orig_pin in site_pins[slice][site_name.lower()] and \
|
||||
site_pins[slice][site_name.lower(
|
||||
)][bel_clock_orig_pin]['direction'] == 'IN':
|
||||
bel_input = bel_clock
|
||||
|
||||
# if we still don't have the input check if the input
|
||||
# is wider than 1 bit and timing defined for the whole
|
||||
# port
|
||||
if (bel_input is None) or (bel_output is None):
|
||||
for pin in pins[slice][site_name][delay_btype_orig]:
|
||||
number = NUMBER_RE.search(pin)
|
||||
if number is not None:
|
||||
orig_pin = pin[:-(len(str(number.group())))]
|
||||
orig_pin_full = pin
|
||||
pim, pin = pin_in_model(
|
||||
orig_pin.lower(), speed_model_clean)
|
||||
if not pim:
|
||||
# some inputs pins are named with unsignificant zeros
|
||||
# remove ti and try again
|
||||
orig_pin = orig_pin + str(int(number.group()))
|
||||
pim, pin = pin_in_model(
|
||||
orig_pin.lower(), speed_model_clean)
|
||||
|
||||
if pim:
|
||||
if pins[slice][site_name][delay_btype_orig][orig_pin_full]['direction'] == 'IN' \
|
||||
and bel_input is None:
|
||||
bel_input = pin
|
||||
if pins[slice][site_name][delay_btype_orig][orig_pin_full]['direction'] == 'OUT' \
|
||||
and bel_output is None:
|
||||
bel_output = pin
|
||||
speed_model_clean = remove_pin_from_model(
|
||||
orig_pin.lower(), speed_model_clean)
|
||||
|
||||
# check if the input is not a BEL property
|
||||
if bel_input is None:
|
||||
# if there is anything not yet decoded
|
||||
if len(speed_model_clean.split("_")) > 1:
|
||||
if len(speed_model_properties.keys()) == 1:
|
||||
bel_input = list(speed_model_properties.keys())[0]
|
||||
|
||||
# if we still don't have input, give up
|
||||
if bel_input is None:
|
||||
continue
|
||||
|
||||
# restore speed model name
|
||||
speed_model = delay_btype + speed_model_clean
|
||||
|
||||
if sequential is not None:
|
||||
if bel_clock is None:
|
||||
continue
|
||||
|
||||
if bel_output is None and bel_clock is None or \
|
||||
bel_output is None and bel_clock == bel_input:
|
||||
continue
|
||||
else:
|
||||
if bel_input is None or bel_output is None:
|
||||
continue
|
||||
|
||||
delay_btype = speed_model
|
||||
# add properties to the delay_btype
|
||||
if speed_model_properties is not None:
|
||||
for prop in sorted(speed_model_properties):
|
||||
prop_string = "_".join(
|
||||
[prop, speed_model_properties[prop]])
|
||||
delay_btype += "_" + prop_string
|
||||
|
||||
yield (slice, bel_location, delay_btype, speed_model_orig,
|
||||
'type'), btype.upper()
|
||||
yield (
|
||||
slice, bel_location, delay_btype, speed_model_orig,
|
||||
'input'), bel_input.upper()
|
||||
|
||||
if bel_output is not None:
|
||||
yield (
|
||||
slice, bel_location, delay_btype, speed_model_orig,
|
||||
'output'), bel_output.upper()
|
||||
|
||||
if bel_clock is not None:
|
||||
yield (
|
||||
slice, bel_location, delay_btype, speed_model_orig,
|
||||
'clock'), bel_clock.upper()
|
||||
|
||||
yield (
|
||||
slice, bel_location, delay_btype, speed_model_orig,
|
||||
'location'), bel_location.upper()
|
||||
|
||||
#XXX: debug
|
||||
yield (
|
||||
slice, bel_location, delay_btype, speed_model_orig,
|
||||
'model'), speed_model_orig
|
||||
|
||||
if sequential is not None:
|
||||
assert bel_clock is not None, (
|
||||
slice, bel_location, delay_btype, speed_model_orig)
|
||||
yield (
|
||||
slice, bel_location, delay_btype, speed_model_orig,
|
||||
'sequential'), sequential[1]
|
||||
|
||||
for t, v in timing:
|
||||
yield (
|
||||
slice, bel_location, delay_btype, speed_model_orig, t), v
|
||||
|
||||
return merged_dict(inner())
|
||||
|
||||
|
||||
def read_bel_properties(properties_file, properties_map):
|
||||
def inner():
|
||||
with open(properties_file, 'r') as f:
|
||||
for line in f:
|
||||
raw_props = line.split()
|
||||
tile = raw_props[0]
|
||||
sites_count = int(raw_props[1])
|
||||
prop_loc = 2
|
||||
|
||||
properties = dict()
|
||||
with open(properties_file, 'r') as f:
|
||||
for line in f:
|
||||
raw_props = line.split()
|
||||
tile = raw_props[0]
|
||||
sites_count = int(raw_props[1])
|
||||
prop_loc = 2
|
||||
properties[tile] = dict()
|
||||
for site in range(0, sites_count):
|
||||
site_name = raw_props[prop_loc]
|
||||
bels_count = int(raw_props[prop_loc + 1])
|
||||
prop_loc += 2
|
||||
properties[tile][site_name] = dict()
|
||||
for bel in range(0, bels_count):
|
||||
bel_name = raw_props[prop_loc]
|
||||
bel_name = clean_bname(bel_name)
|
||||
bel_name = bel_name.lower()
|
||||
bel_properties_count = int(raw_props[prop_loc + 1])
|
||||
properties[tile][site_name][bel_name] = dict()
|
||||
if sites_count == 0:
|
||||
yield (tile, ), {}
|
||||
|
||||
for site in range(0, sites_count):
|
||||
site_name = raw_props[prop_loc]
|
||||
bels_count = int(raw_props[prop_loc + 1])
|
||||
prop_loc += 2
|
||||
for prop in range(0, bel_properties_count):
|
||||
prop_name = raw_props[prop_loc]
|
||||
# the name always starts with "CONFIG." and ends with ".VALUES"
|
||||
# let's get rid of that
|
||||
prop_name = prop_name[7:-7]
|
||||
# append name prop name mappings
|
||||
if bel_name in properties_map:
|
||||
if prop_name in properties_map[bel_name]:
|
||||
prop_name = properties_map[bel_name][prop_name]
|
||||
prop_values_count = int(raw_props[prop_loc + 1])
|
||||
properties[tile][site_name][bel_name][
|
||||
prop_name] = raw_props[prop_loc + 2:prop_loc + 2 +
|
||||
prop_values_count]
|
||||
prop_loc += 2 + prop_values_count
|
||||
|
||||
return properties
|
||||
for bel in range(0, bels_count):
|
||||
bel_name = raw_props[prop_loc]
|
||||
bel_name = clean_bname(bel_name)
|
||||
bel_name = bel_name.lower()
|
||||
bel_properties_count = int(raw_props[prop_loc + 1])
|
||||
|
||||
props = 0
|
||||
prop_loc += 2
|
||||
for prop in range(0, bel_properties_count):
|
||||
prop_name = raw_props[prop_loc]
|
||||
|
||||
# the name always starts with "CONFIG." and ends with ".VALUES"
|
||||
# let's get rid of that
|
||||
if prop_name.startswith(
|
||||
'CONFIG.') and prop_name.endswith(
|
||||
'.VALUES'):
|
||||
prop_name = prop_name[7:-7]
|
||||
|
||||
prop_values_count = int(raw_props[prop_loc + 1])
|
||||
|
||||
if prop_name not in [
|
||||
'RAM_MODE',
|
||||
'WRITE_WIDTH_A',
|
||||
'WRITE_WIDTH_B',
|
||||
'READ_WIDTH_A',
|
||||
'READ_WIDTH_B',
|
||||
]:
|
||||
if bel_name in properties_map:
|
||||
if prop_name in properties_map[bel_name]:
|
||||
prop_name = properties_map[bel_name][
|
||||
prop_name]
|
||||
|
||||
yield (tile, site_name, bel_name, prop_name), \
|
||||
raw_props[prop_loc + 2:prop_loc + 2 +
|
||||
prop_values_count]
|
||||
props += 1
|
||||
|
||||
prop_loc += 2 + prop_values_count
|
||||
|
||||
if props == 0:
|
||||
yield (tile, site_name, bel_name), {}
|
||||
|
||||
return merged_dict(inner())
|
||||
|
||||
|
||||
def read_bel_pins(pins_file):
|
||||
def inner():
|
||||
with open(pins_file, 'r') as f:
|
||||
for line in f:
|
||||
raw_pins = line.split()
|
||||
tile = raw_pins[0]
|
||||
sites_count = int(raw_pins[1])
|
||||
pin_loc = 2
|
||||
|
||||
pins = dict()
|
||||
with open(pins_file, 'r') as f:
|
||||
for line in f:
|
||||
raw_pins = line.split()
|
||||
tile = raw_pins[0]
|
||||
sites_count = int(raw_pins[1])
|
||||
pin_loc = 2
|
||||
pins[tile] = dict()
|
||||
for site in range(0, sites_count):
|
||||
site_name = raw_pins[pin_loc]
|
||||
bels_count = int(raw_pins[pin_loc + 1])
|
||||
pin_loc += 2
|
||||
pins[tile][site_name] = dict()
|
||||
for bel in range(0, bels_count):
|
||||
bel_name = raw_pins[pin_loc]
|
||||
bel_name = clean_bname(bel_name)
|
||||
bel_name = bel_name.lower()
|
||||
bel_pins_count = int(raw_pins[pin_loc + 1])
|
||||
pins[tile][site_name][bel_name] = dict()
|
||||
if sites_count == 0:
|
||||
yield (tile, ), {}
|
||||
|
||||
for site in range(0, sites_count):
|
||||
site_name = raw_pins[pin_loc]
|
||||
bels_count = int(raw_pins[pin_loc + 1])
|
||||
pin_loc += 2
|
||||
for pin in range(0, bel_pins_count):
|
||||
pin_name = raw_pins[pin_loc]
|
||||
pin_direction = raw_pins[pin_loc + 1]
|
||||
pin_is_clock = raw_pins[pin_loc + 2]
|
||||
pins[tile][site_name][bel_name][pin_name] = dict()
|
||||
pins[tile][site_name][bel_name][pin_name][
|
||||
'direction'] = pin_direction
|
||||
pins[tile][site_name][bel_name][pin_name][
|
||||
'is_clock'] = int(pin_is_clock) == 1
|
||||
pin_loc += 3
|
||||
return pins
|
||||
|
||||
for bel in range(0, bels_count):
|
||||
bel_name = raw_pins[pin_loc]
|
||||
bel_name = clean_bname(bel_name)
|
||||
bel_name = bel_name.lower()
|
||||
bel_pins_count = int(raw_pins[pin_loc + 1])
|
||||
|
||||
pin_loc += 2
|
||||
for pin in range(0, bel_pins_count):
|
||||
pin_name = raw_pins[pin_loc]
|
||||
pin_direction = raw_pins[pin_loc + 1]
|
||||
pin_is_clock = raw_pins[pin_loc + 2]
|
||||
pin_is_part_of_bus = raw_pins[pin_loc + 3]
|
||||
|
||||
yield (
|
||||
tile, site_name, bel_name, pin_name,
|
||||
'direction'), pin_direction
|
||||
yield (
|
||||
tile, site_name, bel_name, pin_name,
|
||||
'is_clock'), int(pin_is_clock) == 1
|
||||
yield (
|
||||
tile, site_name, bel_name, pin_name,
|
||||
'is_part_of_bus'
|
||||
), int(pin_is_part_of_bus) == 1
|
||||
pin_loc += 4
|
||||
|
||||
return merged_dict(inner())
|
||||
|
||||
|
||||
def read_site_pins(pins_file):
|
||||
def inner():
|
||||
with open(pins_file, 'r') as f:
|
||||
for line in f:
|
||||
raw_pins = line.split()
|
||||
tile = raw_pins[0]
|
||||
site_count = int(raw_pins[1])
|
||||
pin_loc = 2
|
||||
|
||||
if site_count == 0:
|
||||
yield (tile, ), {}
|
||||
|
||||
for site in range(0, site_count):
|
||||
site_name = raw_pins[pin_loc]
|
||||
site_name = site_name.lower()
|
||||
site_pins_count = int(raw_pins[pin_loc + 1])
|
||||
|
||||
pins = dict()
|
||||
with open(pins_file, 'r') as f:
|
||||
for line in f:
|
||||
raw_pins = line.split()
|
||||
tile = raw_pins[0]
|
||||
site_count = int(raw_pins[1])
|
||||
pin_loc = 2
|
||||
pins[tile] = dict()
|
||||
for site in range(0, site_count):
|
||||
site_name = raw_pins[pin_loc]
|
||||
site_name = site_name.lower()
|
||||
site_pins_count = int(raw_pins[pin_loc + 1])
|
||||
pins[tile][site_name] = dict()
|
||||
pin_loc += 2
|
||||
for pin in range(0, site_pins_count):
|
||||
pin_name = raw_pins[pin_loc]
|
||||
pin_direction = raw_pins[pin_loc + 1]
|
||||
pins[tile][site_name][pin_name] = dict()
|
||||
pins[tile][site_name][pin_name][
|
||||
'direction'] = pin_direction
|
||||
# site clock pins are always named 'CLK'
|
||||
pins[tile][site_name][pin_name][
|
||||
'is_clock'] = pin_name.lower() == 'clk'
|
||||
pin_loc += 2
|
||||
return pins
|
||||
for pin in range(0, site_pins_count):
|
||||
pin_name = raw_pins[pin_loc]
|
||||
pin_direction = raw_pins[pin_loc + 1]
|
||||
pin_is_part_of_bus = raw_pins[pin_loc + 2]
|
||||
|
||||
yield (
|
||||
(tile, site_name, pin_name, 'direction'),
|
||||
pin_direction)
|
||||
yield (
|
||||
(tile, site_name, pin_name, 'is_clock'),
|
||||
pin_name.lower() == 'clk')
|
||||
yield (
|
||||
(tile, site_name, pin_name, 'is_part_of_bus'),
|
||||
int(pin_is_part_of_bus))
|
||||
|
||||
# site clock pins are always named 'CLK'
|
||||
pin_loc += 3
|
||||
|
||||
return merged_dict(inner())
|
||||
|
||||
|
||||
def main():
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
-e third_party/fasm
|
||||
-e third_party/python-sdf-timing
|
||||
intervaltree
|
||||
junit-xml
|
||||
numpy
|
||||
|
|
|
|||
Loading…
Reference in New Issue