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run make format 

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi 2019-10-24 17:45:04 +02:00
parent 04234ec75c
commit 8914753211
1 changed files with 1 additions and 2 deletions
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3
fuzzers/036-iob-ologic/generate.py
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@ -23,8 +23,7 @@ def handle_data_width(segmk, d):
for opt in [2, 3, 4, 5, 6, 7, 8]:
segmk.add_site_tag(
site, 'OSERDES.DATA_WIDTH.W{}'.format(opt),
d['DATA_WIDTH'] == opt)
site, 'OSERDES.DATA_WIDTH.W{}'.format(opt), d['DATA_WIDTH'] == opt)
if verilog.unquote(d['DATA_RATE_OQ']) == 'DDR':
# DDR + WIDTH 6/8 have some overlapping bits, create a feature.