FUZZER - DSP - Fixes Following Review

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
This commit is contained in:
Jake Mercer 2019-10-31 23:18:38 +00:00
parent 15cfb5bd46
commit 6a3db24da1
1 changed files with 1 additions and 9 deletions

View File

@ -6,16 +6,8 @@ from prjxray.verilog import quote
import json
def bits_in(value, width):
bits = []
for i in range(width):
bits.append(value & 1)
value >>= 1
return bits
def add(segmk, site, dsp, tag, bit, value, invert):
tag = dsp + '.' + '%s' % ('Z' if invert else '') + tag + '[%u]' % bit
tag = "%s.%s%s[%u]" % (dsp, ('Z' if invert else ''), tag, bit)
value = (~value if invert else value)
value >>= bit
return segmk.add_site_tag(site, tag, value & 1)