mirror of https://github.com/openXC7/prjxray.git
Reworked the PS7 port def. extractor so instead of a minitest its now a fuzzer.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc
parent
568b20252f
commit
45338f1af4
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@ -0,0 +1,30 @@
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N := 1
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SPECIMENS := $(addprefix build/specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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database: $(SPECIMENS_OK)
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pushdb: build/ps7_ports.json
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mkdir -p ${XRAY_FAMILY_DIR}
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cp build/ps7*.json ${XRAY_FAMILY_DIR}/
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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build/ps7_pins.csv: $(SPECIMENS_OK)
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cp build/specimen_001/ps7_pins.csv build/
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build/ps7_ports.json: build/ps7_pins.csv
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python3 make_ports.py $< $@
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run:
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$(MAKE) clean
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$(MAKE) database
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$(MAKE) pushdb
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touch run.ok
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clean:
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rm -rf build run.ok
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.PHONY: database pushdb run clean
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@ -0,0 +1,3 @@
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# PS7 verilog cell definition extractor
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Extracts all pins of the PS7 bel from Vivado, groups them into ports, writes them to a JSON file.
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@ -0,0 +1,6 @@
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#!/bin/bash -x
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source ${XRAY_GENHEADER}
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${XRAY_VIVADO} -mode batch -source $FUZDIR/generate.tcl
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@ -1,8 +1,8 @@
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create_project -force -in_memory -name design -part xc7z020clg400-1
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create_project -force -name design -part $::env(XRAY_PART)
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set_property design_mode PinPlanning [current_fileset]
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open_io_design -name io_1
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set fp [open ps7.csv w]
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set fp [open ps7_pins.csv w]
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puts $fp "name,is_input,is_output,is_bidir"
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set pins [get_bel_pins -of_objects [get_bels -of_objects [get_sites PS7* -of_objects [get_tiles PSS*]]]]
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@ -0,0 +1,131 @@
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#!/usr/bin/env python3
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"""
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This script loads the PS7 pin dump from Vivado and groups pins into ports. Also
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assigns each port a class that indicates its function. The classes are:
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- "normal": A port that connects to the PL (FPGA)
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- "test": A port used for testing, not accessible from the PL.
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- "debug": A debug port, not accessible.
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- "mio": The "mio" ports go directly to die pads, not relevant for routing.
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Ports are then written to a JSON file.
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"""
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import argparse
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import csv
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import json
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import re
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from collections import defaultdict
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# =============================================================================
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def main():
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BUS_REGEX = re.compile("(.*[A-Z_])([0-9]+)$")
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# Parse arguments
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parser = argparse.ArgumentParser(
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description=__doc__,
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formatter_class=argparse.RawDescriptionHelpFormatter)
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parser.add_argument("csv", type=str, help="PS7 pin dump file")
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parser.add_argument(
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"json",
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type=str,
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help="Output JSON file with PS7 pins grouped into ports")
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args = parser.parse_args()
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# Load pin dump
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with open(args.csv, "r") as fp:
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pin_dump = list(csv.DictReader(fp))
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# Group pins into ports
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ports = defaultdict(lambda :{
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"direction": None,
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"min": None,
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"max": None,
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"width": 0
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})
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for pin in list(pin_dump):
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# Get port name and signal index
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match = BUS_REGEX.match(pin["name"])
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if match:
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name = match.group(1)
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idx = int(match.group(2))
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else:
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name = pin["name"]
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idx = 0
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# Get direction
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is_input = int(pin["is_input"])
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is_output = int(pin["is_output"])
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is_bidir = int(pin["is_bidir"])
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if is_input and not is_output and not is_bidir:
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direction = "input"
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elif not is_input and is_output and not is_bidir:
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direction = "output"
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elif not is_input and not is_output and is_bidir:
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direction = "inout"
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else:
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assert False, pin
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# Add to port
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port = ports[name]
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if port["direction"] is None:
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port["direction"] = direction
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else:
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assert port["direction"] == direction
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if port["min"] is None:
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port["min"] = idx
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else:
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port["min"] = min(port["min"], idx)
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if port["max"] is None:
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port["max"] = idx
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else:
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port["max"] = max(port["max"], idx)
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port["width"] = port["max"] - port["min"] + 1
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# Sort ports by their purpose
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for name, port in ports.items():
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# A test pin (unconnected)
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if name.startswith("TEST"):
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cls = "test"
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# A debug pin (unconnected)
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elif name.startswith("DEBUG"):
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cls = "debug"
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# A MIO/DDR pin.
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elif name.startswith("MIO") or name.startswith("DDR") and \
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name != "DDRARB":
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cls = "mio"
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# PS7 clock/reset
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elif name in ["PSCLK", "PSPORB", "PSSRSTB"]:
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cls = "mio"
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# "Normal" pin
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else:
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cls = "normal"
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port["class"] = cls
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# Write pin ports to a JSON file
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with open(args.json, "w") as fp:
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json.dump(ports, fp, indent=1, sort_keys=True)
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# =============================================================================
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if __name__ == "__main__":
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main()
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@ -120,6 +120,9 @@ $(eval $(call fuzzer,072-ordered_wires,))
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$(eval $(call fuzzer,073-get_counts,))
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$(eval $(call fuzzer,074-dump_all,005-tilegrid 072-ordered_wires))
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$(eval $(call fuzzer,075-pins,))
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ifeq ($(XRAY_DATABASE),zynq7)
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$(eval $(call fuzzer,076-ps7,))
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endif
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endif
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endif
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$(eval $(call fuzzer,100-dsp-mskpat,005-tilegrid))
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@ -1,20 +0,0 @@
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.PHONY: all clean
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all: xtra.ok
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clean:
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rm -rf xtra.ok
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rm -rf ps7_sim.v
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rm -rf ps7_map.v
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rm -rf ps7_pins.json
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rm -rf ps7.csv
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rm -rf *.xml
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rm -rf *.log
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rm -rf .Xil
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ps7.csv: dump_ps7.tcl
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$(XRAY_VIVADO) -mode batch -source dump_ps7.tcl -nojournal -log $(basename $@).log
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xtra.ok: ps7.csv make_cell.py
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python3 make_cell.py $<
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touch xtra.ok
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@ -1,3 +0,0 @@
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# PS7 verilog cell definition extractor
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Extracts all pins of the PS7 bel from Vivado, groups them into buses, removes those that are not connected (TEST*, DEBUG*) and creates the VPR counterpart for it. It also generates model XML, pb_type XML and techmap which handles unconnected ports correctly.
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@ -1,319 +0,0 @@
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#!/usr/bin/env python3
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import argparse
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import csv
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import json
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import re
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from collections import defaultdict
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# =============================================================================
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def main():
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BUS_REGEX = re.compile("(.*[A-Z_])([0-9]+)$")
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# Parse arguments
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parser = argparse.ArgumentParser()
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parser.add_argument("csv", type=str, help="PS7 pin dump file")
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args = parser.parse_args()
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# Load pin dump
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with open(args.csv, "r") as fp:
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pin_dump = list(csv.DictReader(fp))
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# Group pins into buses
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buses = defaultdict(lambda :{
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"direction": None,
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"min": None,
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"max": None,
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"width": 0
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})
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for pin in list(pin_dump):
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# Get bus name and signal index
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match = BUS_REGEX.match(pin["name"])
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if match:
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name = match.group(1)
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idx = int(match.group(2))
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else:
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name = pin["name"]
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idx = 0
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# Get direction
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is_input = int(pin["is_input"])
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is_output = int(pin["is_output"])
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is_bidir = int(pin["is_bidir"])
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if is_input and not is_output and not is_bidir:
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direction = "input"
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elif not is_input and is_output and not is_bidir:
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direction = "output"
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elif not is_input and not is_output and is_bidir:
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direction = "inout"
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else:
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assert False, pin
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# Add to bus
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bus = buses[name]
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if bus["direction"] is None:
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bus["direction"] = direction
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else:
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assert bus["direction"] == direction
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if bus["min"] is None:
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bus["min"] = idx
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else:
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bus["min"] = min(bus["min"], idx)
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if bus["max"] is None:
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bus["max"] = idx
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else:
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bus["max"] = max(bus["max"], idx)
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bus["width"] = bus["max"] - bus["min"] + 1
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# Sort buses by their purpose
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for name, bus in buses.items():
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# A test pin (unconnected)
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if name.startswith("TEST"):
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cls = "test"
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# A debug pin (unconnected)
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elif name.startswith("DEBUG"):
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cls = "debug"
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# A MIO/DDR pin.
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elif name.startswith("MIO") or name.startswith("DDR") and \
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name != "DDRARB":
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cls = "mio"
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# PS7 clock/reset
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elif name in ["PSCLK", "PSPORB", "PSSRSTB"]:
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cls = "mio"
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# "Normal" pin
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else:
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cls = "normal"
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bus["class"] = cls
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# .....................................................
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# Generate JSON with PS7 pins grouped by direction
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ps7_pins = {"input": [], "output": [], "inout": []}
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for name in sorted(buses.keys()):
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bus = buses[name]
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# Skip not relevant pins
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if bus["class"] not in ["normal", "mio"]:
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continue
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if bus["width"] > 1:
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for i in range(bus["min"], bus["max"]+1):
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pin_name = "{}{}".format(name, i)
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ps7_pins[bus["direction"]].append(pin_name)
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else:
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ps7_pins[bus["direction"]].append(name)
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with open("ps7_pins.json", "w") as fp:
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json.dump(ps7_pins, fp, sort_keys=True, indent=2)
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# .....................................................
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# Generate XML model
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pb_name = "PS7"
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blif_model = "PS7_VPR"
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model_xml = """<models>
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<model name="{}">
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""".format(blif_model)
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# Inputs
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model_xml += """ <input_ports>
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"""
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for name in sorted(buses.keys()):
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bus = buses[name]
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# Skip not relevant pins
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if bus["class"] not in ["normal"]:
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continue
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if bus["direction"] != "input":
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continue
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model_xml += " <port name=\"{}\"/>\n".format(name)
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# Outputs
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model_xml += """ </input_ports>
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<output_ports>
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"""
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for name in sorted(buses.keys()):
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bus = buses[name]
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# Skip not relevant pins
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if bus["class"] not in ["normal"]:
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continue
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if bus["direction"] != "output":
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continue
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model_xml += " <port name=\"{}\"/>\n".format(name)
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model_xml += """ </output_ports>
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"""
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model_xml += """ </model>
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</models>"""
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with open("ps7.model.xml", "w") as fp:
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fp.write(model_xml)
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# .....................................................
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# Generate XML pb_type
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pb_xml = """<pb_type name="{}" blif_model=".subckt {}" num_pb="1">
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""".format(pb_name, blif_model)
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for name in sorted(buses.keys()):
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bus = buses[name]
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# Skip not relevant pins
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if bus["class"] not in ["normal"]:
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continue
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pb_xml += " <{} name=\"{}\" num_pins=\"{}\"/>\n".format(
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bus["direction"].ljust(6), name, bus["width"])
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pb_xml += """</pb_type>
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"""
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with open("ps7.pb_type.xml", "w") as fp:
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fp.write(pb_xml)
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# .....................................................
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# Prepare Verilog module definition for the PS7_VPR
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port_defs = []
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for name in sorted(buses.keys()):
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bus = buses[name]
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# Skip not relevant pins (eg. MIO and DDR)
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if bus["class"] not in ["normal"]:
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continue
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# Generate port definition
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if bus["width"] > 1:
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port_str = " {} [{:>2d}:{:>2d}] {}".format(
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bus["direction"].ljust(6), bus["max"], bus["min"], name)
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else:
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port_str = " {} {}".format(
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bus["direction"].ljust(6), name)
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port_defs.append(port_str)
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verilog = """(* blackbox *)
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module PS7_VPR (
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{}
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);
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endmodule
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""".format(",\n".join(port_defs))
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with open("ps7_sim.v", "w") as fp:
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fp.write(verilog)
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# .....................................................
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# Prepare techmap that maps PS7 to PS7_VPR and handles
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# unconnected inputs (ties them to GND)
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port_defs = []
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port_conns = []
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param_defs = []
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wire_defs = []
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for name in sorted(buses.keys()):
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bus = buses[name]
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# Skip not relevant pins
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if bus["class"] not in ["normal", "mio"]:
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continue
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# Generate port definition
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if bus["width"] > 1:
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port_str = " {} [{:>2d}:{:>2d}] {}".format(
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bus["direction"].ljust(6), bus["max"], bus["min"], name)
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else:
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port_str = " {} {}".format(
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bus["direction"].ljust(6), name)
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port_defs.append(port_str)
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# MIO and DDR pins are not mapped as they are dummy
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if bus["class"] == "mio":
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continue
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# This is an input port, needs to be tied to GND if unconnected
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if bus["direction"] == "input":
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# Techmap parameter definition
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param_defs.append(
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" parameter _TECHMAP_CONSTMSK_{}_ = 0;".format(name.upper()))
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param_defs.append(
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" parameter _TECHMAP_CONSTVAL_{}_ = 0;".format(name.upper()))
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# Wire definition using generate statement. Necessary for detection
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# of unconnected ports.
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wire_defs.append(
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"""
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generate if((_TECHMAP_CONSTMSK_{name_upr}_ == {N}'d0) && (_TECHMAP_CONSTVAL_{name_upr}_ == {N}'d0))
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wire [{M}:0] {name_lwr} = {N}'d0;
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else
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wire [{M}:0] {name_lwr} = {name};
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endgenerate""".format(
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name=name,
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name_upr=name.upper(),
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name_lwr=name.lower(),
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N=bus["width"],
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M=bus["width"] - 1))
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# Connection to the "generated" wire.
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port_conns.append(
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" .{name:<25}({name_lwr})".format(
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name=name, name_lwr=name.lower()))
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# An output port
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else:
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# Direct connection
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port_conns.append(" .{name:<25}({name})".format(name=name))
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# Format the final verilog.
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verilog = """module PS7 (
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{port_defs}
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);
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// Techmap specific parameters.
|
||||
{param_defs}
|
||||
|
||||
// Detect all unconnected inputs and tie them to 0.
|
||||
{wire_defs}
|
||||
|
||||
// Replacement cell.
|
||||
PS7_VPR _TECHMAP_REPLACE_ (
|
||||
{port_conns}
|
||||
);
|
||||
|
||||
endmodule
|
||||
""".format(
|
||||
port_defs=",\n".join(port_defs),
|
||||
param_defs="\n".join(param_defs),
|
||||
wire_defs="\n".join(wire_defs),
|
||||
port_conns=",\n".join(port_conns))
|
||||
|
||||
with open("ps7_map.v", "w") as fp:
|
||||
fp.write(verilog)
|
||||
|
||||
|
||||
# =============================================================================
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
Loading…
Reference in New Issue