Update to 0.7 release.

and bump the vpithunk magic number.

.cvsignore

@@ -2,16 +2,23 @@ lexor_keyword.cc
 parse.h
 parse.cc
 parse.cc.output
+parse.output
 syn-rules.cc
 syn-rules.cc.output
+syn-rules.output
 lexor.cc
+iverilog-vpi
+iverilog-vpi.pdf
+iverilog-vpi.ps
 ivl
+ivl.exp
 dep
 configure
 Makefile
-verilog
-gverilog
-iverilog
+check
+check.cc
 config.status
 config.log
 config.cache
+config.h
+dosify

Attrib.cc

@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2000 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: Attrib.cc,v 1.5 2002/08/12 01:34:58 steve Exp $"
+#endif
+
+# include "config.h"
+
+# include  "Attrib.h"
+# include  <assert.h>
+
+Attrib::Attrib()
+{
+      nlist_ = 0;
+      list_ = 0;
+}
+
+Attrib::~Attrib()
+{
+      delete[] list_;
+}
+
+#if 0
+void Attrib::copy_attributes(const map<string,verinum>&attr)
+{
+      assert(list_ == 0);
+
+      nlist_ = attr.size();
+      list_ = new cell_[nlist_];
+
+      map<string,verinum>::const_iterator idx;
+      unsigned jdx;
+      for (idx = attr.begin(), jdx = 0 ;  idx != attr.end() ;  idx ++, jdx++) {
+	    struct cell_*tmp = list_ + jdx;
+	    tmp->key = (*idx).first;
+	    tmp->val = (*idx).second;
+      }
+}
+#endif
+
+const verinum& Attrib::attribute(const string&key) const
+{
+      for (unsigned idx = 0 ;  idx < nlist_ ;  idx += 1) {
+
+	    if (key == list_[idx].key)
+		  return list_[idx].val;
+      }
+
+      static const verinum null;
+      return null;
+}
+
+void Attrib::attribute(const string&key, const verinum&value)
+{
+      unsigned idx;
+
+      for (idx = 0 ; idx < nlist_ ;  idx += 1) {
+	    if (key == list_[idx].key) {
+		  list_[idx].val = value;
+		  return;
+	    }
+      }
+
+      struct cell_*tmp = new struct cell_[nlist_+1];
+      for (idx = 0 ;  idx < nlist_ ;  idx += 1)
+	    tmp[idx] = list_[idx];
+
+      tmp[nlist_].key = key;
+      tmp[nlist_].val = value;
+
+      nlist_ += 1;
+      delete[]list_;
+      list_ = tmp;
+}
+
+bool Attrib::has_compat_attributes(const Attrib&that) const
+{
+      unsigned idx;
+
+      for (idx = 0 ;  idx < that.nlist_ ;  idx += 1) {
+
+	    verinum tmp = attribute(that.list_[idx].key);
+	    if (tmp != that.list_[idx].val)
+		  return false;
+      }
+
+      return true;
+}
+
+unsigned Attrib::attr_cnt() const
+{
+      return nlist_;
+}
+
+const char* Attrib::attr_key(unsigned idx) const
+{
+      assert(idx < nlist_);
+      return list_[idx].key.c_str();
+}
+
+const verinum& Attrib::attr_value(unsigned idx) const
+{
+      assert(idx < nlist_);
+      return list_[idx].val;
+}
+
+
+/*
+ * $Log: Attrib.cc,v $
+ * Revision 1.5  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.4  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
+ * Revision 1.3  2002/05/23 03:08:50  steve
+ *  Add language support for Verilog-2001 attribute
+ *  syntax. Hook this support into existing $attribute
+ *  handling, and add number and void value types.
+ *
+ *  Add to the ivl_target API new functions for access
+ *  of complex attributes attached to gates.
+ *
+ * Revision 1.2  2001/07/25 03:10:48  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
+ * Revision 1.1  2000/12/04 17:37:03  steve
+ *  Add Attrib class for holding NetObj attributes.
+ *
+ */
+

Attrib.h

@@ -0,0 +1,87 @@
+#ifndef __Attrib_H
+#define __Attrib_H
+/*
+ * Copyright (c) 2000 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: Attrib.h,v 1.4 2002/08/12 01:34:58 steve Exp $"
+#endif
+
+# include  <string>
+# include  "verinum.h"
+
+/*
+ * This class keeps a map of key/value pairs. The map can be set from
+ * an STL map, or by setting individual mappings.
+ */
+class Attrib {
+
+    public:
+      Attrib();
+      ~Attrib();
+
+      const verinum&attribute(const string&key) const;
+      void attribute(const string&key, const verinum&value);
+      bool has_compat_attributes(const Attrib&that) const;
+
+
+	/* Provide a means of iterating over the entries in the map. */
+      unsigned       attr_cnt() const;
+      const char*    attr_key(unsigned idx) const;
+      const verinum& attr_value(unsigned idx) const;
+
+
+    private:
+      struct cell_ {
+	    string  key;
+	    verinum val;
+      };
+
+      unsigned nlist_;
+      struct cell_*list_;
+
+    private: // not implemented
+      Attrib(const Attrib&);
+      Attrib& operator= (const Attrib&);
+};
+
+/*
+ * $Log: Attrib.h,v $
+ * Revision 1.4  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.3  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
+ * Revision 1.2  2002/05/23 03:08:50  steve
+ *  Add language support for Verilog-2001 attribute
+ *  syntax. Hook this support into existing $attribute
+ *  handling, and add number and void value types.
+ *
+ *  Add to the ivl_target API new functions for access
+ *  of complex attributes attached to gates.
+ *
+ * Revision 1.1  2000/12/04 17:37:03  steve
+ *  Add Attrib class for holding NetObj attributes.
+ *
+ */
+#endif

HName.cc

@@ -0,0 +1,279 @@
+/*
+ * Copyright (c) 2001 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: HName.cc,v 1.5 2002/11/02 03:27:52 steve Exp $"
+#endif
+
+# include  "config.h"
+# include  "HName.h"
+# include  <iostream>
+# include  <string.h>
+# include  <stdlib.h>
+#ifdef HAVE_MALLOC_H
+# include  <malloc.h>
+#endif
+
+hname_t::hname_t()
+{
+      item_ = 0;
+      count_ = 0;
+}
+
+hname_t::hname_t(const char*text)
+{
+      item_ = strdup(text);
+      count_ = 1;
+}
+
+hname_t::hname_t(const hname_t&that)
+{
+      count_ = that.count_;
+      switch (count_) {
+	  case 0:
+	    item_ = 0;
+	    break;
+	  case 1:
+	    item_ = strdup(that.item_);
+	    break;
+	  default:
+	    array_ = new char*[count_];
+	    for (unsigned idx = 0 ;  idx < count_ ;  idx += 1)
+		  array_[idx] = strdup(that.array_[idx]);
+	    break;
+      }
+}
+
+hname_t::~hname_t()
+{
+      switch (count_) {
+	  case 0:
+	    break;
+	  case 1:
+	    free(item_);
+	    break;
+	  default:
+	    for (unsigned idx = 0 ;  idx < count_ ;  idx += 1)
+		  free(array_[idx]);
+	    delete[]array_;
+	    break;
+      }
+}
+
+unsigned hname_t::component_count() const
+{
+      return count_;
+}
+
+void hname_t::append(const char*text)
+{
+      char**tmp;
+
+      switch (count_) {
+	  case 0:
+	    count_ = 1;
+	    item_ = strdup(text);
+	    break;
+	  case 1:
+	    count_ = 2;
+	    tmp = new char*[2];
+	    tmp[0] = item_;
+	    tmp[1] = strdup(text);
+	    array_ = tmp;
+	    break;
+	  default:
+	    tmp = new char*[count_+1];
+	    for (unsigned idx = 0 ;  idx < count_ ;  idx += 1)
+		  tmp[idx] = array_[idx];
+	    delete[]array_;
+	    array_ = tmp;
+	    array_[count_] = strdup(text);
+	    count_ += 1;
+      }
+}
+
+void hname_t::prepend(const char*text)
+{
+      char**tmp;
+
+      switch (count_) {
+	  case 0:
+	    count_ = 1;
+	    item_ = strdup(text);
+	    break;
+	  case 1:
+	    count_ = 2;
+	    tmp = new char*[2];
+	    tmp[0] = strdup(text);
+	    tmp[1] = item_;
+	    array_ = tmp;
+	    break;
+	  default:
+	    tmp = new char*[count_+1];
+	    tmp[0] = strdup(text);
+	    for (unsigned idx = 0 ;  idx < count_ ;  idx += 1)
+		  tmp[idx+1] = array_[idx];
+	    delete[]array_;
+	    array_ = tmp;
+	    count_ += 1;
+      }
+}
+
+char* hname_t::remove_tail_name()
+{
+      if (count_ == 0)
+	    return 0;
+
+      if (count_ == 1) {
+	    char*tmp = item_;
+	    count_ = 0;
+	    item_ = 0;
+	    return tmp;
+      }
+
+      if (count_ == 2) {
+	    char*tmp1 = array_[0];
+	    char*tmp2 = array_[1];
+	    delete[]array_;
+	    count_ = 1;
+	    item_ = tmp1;
+	    return tmp2;
+      }
+
+      char*tmpo = array_[count_-1];
+      char**tmpa = new char*[count_-1];
+      for (unsigned idx = 0 ;  idx < count_-1 ;  idx += 1)
+	    tmpa[idx] = array_[idx];
+
+      delete[]array_;
+      array_ = tmpa;
+      count_ -= 1;
+      return tmpo;
+}
+
+const char* hname_t::peek_name(unsigned idx) const
+{
+      if (idx >= count_)
+	    return 0;
+
+      if (count_ == 1)
+	    return item_;
+
+      return array_[idx];
+}
+
+const char* hname_t::peek_tail_name() const
+{
+      switch (count_) {
+	  case 0:
+	    return 0;
+	  case 1:
+	    return item_;
+	  default:
+	    return array_[count_-1];
+      }
+}
+
+bool operator < (const hname_t&l, const hname_t&r)
+{
+      unsigned idx = 0;
+      const char*lc = l.peek_name(idx);
+      const char*rc = r.peek_name(idx);
+
+      while (lc && rc) {
+	    int cmp = strcmp(lc, rc);
+	    if (cmp < 0)
+		  return true;
+	    if (cmp > 0)
+		  return false;
+	    idx += 1;
+	    lc = l.peek_name(idx);
+	    rc = r.peek_name(idx);
+      }
+
+      if (lc && !rc)
+	    return false;
+      if (rc && !lc)
+	    return true;
+
+	// Must be ==
+      return false;
+}
+
+bool operator == (const hname_t&l, const hname_t&r)
+{
+      unsigned idx = 0;
+      const char*lc = l.peek_name(idx);
+      const char*rc = r.peek_name(idx);
+
+      while (lc && rc) {
+	    int cmp = strcmp(lc, rc);
+	    if (cmp != 0)
+		  return false;
+	    idx += 1;
+	    lc = l.peek_name(idx);
+	    rc = r.peek_name(idx);
+      }
+
+      if (lc || rc)
+	    return false;
+
+	// Must be ==
+      return true;
+}
+
+ostream& operator<< (ostream&out, const hname_t&that)
+{
+      switch (that.count_) {
+	  case 0:
+	    out << "";
+	    return out;
+	  case 1:
+	    out << that.item_;
+	    return out;
+
+	  default:
+	    out << that.array_[0];
+	    for (unsigned idx = 1 ;  idx < that.count_ ;  idx += 1)
+		  out << "." << that.array_[idx];
+
+	    return out;
+      }
+}
+
+/*
+ * $Log: HName.cc,v $
+ * Revision 1.5  2002/11/02 03:27:52  steve
+ *  Allow named events to be referenced by
+ *  hierarchical names.
+ *
+ * Revision 1.4  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.3  2002/01/05 04:36:06  steve
+ *  include malloc.h only when available.
+ *
+ * Revision 1.2  2001/12/18 04:52:45  steve
+ *  Include config.h for namespace declaration.
+ *
+ * Revision 1.1  2001/12/03 04:47:14  steve
+ *  Parser and pform use hierarchical names as hname_t
+ *  objects instead of encoded strings.
+ *
+ */
+

HName.h

@@ -0,0 +1,101 @@
+#ifndef __HName_H
+#define __HName_H
+/*
+ * Copyright (c) 2001 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: HName.h,v 1.4 2002/11/02 03:27:51 steve Exp $"
+#endif
+
+# include  <iostream>
+#ifdef __GNUC__
+#if __GNUC__ > 2
+using namespace std;
+#endif
+#endif
+
+/*
+ * This class represents a Verilog hierarchical name. A hierarchical
+ * name is an ordered list of simple names.
+ */
+
+class hname_t {
+
+    public:
+      hname_t ();
+      explicit hname_t (const char*text);
+      hname_t (const hname_t&that);
+      ~hname_t();
+
+	// This method adds a name to the end of the hierarchical
+	// path. This becomes a new base name.
+      void append(const char*text);
+
+	// This method adds a name to the *front* of the hierarchical
+	// path. The base name remains the same, unless this is the
+	// only component.
+      void prepend(const char*text);
+
+	// This method removes the tail name from the hierarchy, and
+	// returns a pointer to that tail name. That tail name now
+	// must be removed by the caller.
+      char* remove_tail_name();
+
+	// Return the given component in the hierarchical name. If the
+	// idx is too large, return 0.
+      const char*peek_name(unsigned idx) const;
+      const char*peek_tail_name() const;
+
+	// Return the number of components in the hierarchical
+	// name. If this is a simple name, this will return 1.
+      unsigned component_count() const;
+
+      friend ostream& operator<< (ostream&, const hname_t&);
+
+    private:
+      union {
+	    char**array_;
+	    char* item_;
+      };
+      unsigned count_;
+
+    private: // not implemented
+      hname_t& operator= (const hname_t&);
+};
+
+extern bool operator <  (const hname_t&, const hname_t&);
+extern bool operator == (const hname_t&, const hname_t&);
+
+/*
+ * $Log: HName.h,v $
+ * Revision 1.4  2002/11/02 03:27:51  steve
+ *  Allow named events to be referenced by
+ *  hierarchical names.
+ *
+ * Revision 1.3  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.2  2002/06/14 03:25:51  steve
+ *  Compiler portability.
+ *
+ * Revision 1.1  2001/12/03 04:47:14  steve
+ *  Parser and pform use hierarchical names as hname_t
+ *  objects instead of encoded strings.
+ *
+ */
+#endif

LineInfo.cc

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2000 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: LineInfo.cc,v 1.3 2002/08/12 01:34:58 steve Exp $"
+#endif
+
+# include "config.h"
+
+# include  "LineInfo.h"
+# include  <cstdio>
+
+LineInfo::~LineInfo()
+{
+}
+
+string LineInfo::get_line() const
+{
+      char buf[8];
+      sprintf(buf, "%u", lineno_);
+      return string(file_? file_ : "") + ":" + buf;
+}
+
+void LineInfo::set_line(const LineInfo&that)
+{
+      file_ = that.file_;
+      lineno_ = that.lineno_;
+}
+
+/*
+ * $Log: LineInfo.cc,v $
+ * Revision 1.3  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.2  2001/07/25 03:10:48  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
+ * Revision 1.1  2000/11/30 17:31:42  steve
+ *  Change LineInfo to store const C strings.
+ *
+ */
+

LineInfo.h

@@ -18,62 +18,50 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: LineInfo.h,v 1.4 2000/02/23 02:56:53 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: LineInfo.h,v 1.6 2002/08/12 01:34:58 steve Exp $"
 #endif
 
-# include  <cstdio>
 # include  <string>
 
+/*
+ * This class holds line information for an internal object.
+ *
+ * Note that the file names are C-style strings that are allocated by
+ * the lexor (which parses the line directives) and are never
+ * deallocated. We can therefore safely store the pointer and never
+ * delete the string, even if LineInfo objects are destroyed.
+ */
+
 class LineInfo {
     public:
-      LineInfo() : lineno_(0) { }
+      LineInfo() : file_(0), lineno_(0) { }
+      ~LineInfo();
 
-      string get_line() const
-	    { char buf[8];
-	      sprintf(buf, "%u", lineno_);
-	      return file_ + ":" + buf;
-	    }
+      string get_line() const;
 
-      void set_line(const LineInfo&that)
-	    { file_ = that.file_;
-	      lineno_ = that.lineno_;
-	    }
+      void set_line(const LineInfo&that);
 
-      void set_file(const string&f) { file_ = f; }
+      void set_file(const char*f) { file_ = f; }
       void set_lineno(unsigned n) { lineno_ = n; }
 
     private:
-      string file_;
+      const char* file_;
       unsigned lineno_;
 };
 
 /*
  * $Log: LineInfo.h,v $
+ * Revision 1.6  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.5  2000/11/30 17:31:42  steve
+ *  Change LineInfo to store const C strings.
+ *
  * Revision 1.4  2000/02/23 02:56:53  steve
  *  Macintosh compilers do not support ident.
  *
  * Revision 1.3  1999/02/15 02:06:15  steve
  *  Elaborate gate ranges.
- *
- * Revision 1.2  1999/02/01 00:26:48  steve
- *  Carry some line info to the netlist,
- *  Dump line numbers for processes.
- *  Elaborate prints errors about port vector
- *  width mismatch
- *  Emit better handles null statements.
- *
- * Revision 1.1  1999/01/25 05:45:56  steve
- *  Add the LineInfo class to carry the source file
- *  location of things. PGate, Statement and PProcess.
- *
- *  elaborate handles module parameter mismatches,
- *  missing or incorrect lvalues for procedural
- *  assignment, and errors are propogated to the
- *  top of the elaboration call tree.
- *
- *  Attach line numbers to processes, gates and
- *  assignment statements.
- *
  */
 #endif

Makefile.in

@@ -3,9 +3,7 @@
 #    and/or modify it in source code form under the terms of the GNU
 #    Library General Public License as published by the Free Software
 #    Foundation; either version 2 of the License, or (at your option)
-#    any later version. In order to redistribute the software in
-#    binary form, you will need a Picture Elements Binary Software
-#    License.
+#    any later version.
 #
 #    This program is distributed in the hope that it will be useful,
 #    but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -18,23 +16,33 @@
 #    59 Temple Place - Suite 330
 #    Boston, MA 02111-1307, USA
 #
-#ident "$Id: Makefile.in,v 1.57 2000/06/16 18:59:49 steve Exp $"
+#ident "$Id: Makefile.in,v 1.140 2002/12/10 05:45:44 steve Exp $"
 #
 #
 SHELL = /bin/sh
 
-VERSION = 0.3PRE
+# This version string is only used in the version message printed
+# by the compiler. It reflects the assigned version number for the
+# product as a whole. Most components also print the CVS Name: token
+# in order to get a more automatic version stamp as well.
+VERSION = 0.7
 
 prefix = @prefix@
 exec_prefix = @exec_prefix@
 srcdir = @srcdir@
 
+SUBDIRS = @subdirs@
+
 VPATH = $(srcdir)
 
-bindir = $(exec_prefix)/bin
-libdir = $(exec_prefix)/lib
-mandir = @mandir@
+bindir = @bindir@
+libdir = @libdir@
 includedir = $(prefix)/include
+mandir = @mandir@
+
+dllib=@DLLIB@
+rdynamic=@rdynamic@
+strip_dynamic=@strip_dynamic@
 
 CC = @CC@
 CXX = @CXX@
@@ -43,123 +51,264 @@ INSTALL_SCRIPT = @INSTALL_SCRIPT@
 INSTALL_PROGRAM = @INSTALL_PROGRAM@
 INSTALL_DATA = @INSTALL_DATA@
 STRIP = @STRIP@
+LEX = @LEX@
+YACC = @YACC@
 
 CPPFLAGS = @CPPFLAGS@ @DEFS@
-CXXFLAGS = @CXXFLAGS@ -I$(srcdir)
+CXXFLAGS = @CXXFLAGS@ -I. -I$(srcdir)
+PICFLAGS = @PICFLAG@
 LDFLAGS = @LDFLAGS@
 
-all: ivl verilog iverilog
+# The TARGETS variable lists the target modules that can be build and
+# installed. Some of them depend on external things, so are only
+# compiled if the prerequisites are installed.
+TARGETS = tgt-null
+ifeq ('@HAVE_IPAL@','yes')
+TARGETS += tgt-pal
+endif
+
+all: ivl@EXEEXT@ libvpi.a
+	for dir in $(SUBDIRS) ; do (cd $$dir ; $(MAKE) all); done
 	cd vpi ; $(MAKE) all
-	cd vvm ; $(MAKE) all
 	cd ivlpp ; $(MAKE) all
+	cd driver ; $(MAKE) VERSION=$(VERSION) all
+	cd tgt-verilog ; $(MAKE) all
+	cd tgt-stub ; $(MAKE) all
+	for tgt in $(TARGETS); do (cd $$tgt ; $(MAKE) all); done
+
+# In the windows world, the installer will need a dosify program to
+# dosify text files.
+ifeq (@WIN32@,yes)
+all: dosify.exe
+dosify.exe: dosify.c
+	$(CC) -o dosify.exe dosify.c
+
+ifeq (@MINGW32@,yes)
+SUBDIRS += driver-vpi
+endif
+
+else
+all: iverilog-vpi
+endif
+
+# This rule rules the compiler in the trivial hello.vl program to make
+# sure the basics were compiled properly.
+check: all
+	for dir in $(SUBDIRS); do (cd $$dir ; $(MAKE) check); done
+	driver/iverilog -Ccheck.conf -ocheck.vvp -tvvp-check -B./ivlpp $(srcdir)/examples/hello.vl
+	vvp/vvp -M./vpi ./check.vvp | grep 'Hello, World'
 
 clean:
-	rm -f *.o parse.cc parse.cc.output parse.h dep/*.d lexor.cc verilog
+	rm -f *.o parse.cc parse.cc.output parse.h dep/*.d lexor.cc lexor_keyword.cc ivl@EXEEXT@ libivl.a libvpi.a iverilog-vpi
 	cd vpi ; $(MAKE) clean
-	cd vvm ; $(MAKE) clean
+	cd driver ; $(MAKE) clean
 	cd ivlpp ; $(MAKE) clean
+	cd tgt-verilog ; $(MAKE) clean
+	cd tgt-stub ; $(MAKE) clean
+	for dir in $(SUBDIRS); do (cd $$dir ; $(MAKE) clean); done
+	for tgt in $(TARGETS); do (cd $$tgt ; $(MAKE) clean); done
 
 distclean: clean
+	for dir in $(SUBDIRS); do (cd $$dir ; $(MAKE) distclean); done
+	for tgt in $(TARGETS); do (cd $$tgt ; $(MAKE) distclean); done
 	rm -f vpi/Makefile
-	rm -f vvm/Makefile
 	rm -f ivlpp/Makefile
+	rm -f driver/Makefile
 	rm -f config.status config.cache config.log
 	rm -f Makefile
+	rm -f tgt-pal/Makefile tgt-stub/Makefile tgt-verilog/Makefile
 
-TT = t-null.o t-verilog.o t-vvm.o t-xnf.o
-FF = nodangle.o propinit.o synth.o syn-rules.o xnfio.o
+TT = t-dll.o t-dll-api.o t-dll-expr.o t-dll-proc.o t-xnf.o
+FF = cprop.o nodangle.o synth.o synth2.o syn-rules.o xnfio.o
 
-O = main.o cprop.o design_dump.o dup_expr.o elaborate.o elab_expr.o \
-elab_net.o elab_pexpr.o elab_scope.o elab_sig.o emit.o eval.o eval_tree.o \
-expr_synth.o functor.o lexor.o lexor_keyword.o link_const.o \
-mangle.o netlist.o \
-net_design.o net_event.o net_force.o net_scope.o net_udp.o nexus_from_link.o \
-pad_to_width.o \
+O = main.o async.o design_dump.o dup_expr.o elaborate.o elab_expr.o \
+elab_lval.o elab_net.o elab_anet.o elab_pexpr.o elab_scope.o \
+elab_sig.o emit.o eval.o eval_attrib.o eval_rconst.o \
+eval_tree.o expr_synth.o functor.o lexor.o lexor_keyword.o link_const.o \
+load_module.o netlist.o netmisc.o net_assign.o \
+net_design.o net_event.o net_expr.o net_force.o net_func.o \
+net_link.o net_modulo.o net_nex_input.o net_nex_output.o \
+net_proc.o net_scope.o net_udp.o pad_to_width.o \
 parse.o parse_misc.o pform.o pform_dump.o \
-set_width.o \
-verinum.o verireal.o target.o targets.o util.o Module.o PDelays.o PEvent.o \
+set_width.o sync.o \
+verinum.o verireal.o target.o targets.o \
+Attrib.o HName.o LineInfo.o Module.o PDelays.o PEvent.o \
 PExpr.o PGate.o \
-PTask.o PFunction.o PWire.o Statement.o \
+PTask.o PFunction.o PWire.o Statement.o StringHeap.o \
 $(FF) $(TT)
 
-Makefile: Makefile.in config.status
+Makefile: Makefile.in config.h.in config.status
 	./config.status
 
-# Make the actual verilog program from the script template. This
-# simply invloves editing the substitution strings in the script into
-# the configured copy.
-tmp1 = bindir
-tmp2 = libdir
-tmp3 = includedir
-tmp4 = CXX
-verilog: $(srcdir)/verilog.sh
-	sed -e 's;@$(tmp1)@;@bindir@;' \
-	    -e 's;@$(tmp2)@;@libdir@;' \
-	    -e 's;@$(tmp3)@;@includedir@;' \
-	    -e 's;@dllib@;@DLLIB@;' \
-	    -e 's;@$(tmp4)@;@CXX@;' < $< > $@
 
-ivl: $O
-	$(CXX) $(CXXFLAGS) -o ivl $O
+libvpi.a: vpithunk.o
+	rm -f $@
+	ar cvq $@ vpithunk.o
+	ranlib $@
 
-iverilog: iverilog.c
-	$(CC) $(CPPFLAGS) -o iverilog -DCXX='"@CXX@"' -DIVL_ROOT='"@libdir@/ivl"'  -DIVL_INC='"@includedir@"' -DIVL_LIB='"@libdir@"' -DDLLIB='"@DLLIB@"' iverilog.c
-
-%.o dep/%.d: %.cc
+# The vpithunk.c file (that makes up the libvpi.a library) needs to
+# be make with PIC flags, because shared objects load it.
+vpithunk.o: vpithunk.c
 	@[ -d dep ] || mkdir dep
-	$(CXX) $(CPPFLAGS) $(CXXFLAGS) -MD -c $< -o $*.o
+	$(CC) $(CPPFLAGS) $(CFLAGS) $(PICFLAGS) -MD -c $< -o $*.o
 	mv $*.d dep/$*.d
 
 
-lexor.o dep/lexor.d: lexor.cc parse.h
+ifeq (@WIN32@,yes)
+# Under Windows (mingw) I need to make the ivl.exe in two steps.
+# The first step makes an ivl.exe that dlltool can use to make an
+# export and import library, and the last link makes a, ivl.exe
+# that really exports the things that the import library imports.
+ivl@EXEEXT@: $O ivl.def
+	$(CXX) -o ivl@EXEEXT@ $O $(dllib) @EXTRALIBS@	
+	dlltool --dllname ivl@EXEEXT@ --def ivl.def \
+		--output-lib libivl.a --output-exp ivl.exp
+	$(CXX) -o ivl@EXEEXT@ ivl.exp $O $(dllib) @EXTRALIBS@	
+else
+ivl@EXEEXT@: $O
+	$(CXX) $(CXXFLAGS) $(rdynamic) $(LDFLAGS) -o ivl@EXEEXT@ $O $(dllib)
+endif
 
-parse.o dep/parse.d: parse.cc
+
+ifeq (@WIN32@,yes)
+
+else
+iverilog-vpi: iverilog-vpi.sh
+	sed -e 's;@SHARED@;@shared@;' -e 's;@PIC@;@PICFLAG@;' \
+	    -e 's;@INCLUDEDIR@;@includedir@;' -e 's;@LIBDIR@;@libdir@;' $< > $@
+	chmod +x $@
+endif
+
+%.o: %.cc
+	@[ -d dep ] || mkdir dep
+	$(CXX) @ident_support@ $(CPPFLAGS) $(CXXFLAGS) -MD -c $< -o $*.o
+	mv $*.d dep/$*.d
+
+
+lexor.o: lexor.cc parse.h
+
+parse.o: parse.cc
 
 parse.h parse.cc: $(srcdir)/parse.y
-	bison --verbose -t -p VL -d $(srcdir)/parse.y -o parse.cc
-	mv parse.cc.h parse.h
+	$(YACC) --verbose -t -p VL -d -o parse.cc $(srcdir)/parse.y
+	mv parse.cc.h parse.h || mv parse.hh parse.h
 
 syn-rules.cc: $(srcdir)/syn-rules.y
-	bison --verbose -p syn_ -o syn-rules.cc $(srcdir)/syn-rules.y
+	$(YACC) --verbose -p syn_ -o syn-rules.cc $(srcdir)/syn-rules.y
 
 lexor.cc: $(srcdir)/lexor.lex
-	flex -PVL -s -olexor.cc $(srcdir)/lexor.lex
+	$(LEX) -PVL -s -olexor.cc $(srcdir)/lexor.lex
 
-lexor_keyword.o dep/lexor_keyword.d: lexor_keyword.cc
+lexor_keyword.o: lexor_keyword.cc
 
 lexor_keyword.cc: lexor_keyword.gperf
-	gperf -o -i 7 -C -k 1-3,$$ -L ANSI-C -H keyword_hash -N check_identifier -t lexor_keyword.gperf > lexor_keyword.cc
+	gperf -o -i 7 -C -k 1-3,$$ -L ANSI-C -H keyword_hash -N check_identifier -t $(srcdir)/lexor_keyword.gperf > lexor_keyword.cc || (rm -f lexor_keyword.cc ; false)
 
+iverilog-vpi.ps: $(srcdir)/iverilog-vpi.man
+	man -t $(srcdir)/iverilog-vpi.man > iverilog-vpi.ps
 
-install: all installdirs $(bindir)/iverilog $(libdir)/ivl/ivl $(mandir)/man1/iverilog.1
+iverilog-vpi.pdf: iverilog-vpi.ps
+	ps2pdf iverilog-vpi.ps iverilog-vpi.pdf
+
+ifeq (@WIN32@,yes)
+INSTALL_DOC = $(prefix)/iverilog-vpi.pdf
+INSTALL_DOCDIR =
+all: iverilog-vpi.pdf
+else
+INSTALL_DOC = $(mandir)/man1/iverilog-vpi.1
+INSTALL_DOCDIR = $(mandir)/man1
+endif
+
+ifeq (@WIN32@,yes)
+WIN32_INSTALL = $(prefix)/hello.vl $(prefix)/sqrt.vl $(prefix)/sqrt-virtex.v $(prefix)/QUICK_START.txt
+else
+WIN32_INSTALL = $(bindir)/iverilog-vpi
+endif
+
+install: all installdirs $(libdir)/ivl/ivl@EXEEXT@ $(libdir)/ivl/iverilog.conf $(includedir)/ivl_target.h $(includedir)/vpi_user.h $(includedir)/acc_user.h $(includedir)/veriuser.h $(libdir)/libvpi.a $(WIN32_INSTALL) $(INSTALL_DOC)
 	cd vpi ; $(MAKE) install
-	cd vvm ; $(MAKE) install
 	cd ivlpp ; $(MAKE) install
+	cd driver ; $(MAKE) install
+	for tgt in $(SUBDIRS); do (cd $$tgt ; $(MAKE) install); done
+	for tgt in $(TARGETS); do (cd $$tgt ; $(MAKE) install); done
 
-$(bindir)/iverilog: ./iverilog
-	$(INSTALL_PROGRAM) ./iverilog $(bindir)/iverilog
-	$(STRIP) $(bindir)/iverilog
+$(bindir)/iverilog-vpi: ./iverilog-vpi
+	$(INSTALL_SCRIPT) ./iverilog-vpi $(bindir)/iverilog-vpi
 
-$(libdir)/ivl/ivl: ./ivl
-	$(INSTALL_PROGRAM) ./ivl $(libdir)/ivl/ivl
-	$(STRIP) $(libdir)/ivl/ivl
+$(libdir)/libvpi.a : ./libvpi.a
+	$(INSTALL_DATA) libvpi.a $(libdir)/libvpi.a
 
-$(mandir)/man1/iverilog.1: $(srcdir)/iverilog.man
-	$(INSTALL_DATA) $(srcdir)/iverilog.man $(mandir)/man1/iverilog.1
+$(libdir)/ivl/ivl@EXEEXT@: ./ivl@EXEEXT@
+	$(INSTALL_PROGRAM) ./ivl@EXEEXT@ $(libdir)/ivl/ivl@EXEEXT@
+	$(STRIP) $(strip_dynamic) $(libdir)/ivl/ivl@EXEEXT@
+
+# Install iverilog.conf whenever ivl.exe is installed. This
+# forces iverilog.conf to be treated similarly, in spite of
+# dates in the source bundle.
+$(libdir)/ivl/iverilog.conf: $(libdir)/ivl/ivl@EXEEXT@
+	$(INSTALL_DATA) $(srcdir)/iverilog.conf $(libdir)/ivl/iverilog.conf
+
+$(includedir)/ivl_target.h: $(srcdir)/ivl_target.h
+	$(INSTALL_DATA) $(srcdir)/ivl_target.h $(includedir)/ivl_target.h
+
+$(includedir)/vpi_user.h: $(srcdir)/vpi_user.h
+	$(INSTALL_DATA) $(srcdir)/vpi_user.h $(includedir)/vpi_user.h
+
+$(includedir)/acc_user.h: $(srcdir)/acc_user.h
+	$(INSTALL_DATA) $(srcdir)/acc_user.h $(includedir)/acc_user.h
+
+$(includedir)/veriuser.h: $(srcdir)/veriuser.h
+	$(INSTALL_DATA) $(srcdir)/veriuser.h $(includedir)/veriuser.h
+
+$(mandir)/man1/iverilog-vpi.1: $(srcdir)/iverilog-vpi.man
+	$(INSTALL_DATA) $(srcdir)/iverilog-vpi.man $(mandir)/man1/iverilog-vpi.1
+
+$(prefix)/iverilog-vpi.pdf: iverilog-vpi.pdf
+	$(INSTALL_DATA) iverilog-vpi.pdf $(prefix)/iverilog-vpi.pdf
+
+# In windows installations, put a few examples and the quick_start
+# into the destination directory.
+ifeq (@WIN32@,yes)
+$(prefix)/hello.vl: $(srcdir)/examples/hello.vl
+	./dosify.exe $(srcdir)/examples/hello.vl tmp.vl
+	mv tmp.vl $(prefix)/hello.vl
+
+$(prefix)/sqrt.vl: $(srcdir)/examples/sqrt.vl
+	./dosify.exe $(srcdir)/examples/sqrt.vl tmp.vl
+	mv tmp.vl $(prefix)/sqrt.vl
+
+$(prefix)/sqrt-virtex.v: $(srcdir)/examples/sqrt-virtex.v
+	./dosify.exe $(srcdir)/examples/sqrt-virtex.v tmp.vl
+	mv tmp.vl $(prefix)/sqrt-virtex.v
+
+$(prefix)/QUICK_START.txt: $(srcdir)/QUICK_START.txt
+	./dosify.exe $(srcdir)/QUICK_START.txt tmp.txt
+	mv tmp.txt $(prefix)/QUICK_START.txt
+endif
 
 installdirs: mkinstalldirs
-	$(srcdir)/mkinstalldirs $(bindir) $(libdir)/ivl $(mandir)/man1
+	$(srcdir)/mkinstalldirs $(bindir) $(includedir) $(libdir)/ivl \
+	    $(mandir) $(mandir)/man1
 
 uninstall:
+	rm -f $(libdir)/ivl/iverilog.conf
 	rm -f $(libdir)/ivl/ivl
+	-rmdir $(libdir)/ivl
+	rm -f $(libdir)/libvpi.a
 	rm -f $(bindir)/verilog
-	rm -f $(bindir)/gverilog
-	rm -f $(bindir)/iverilog
-	rm -f $(mandir)/man1/verilog.1
-	rm -f $(mandir)/man1/iverilog.1
+	rm -f $(bindir)/iverilog-vpi
+	rm -f $(bindir)/gverilog@EXEEXT@
+	rm -f $(includedir)/ivl_target.h
+	rm -f $(includedir)/vpi_user.h
+	rm -f $(includedir)/acc_user.h
+	rm -f $(includedir)/veriuser.h
+	rm -f $(mandir)/man1/iverilog-vpi.1
+	cd driver ; $(MAKE) uninstall
 	cd vpi ; $(MAKE) uninstall
-	cd vvm ; $(MAKE) uninstall
 	cd ivlpp ; $(MAKE) uninstall
+	for tgt in $(SUBDIRS); do (cd $$tgt ; $(MAKE) uninstall); done
+	for tgt in $(TARGETS); do (cd $$tgt ; $(MAKE) uninstall); done
 
 
 -include $(patsubst %.o, dep/%.d, $O)
+-include $(patsubst %.o, dep/%.d, vpithunk.o)

Module.cc

@@ -16,21 +16,25 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: Module.cc,v 1.12 2000/05/16 04:05:15 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: Module.cc,v 1.19 2002/08/12 01:34:58 steve Exp $"
 #endif
 
+# include "config.h"
+
 # include  "Module.h"
 # include  "PGate.h"
 # include  "PWire.h"
 # include  <assert.h>
 
-Module::Module(const string&name, const svector<Module::port_t*>*pp)
-: name_(name)
+Module::Module(const char*name)
+: name_(strdup(name))
 {
-      if (pp)
-	    ports_ = *pp;
+}
 
+Module::~Module()
+{
+      free(name_);
 }
 
 void Module::add_gate(PGate*gate)
@@ -50,7 +54,7 @@ void Module::add_function(const string &name, PFunction *func)
 
 PWire* Module::add_wire(PWire*wire)
 {
-      PWire*&ep = wires_[wire->name()];
+      PWire*&ep = wires_[wire->path()];
       if (ep) return ep;
 
       assert(ep == 0);
@@ -65,29 +69,39 @@ void Module::add_behavior(PProcess*b)
 
 unsigned Module::port_count() const
 {
-      return ports_.count();
+      return ports.count();
 }
 
+/*
+ * Return the array of PEIdent object that are at this port of the
+ * module. If the port is internally unconnected, return an empty
+ * array. 
+ */
 const svector<PEIdent*>& Module::get_port(unsigned idx) const
 {
-      assert(idx < ports_.count());
-      return ports_[idx]->expr;
+      assert(idx < ports.count());
+      static svector<PEIdent*> zero;
+
+      if (ports[idx])
+	    return ports[idx]->expr;
+      else
+	    return zero;
 }
 
 unsigned Module::find_port(const string&name) const
 {
       assert(name != "");
-      for (unsigned idx = 0 ;  idx < ports_.count() ;  idx += 1)
-	    if (ports_[idx]->name == name)
+      for (unsigned idx = 0 ;  idx < ports.count() ;  idx += 1)
+	    if (ports[idx]->name == name)
 		  return idx;
 
-      return ports_.count();
+      return ports.count();
 }
 
 
-PWire* Module::get_wire(const string&name) const
+PWire* Module::get_wire(const hname_t&name) const
 {
-      map<string,PWire*>::const_iterator obj = wires_.find(name);
+      map<hname_t,PWire*>::const_iterator obj = wires_.find(name);
       if (obj == wires_.end())
 	    return 0;
       else
@@ -107,7 +121,7 @@ PGate* Module::get_gate(const string&name)
       return 0;
 }
 
-const map<string,PWire*>& Module::get_wires() const
+const map<hname_t,PWire*>& Module::get_wires() const
 {
       return wires_;
 }
@@ -125,6 +139,29 @@ const list<PProcess*>& Module::get_behaviors() const
 
 /*
  * $Log: Module.cc,v $
+ * Revision 1.19  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.18  2002/05/19 23:37:28  steve
+ *  Parse port_declaration_lists from the 2001 Standard.
+ *
+ * Revision 1.17  2001/12/03 04:47:14  steve
+ *  Parser and pform use hierarchical names as hname_t
+ *  objects instead of encoded strings.
+ *
+ * Revision 1.16  2001/10/20 05:21:51  steve
+ *  Scope/module names are char* instead of string.
+ *
+ * Revision 1.15  2001/07/25 03:10:48  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
+ * Revision 1.14  2000/11/15 20:31:05  steve
+ *  Fix warning about temporaries.
+ *
+ * Revision 1.13  2000/11/05 06:05:59  steve
+ *  Handle connectsion to internally unconnected modules (PR#38)
+ *
  * Revision 1.12  2000/05/16 04:05:15  steve
  *  Module ports are really special PEIdent
  *  expressions, because a name can be used

Module.h

@@ -18,14 +18,16 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: Module.h,v 1.19 2000/05/16 04:05:15 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: Module.h,v 1.27 2002/08/19 02:39:16 steve Exp $"
 #endif
 
 # include  <list>
 # include  <map>
 # include  "svector.h"
+# include  "HName.h"
 # include  "named.h"
+# include  "LineInfo.h"
 # include  <string>
 class PEvent;
 class PExpr;
@@ -44,7 +46,7 @@ class NetScope;
  * therefore the handle for grasping the described circuit.
  */
 
-class Module {
+class Module : public LineInfo {
 
 	/* The module ports are in general a vector of port_t
 	   objects. Each port has a name and an ordered list of
@@ -58,20 +60,27 @@ class Module {
       };
 
     public:
-      explicit Module(const string&name, const svector<port_t*>*);
+      explicit Module(const char*name);
+      ~Module();
 
 
 	/* The module has parameters that are evaluated when the
 	   module is elaborated. During parsing, I put the parameters
 	   into this map. */
-      map<string,PExpr*>parameters;
-      map<string,PExpr*>localparams;
+      struct param_expr_t {
+	    PExpr*expr;
+	    PExpr*msb;
+	    PExpr*lsb;
+	    bool signed_flag;
+      };
+      map<string,param_expr_t>parameters;
+      map<string,param_expr_t>localparams;
 
 	/* The module also has defparam assignments which don't create
 	   new parameters within the module, but may be used to set
 	   values within this module (when instantiated) or in other
 	   instantiated modules. */
-      map<string,PExpr*>defparms;
+      map<hname_t,PExpr*>defparms;
 
         /* Parameters may be overridden at instantiation time;
            the overrides do not contain explicit parameter names,
@@ -81,11 +90,18 @@ class Module {
            a parameter-index to its name. */
       list<string> param_names;
 
+	/* This is an array of port descriptors, which is in turn a
+	   named array of PEident pointers. */
+      svector<port_t*> ports;
+
 	/* Keep a table of named events declared in the module. */
       map<string,PEvent*>events;
 
+	/* These are the timescale for this module. The default is
+	   set by the `timescale directive. */
+      int time_unit, time_precision;
 
-      const string&get_name() const { return name_; }
+      const char*mod_name() const { return name_; }
 
       void add_gate(PGate*gate);
 
@@ -104,10 +120,10 @@ class Module {
 
 	// Find a wire by name. This is used for connecting gates to
 	// existing wires, etc.
-      PWire* get_wire(const string&name) const;
+      PWire* get_wire(const hname_t&name) const;
       PGate* get_gate(const string&name);
 
-      const map<string,PWire*>& get_wires() const;
+      const map<hname_t,PWire*>& get_wires() const;
       const list<PGate*>& get_gates() const;
       const list<PProcess*>& get_behaviors() const;
 
@@ -119,10 +135,9 @@ class Module {
       bool elaborate_sig(Design*, NetScope*scope) const;
 
     private:
-      const string name_;
+      char* name_;
 
-      svector<port_t*> ports_;
-      map<string,PWire*> wires_;
+      map<hname_t,PWire*> wires_;
       list<PGate*> gates_;
       list<PProcess*> behaviors_;
       map<string,PTask*> tasks_;
@@ -136,6 +151,31 @@ class Module {
 
 /*
  * $Log: Module.h,v $
+ * Revision 1.27  2002/08/19 02:39:16  steve
+ *  Support parameters with defined ranges.
+ *
+ * Revision 1.26  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.25  2002/05/19 23:37:28  steve
+ *  Parse port_declaration_lists from the 2001 Standard.
+ *
+ * Revision 1.24  2001/12/03 04:47:14  steve
+ *  Parser and pform use hierarchical names as hname_t
+ *  objects instead of encoded strings.
+ *
+ * Revision 1.23  2001/10/31 03:11:15  steve
+ *  detect module ports not declared within the module.
+ *
+ * Revision 1.22  2001/10/20 05:21:51  steve
+ *  Scope/module names are char* instead of string.
+ *
+ * Revision 1.21  2000/11/05 06:05:59  steve
+ *  Handle connectsion to internally unconnected modules (PR#38)
+ *
+ * Revision 1.20  2000/07/22 22:09:03  steve
+ *  Parse and elaborate timescale to scopes.
+ *
  * Revision 1.19  2000/05/16 04:05:15  steve
  *  Module ports are really special PEIdent
  *  expressions, because a name can be used

PDelays.cc

@@ -16,24 +16,31 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PDelays.cc,v 1.2 2000/02/23 02:56:53 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PDelays.cc,v 1.9 2002/08/12 01:34:58 steve Exp $"
 #endif
 
+# include "config.h"
+
+# include  <iostream>
+
 # include  "PDelays.h"
 # include  "PExpr.h"
 # include  "verinum.h"
 
 PDelays::PDelays()
 {
+      delete_flag_ = true;
       for (unsigned idx = 0 ;  idx < 3 ;  idx += 1)
 	    delay_[idx] = 0;
 }
 
 PDelays::~PDelays()
 {
-      for (unsigned idx = 0 ;  idx < 3 ;  idx += 1)
-	    delete delay_[idx];
+      if (delete_flag_) {
+	    for (unsigned idx = 0 ;  idx < 3 ;  idx += 1)
+		  delete delay_[idx];
+      }
 }
 
 void PDelays::set_delay(PExpr*del)
@@ -41,41 +48,69 @@ void PDelays::set_delay(PExpr*del)
       assert(del);
       assert(delay_[0] == 0);
       delay_[0] = del;
+      delete_flag_ = true;
 }
 
 
-void PDelays::set_delays(const svector<PExpr*>*del)
+void PDelays::set_delays(const svector<PExpr*>*del, bool df)
 {
       assert(del);
       assert(del->count() <= 3);
       for (unsigned idx = 0 ;  idx < del->count() ;  idx += 1)
 	    delay_[idx] = (*del)[idx];
+
+      delete_flag_ = df;
 }
 
-void PDelays::eval_delays(Design*des, const string&path,
-			unsigned long&rise_time,
-			unsigned long&fall_time,
-			unsigned long&decay_time) const
+static unsigned long calculate_val(Design*des, const NetScope*scope,
+				   const PExpr*expr)
 {
-      verinum*dv;
+      assert(expr);
+      unsigned long val;
+
+      int shift = scope->time_unit() - des->get_precision();
+
+      if (verireal*dr = expr->eval_rconst(des, scope)) {
+	    val = dr->as_long(shift);
+	    delete dr;
+
+      } else {
+	    verinum*dv = expr->eval_const(des, scope);
+	    if (dv == 0) {
+		  cerr << expr->get_line() << ": sorry: non-constant "
+		       << "delays not supported here: " << *expr << endl;
+		  des->errors += 1;
+		  return 0;
+	    }
+
+	    assert(dv);
+	    val = dv->as_ulong();
+	    val = des->scale_to_precision(val, scope);
+	    delete dv;
+      }
+
+      return val;
+}
+
+void PDelays::eval_delays(Design*des, NetScope*scope,
+			  unsigned long&rise_time,
+			  unsigned long&fall_time,
+			  unsigned long&decay_time) const
+{
+      assert(scope);
+
+      int shift = scope->time_unit() - des->get_precision();
+
 
       if (delay_[0]) {
-	    dv = delay_[0]->eval_const(des, path);
-	    assert(dv);
-	    rise_time = dv->as_ulong();
-	    delete dv;
+	    rise_time = calculate_val(des, scope, delay_[0]);
 
 	    if (delay_[1]) {
-		  dv = delay_[1]->eval_const(des, path);
-		  assert(dv);
-		  fall_time = dv->as_ulong();
-		  delete dv;
+		  fall_time = calculate_val(des, scope, delay_[1]);
 
 		  if (delay_[2]) {
-			dv = delay_[2]->eval_const(des, path);
-			assert(dv);
-			decay_time = dv->as_ulong();
-			delete dv;
+			decay_time = calculate_val(des, scope, delay_[2]);
+
 		  } else {
 			if (rise_time < fall_time)
 			      decay_time = rise_time;
@@ -96,6 +131,31 @@ void PDelays::eval_delays(Design*des, const string&path,
 
 /*
  * $Log: PDelays.cc,v $
+ * Revision 1.9  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.8  2001/12/29 20:19:31  steve
+ *  Do not delete delay expressions of UDP instances.
+ *
+ * Revision 1.7  2001/11/22 06:20:59  steve
+ *  Use NetScope instead of string for scope path.
+ *
+ * Revision 1.6  2001/11/07 04:01:59  steve
+ *  eval_const uses scope instead of a string path.
+ *
+ * Revision 1.5  2001/07/25 03:10:48  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
+ * Revision 1.4  2001/01/20 02:15:50  steve
+ *  apologize for not supporting non-constant delays.
+ *
+ * Revision 1.3  2001/01/14 23:04:55  steve
+ *  Generalize the evaluation of floating point delays, and
+ *  get it working with delay assignment statements.
+ *
+ *  Allow parameters to be referenced by hierarchical name.
+ *
  * Revision 1.2  2000/02/23 02:56:53  steve
  *  Macintosh compilers do not support ident.
  *

PDelays.h

@@ -1,7 +1,7 @@
 #ifndef __PDelays_H
 #define __PDelays_H
 /*
- * Copyright (c) 1999 Stephen Williams ([email protected])
+ * Copyright (c) 1999-2002 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -18,15 +18,23 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PDelays.h,v 1.2 2000/02/23 02:56:53 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PDelays.h,v 1.7 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include  "svector.h"
 # include  <string>
+# include  <iostream>
+
+#ifdef __GNUC__
+#if __GNUC__ > 2
+using namespace std;
+#endif
+#endif
+
 class Design;
+class NetScope;
 class PExpr;
-class ostream;
 
 /*
  * Various PForm objects can carry delays. These delays include rise,
@@ -38,10 +46,13 @@ class PDelays {
       PDelays();
       ~PDelays();
 
+	/* Set the delay expressions. If the delete_flag is true, then
+	   this object takes ownership of the expressions, and will
+	   delete it in the destructor. */
       void set_delay(PExpr*);
-      void set_delays(const svector<PExpr*>*del);
+      void set_delays(const svector<PExpr*>*del, bool delete_flag=true);
 
-      void eval_delays(Design*des, const string&path,
+      void eval_delays(Design*des, NetScope*scope,
 		       unsigned long&rise_time,
 		       unsigned long&fall_time,
 		       unsigned long&decay_time) const;
@@ -50,6 +61,7 @@ class PDelays {
 
     private:
       PExpr* delay_[3];
+      bool delete_flag_;
 
     private: // not implemented
       PDelays(const PDelays&);
@@ -60,6 +72,21 @@ ostream& operator << (ostream&o, const PDelays&);
 
 /*
  * $Log: PDelays.h,v $
+ * Revision 1.7  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.6  2002/06/14 03:25:51  steve
+ *  Compiler portability.
+ *
+ * Revision 1.5  2001/12/29 20:19:31  steve
+ *  Do not delete delay expressions of UDP instances.
+ *
+ * Revision 1.4  2001/11/22 06:20:59  steve
+ *  Use NetScope instead of string for scope path.
+ *
+ * Revision 1.3  2001/01/16 02:44:17  steve
+ *  Use the iosfwd header if available.
+ *
  * Revision 1.2  2000/02/23 02:56:53  steve
  *  Macintosh compilers do not support ident.
  *

PEvent.cc

@@ -16,10 +16,12 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PEvent.cc,v 1.1 2000/04/01 19:31:57 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PEvent.cc,v 1.3 2002/08/12 01:34:58 steve Exp $"
 #endif
 
+# include "config.h"
+
 # include  "PEvent.h"
 
 PEvent::PEvent(const string&n)
@@ -38,6 +40,13 @@ string PEvent::name() const
 
 /*
  * $Log: PEvent.cc,v $
+ * Revision 1.3  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.2  2001/07/25 03:10:48  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
  * Revision 1.1  2000/04/01 19:31:57  steve
  *  Named events as far as the pform.
  *

PEvent.h

@@ -18,19 +18,20 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PEvent.h,v 1.3 2000/04/09 17:44:30 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PEvent.h,v 1.6 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include  "LineInfo.h"
 # include  <string>
-class ostream;
+
 class Design;
 class NetScope;
 
 /*
  * The PEvent class represents event objects. These are things that
- * are declared in Verilog as ``event foo;''
+ * are declared in Verilog as ``event foo;'' The name passed to the
+ * constructure is the "foo" part of the declaration.
  */
 class PEvent : public LineInfo {
 
@@ -52,6 +53,16 @@ class PEvent : public LineInfo {
 
 /*
  * $Log: PEvent.h,v $
+ * Revision 1.6  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.5  2001/12/03 04:47:14  steve
+ *  Parser and pform use hierarchical names as hname_t
+ *  objects instead of encoded strings.
+ *
+ * Revision 1.4  2001/01/16 02:44:18  steve
+ *  Use the iosfwd header if available.
+ *
  * Revision 1.3  2000/04/09 17:44:30  steve
  *  Catch event declarations during scope elaborate.
  *

PExpr.cc

@@ -16,10 +16,14 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PExpr.cc,v 1.18 2000/05/07 04:37:55 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PExpr.cc,v 1.32 2002/11/09 19:20:48 steve Exp $"
 #endif
 
+# include "config.h"
+
+# include  <iostream>
+
 # include  "PExpr.h"
 # include  "Module.h"
 # include  <typeinfo>
@@ -42,37 +46,34 @@ bool PExpr::is_constant(Module*) const
       return false;
 }
 
-NetNet* PExpr::elaborate_net(Design*des, const string&path, unsigned,
-			     unsigned long,
-			     unsigned long,
-			     unsigned long,
-			     Link::strength_t,
-			     Link::strength_t) const
-{
-      cerr << get_line() << ": error: Unable to elaborate `"
-	   << *this << "' as gates." << endl;
-      return 0;
-}
-
-NetNet* PExpr::elaborate_lnet(Design*des, const string&path) const
+NetNet* PExpr::elaborate_lnet(Design*des, NetScope*, bool) const
 {
       cerr << get_line() << ": error: expression not valid in assign l-value: "
 	   << *this << endl;
       return 0;
 }
 
+PEBinary::PEBinary(char op, PExpr*l, PExpr*r)
+: op_(op), left_(l), right_(r)
+{
+}
+
+PEBinary::~PEBinary()
+{
+}
+
 bool PEBinary::is_constant(Module*mod) const
 {
       return left_->is_constant(mod) && right_->is_constant(mod);
 }
 
-PECallFunction::PECallFunction(const char*n, const svector<PExpr *> &parms) 
-: name_(n), parms_(parms)
+PECallFunction::PECallFunction(const hname_t&n, const svector<PExpr *> &parms) 
+: path_(n), parms_(parms)
 {
 }
 
-PECallFunction::PECallFunction(const char*n) 
-: name_(n)
+PECallFunction::PECallFunction(const hname_t&n) 
+: path_(n)
 {
 }
 
@@ -118,8 +119,28 @@ PExpr* PEEvent::expr() const
       return expr_;
 }
 
-PEIdent::PEIdent(const string&s)
-: text_(s), msb_(0), lsb_(0), idx_(0)
+PEFNumber::PEFNumber(verireal*v)
+: value_(v)
+{
+}
+
+PEFNumber::~PEFNumber()
+{
+      delete value_;
+}
+
+const verireal& PEFNumber::value() const
+{
+      return *value_;
+}
+
+bool PEFNumber::is_constant(Module*) const
+{
+      return true;
+}
+
+PEIdent::PEIdent(const hname_t&s)
+: path_(s), msb_(0), lsb_(0), idx_(0)
 {
 }
 
@@ -127,9 +148,9 @@ PEIdent::~PEIdent()
 {
 }
 
-string PEIdent::name() const
+const hname_t& PEIdent::path() const
 {
-      return text_;
+      return path_;
 }
 
 /*
@@ -138,13 +159,17 @@ string PEIdent::name() const
  */
 bool PEIdent::is_constant(Module*mod) const
 {
-      map<string,PExpr*>::const_iterator cur;
+      if (mod == 0) return false;
 
-      cur = mod->parameters.find(text_);
-      if (cur != mod->parameters.end()) return true;
+      { map<string,Module::param_expr_t>::const_iterator cur;
+        cur = mod->parameters.find(path_.peek_name(0));
+	if (cur != mod->parameters.end()) return true;
+      }
 
-      cur = mod->localparams.find(text_);
-      if (cur != mod->localparams.end()) return true;
+      { map<string,Module::param_expr_t>::const_iterator cur;
+        cur = mod->localparams.find(path_.peek_name(0));
+	if (cur != mod->localparams.end()) return true;
+      }
 
       return false;
 }
@@ -179,13 +204,14 @@ bool PENumber::is_constant(Module*) const
       return true;
 }
 
-PEString::PEString(const string&s)
+PEString::PEString(char*s)
 : text_(s)
 {
 }
 
 PEString::~PEString()
 {
+      delete[]text_;
 }
 
 string PEString::value() const
@@ -207,13 +233,76 @@ PETernary::~PETernary()
 {
 }
 
-bool PETernary::is_constant(Module*) const
+bool PETernary::is_constant(Module*m) const
 {
-      return false;
+      return expr_->is_constant(m)
+	    && tru_->is_constant(m)
+	    && fal_->is_constant(m);
+}
+
+PEUnary::PEUnary(char op, PExpr*ex)
+: op_(op), expr_(ex)
+{
+}
+
+PEUnary::~PEUnary()
+{
+}
+
+bool PEUnary::is_constant(Module*m) const
+{
+      return expr_->is_constant(m);
 }
 
 /*
  * $Log: PExpr.cc,v $
+ * Revision 1.32  2002/11/09 19:20:48  steve
+ *  Port expressions for output ports are lnets, not nets.
+ *
+ * Revision 1.31  2002/08/19 02:39:16  steve
+ *  Support parameters with defined ranges.
+ *
+ * Revision 1.30  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.29  2001/12/30 21:32:03  steve
+ *  Support elaborate_net for PEString objects.
+ *
+ * Revision 1.28  2001/12/03 04:47:14  steve
+ *  Parser and pform use hierarchical names as hname_t
+ *  objects instead of encoded strings.
+ *
+ * Revision 1.27  2001/11/08 05:15:50  steve
+ *  Remove string paths from PExpr elaboration.
+ *
+ * Revision 1.26  2001/11/07 04:26:46  steve
+ *  elaborate_lnet uses scope instead of string path.
+ *
+ * Revision 1.25  2001/11/06 06:11:55  steve
+ *  Support more real arithmetic in delay constants.
+ *
+ * Revision 1.24  2001/07/25 03:10:48  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
+ * Revision 1.23  2001/01/14 23:04:55  steve
+ *  Generalize the evaluation of floating point delays, and
+ *  get it working with delay assignment statements.
+ *
+ *  Allow parameters to be referenced by hierarchical name.
+ *
+ * Revision 1.22  2001/01/12 04:31:27  steve
+ *  Handle error idents in constants not in any scope (PR#97)
+ *
+ * Revision 1.21  2000/12/16 19:03:30  steve
+ *  Evaluate <= and ?: in parameter expressions (PR#81)
+ *
+ * Revision 1.20  2000/12/10 22:01:35  steve
+ *  Support decimal constants in behavioral delays.
+ *
+ * Revision 1.19  2000/06/30 15:50:20  steve
+ *  Allow unary operators in constant expressions.
+ *
  * Revision 1.18  2000/05/07 04:37:55  steve
  *  Carry strength values from Verilog source to the
  *  pform and netlist for gates.

PExpr.h

@@ -18,8 +18,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PExpr.h,v 1.40 2000/06/13 05:22:16 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PExpr.h,v 1.63 2002/11/09 19:20:48 steve Exp $"
 #endif
 
 # include  <string>
@@ -51,8 +51,11 @@ class PExpr : public LineInfo {
 
       virtual void dump(ostream&) const;
 
-	// Procedural elaboration of the expression.
-      virtual NetExpr*elaborate_expr(Design*des, NetScope*scope) const;
+	// Procedural elaboration of the expression. Set thie
+	// bare_memory_ok flag if the result is allowed to be a
+	// NetEMemory without an index.
+      virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
+				     bool sys_task_arg =false) const;
 
 	// Elaborate expressions that are the r-value of parameter
 	// assignments. This elaboration follows the restrictions of
@@ -62,7 +65,7 @@ class PExpr : public LineInfo {
 
 	// This method elaborate the expression as gates, for use in a
 	// continuous assign or other wholly structural context.
-      virtual NetNet* elaborate_net(Design*des, const string&path,
+      virtual NetNet* elaborate_net(Design*des, NetScope*scope,
 				    unsigned lwidth,
 				    unsigned long rise,
 				    unsigned long fall,
@@ -71,14 +74,28 @@ class PExpr : public LineInfo {
 				    Link::strength_t drive1 =Link::STRONG)
 	    const;
 
+	// This method elaborates the expression as NetNet objects. It
+	// only allows regs suitable for procedural continuous assignments.
+      virtual NetNet* elaborate_anet(Design*des, NetScope*scope) const;
+
 	// This method elaborates the expression as gates, but
 	// restricted for use as l-values of continuous assignments.
-      virtual NetNet* elaborate_lnet(Design*des, const string&path) const;
+      virtual NetNet* elaborate_lnet(Design*des, NetScope*scope,
+				     bool implicit_net_ok =false) const;
+
+	// Expressions that can be in the l-value of procedural
+	// assignments can be elaborated with this method.
+      virtual NetAssign_* elaborate_lval(Design*des, NetScope*scope) const;
 
 	// This attempts to evaluate a constant expression, and return
 	// a verinum as a result. If the expression cannot be
 	// evaluated, return 0.
-      virtual verinum* eval_const(const Design*des, const string&path) const;
+      virtual verinum* eval_const(const Design*des, const NetScope*sc) const;
+
+	// This attempts to evaluate a constant expression as a
+	// decimal floating point. This is used when calculating delay
+	// constants.
+      virtual verireal* eval_rconst(const Design*, const NetScope*) const;
 
 	// This method returns true if that expression is the same as
 	// this expression. This method is used for comparing
@@ -105,16 +122,24 @@ class PEConcat : public PExpr {
       ~PEConcat();
 
       virtual void dump(ostream&) const;
-      virtual NetNet* elaborate_lnet(Design*des, const string&path) const;
-      virtual NetNet* elaborate_net(Design*des, const string&path,
+
+	// Concatenated Regs can be on the left of procedural
+	// continuous assignments.
+      virtual NetNet* elaborate_anet(Design*des, NetScope*scope) const;
+
+      virtual NetNet* elaborate_lnet(Design*des, NetScope*scope,
+				     bool implicit_net_ok =false) const;
+      virtual NetNet* elaborate_net(Design*des, NetScope*scope,
 				    unsigned width,
 				    unsigned long rise,
 				    unsigned long fall,
 				    unsigned long decay,
 				    Link::strength_t drive0,
 				    Link::strength_t drive1) const;
-      virtual NetExpr*elaborate_expr(Design*des, NetScope*) const;
+      virtual NetExpr*elaborate_expr(Design*des, NetScope*,
+				     bool sys_task_arg =false) const;
       virtual NetEConcat*elaborate_pexpr(Design*des, NetScope*) const;
+      virtual NetAssign_* elaborate_lval(Design*des, NetScope*scope) const;
       virtual bool is_constant(Module*) const;
 
     private:
@@ -141,7 +166,7 @@ class PEEvent : public PExpr {
 
       edge_t type() const;
       PExpr* expr() const;
-
+ 
       virtual void dump(ostream&) const;
 
     private:
@@ -149,19 +174,58 @@ class PEEvent : public PExpr {
       PExpr *expr_;
 };
 
+/*
+ * This holds a floating point constant in the source.
+ */
+class PEFNumber : public PExpr {
+
+    public:
+      explicit PEFNumber(verireal*vp);
+      ~PEFNumber();
+
+      const verireal& value() const;
+
+	/* The eval_const method as applied to a floating point number
+	   gets the *integer* value of the number. This accounts for
+	   any rounding that is needed to get the value. */
+      virtual verinum* eval_const(const Design*des, const NetScope*sc) const;
+
+	/* This method returns the full floating point value. */
+      virtual verireal* eval_rconst(const Design*, const NetScope*) const;
+
+	/* A PEFNumber is a constant, so this returns true. */
+      virtual bool is_constant(Module*) const;
+
+      virtual NetExpr*elaborate_expr(Design*des, NetScope*,
+				     bool sys_task_arg =false) const;
+      virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;
+
+      virtual void dump(ostream&) const;
+
+    private:
+      verireal*value_;
+};
+
 class PEIdent : public PExpr {
 
     public:
-      explicit PEIdent(const string&s);
+      explicit PEIdent(const hname_t&s);
       ~PEIdent();
 
       virtual void dump(ostream&) const;
 
+	// Regs can be on the left of procedural continuous assignments
+      virtual NetNet* elaborate_anet(Design*des, NetScope*scope) const;
+
 	// Identifiers are allowed (with restrictions) is assign l-values.
-      virtual NetNet* elaborate_lnet(Design*des, const string&path) const;
+      virtual NetNet* elaborate_lnet(Design*des, NetScope*scope,
+				     bool implicit_net_ok =false) const;
+
+	// Identifiers are also allowed as procedural assignment l-values.
+      virtual NetAssign_* elaborate_lval(Design*des, NetScope*scope) const;
 
 	// Structural r-values are OK.
-      virtual NetNet* elaborate_net(Design*des, const string&path,
+      virtual NetNet* elaborate_net(Design*des, NetScope*scope,
 				    unsigned lwidth,
 				    unsigned long rise,
 				    unsigned long fall,
@@ -169,7 +233,8 @@ class PEIdent : public PExpr {
 				    Link::strength_t drive0,
 				    Link::strength_t drive1) const;
 
-      virtual NetExpr*elaborate_expr(Design*des, NetScope*) const;
+      virtual NetExpr*elaborate_expr(Design*des, NetScope*,
+				     bool sys_task_arg =false) const;
       virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;
 
 	// Elaborate the PEIdent as a port to a module. This method
@@ -177,12 +242,13 @@ class PEIdent : public PExpr {
       NetNet* elaborate_port(Design*des, NetScope*sc) const;
 
       virtual bool is_constant(Module*) const;
-      verinum* eval_const(const Design*des, const string&path) const;
+      verinum* eval_const(const Design*des, const NetScope*sc) const;
+      verireal*eval_rconst(const Design*des, const NetScope*sc) const;
 
-      string name() const;
+      const hname_t& path() const;
 
     private:
-      string text_;
+      hname_t path_;
 
     public:
 	// Use these to support bit- and part-select operators.
@@ -193,11 +259,24 @@ class PEIdent : public PExpr {
 	// expression.
       PExpr*idx_;
 
-      NetNet* elaborate_net_ram_(Design*des, const string&path,
+      NetNet* elaborate_net_ram_(Design*des, NetScope*scope,
 				 NetMemory*mem, unsigned lwidth,
 				 unsigned long rise,
 				 unsigned long fall,
 				 unsigned long decay) const;
+
+      NetNet* elaborate_net_bitmux_(Design*des, NetScope*scope,
+				    NetNet*sig,
+				    unsigned long rise,
+				    unsigned long fall,
+				    unsigned long decay,
+				    Link::strength_t drive0,
+				    Link::strength_t drive1) const;
+
+    private:
+      NetAssign_* elaborate_mem_lval_(Design*des, NetScope*scope,
+				      NetMemory*mem) const;
+
 };
 
 class PENumber : public PExpr {
@@ -209,16 +288,20 @@ class PENumber : public PExpr {
       const verinum& value() const;
 
       virtual void dump(ostream&) const;
-      virtual NetNet* elaborate_net(Design*des, const string&path,
+      virtual NetNet* elaborate_net(Design*des, NetScope*scope,
 				    unsigned lwidth,
 				    unsigned long rise,
 				    unsigned long fall,
 				    unsigned long decay,
 				    Link::strength_t drive0,
 				    Link::strength_t drive1) const;
-      virtual NetEConst*elaborate_expr(Design*des, NetScope*) const;
+      virtual NetEConst*elaborate_expr(Design*des, NetScope*,
+				     bool sys_task_arg =false) const;
       virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;
-      virtual verinum* eval_const(const Design*des, const string&path) const;
+      virtual NetAssign_* elaborate_lval(Design*des, NetScope*scope) const;
+
+      virtual verinum* eval_const(const Design*des, const NetScope*sc) const;
+      virtual verireal*eval_rconst(const Design*, const NetScope*) const;
 
       virtual bool is_the_same(const PExpr*that) const;
       virtual bool is_constant(Module*) const;
@@ -227,39 +310,59 @@ class PENumber : public PExpr {
       verinum*const value_;
 };
 
+/*
+ * This represents a string constant in an expression.
+ *
+ * The s parameter to the PEString constructor is a C string that this
+ * class instance will take for its own. The caller should not delete
+ * the string, the destructor will do it.
+ */
 class PEString : public PExpr {
 
     public:
-      explicit PEString(const string&s);
+      explicit PEString(char*s);
       ~PEString();
 
       string value() const;
       virtual void dump(ostream&) const;
-      virtual NetEConst*elaborate_expr(Design*des, NetScope*) const;
-      virtual NetEConst*elaborate_pexpr(Design*des, NetScope*sc) const;
-
-      virtual bool is_constant(Module*) const;
-
-    private:
-      const string text_;
-};
-
-class PEUnary : public PExpr {
-
-    public:
-      explicit PEUnary(char op, PExpr*ex)
-      : op_(op), expr_(ex) { }
-
-      virtual void dump(ostream&out) const;
-      virtual NetNet* elaborate_net(Design*des, const string&path,
+      virtual NetNet* elaborate_net(Design*des, NetScope*scope,
 				    unsigned width,
 				    unsigned long rise,
 				    unsigned long fall,
 				    unsigned long decay,
 				    Link::strength_t drive0,
 				    Link::strength_t drive1) const;
-      virtual NetEUnary*elaborate_expr(Design*des, NetScope*) const;
+      virtual NetEConst*elaborate_expr(Design*des, NetScope*,
+				     bool sys_task_arg =false) const;
+      virtual NetEConst*elaborate_pexpr(Design*des, NetScope*sc) const;
+      verinum* PEString::eval_const(const Design*, const NetScope*) const;
+
+      virtual bool is_constant(Module*) const;
+
+    private:
+      char*text_;
+};
+
+class PEUnary : public PExpr {
+
+    public:
+      explicit PEUnary(char op, PExpr*ex);
+      ~PEUnary();
+
+      virtual void dump(ostream&out) const;
+      virtual NetNet* elaborate_net(Design*des, NetScope*scope,
+				    unsigned width,
+				    unsigned long rise,
+				    unsigned long fall,
+				    unsigned long decay,
+				    Link::strength_t drive0,
+				    Link::strength_t drive1) const;
+      virtual NetExpr*elaborate_expr(Design*des, NetScope*,
+				     bool sys_task_arg =false) const;
       virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;
+      virtual verinum* eval_const(const Design*des, const NetScope*sc) const;
+
+      virtual bool is_constant(Module*) const;
 
     private:
       char op_;
@@ -269,22 +372,24 @@ class PEUnary : public PExpr {
 class PEBinary : public PExpr {
 
     public:
-      explicit PEBinary(char op, PExpr*l, PExpr*r)
-      : op_(op), left_(l), right_(r) { }
+      explicit PEBinary(char op, PExpr*l, PExpr*r);
+      ~PEBinary();
 
       virtual bool is_constant(Module*) const;
 
       virtual void dump(ostream&out) const;
-      virtual NetNet* elaborate_net(Design*des, const string&path,
+      virtual NetNet* elaborate_net(Design*des, NetScope*scope,
 				    unsigned width,
 				    unsigned long rise,
 				    unsigned long fall,
 				    unsigned long decay,
 				    Link::strength_t drive0,
 				    Link::strength_t drive1) const;
-      virtual NetEBinary*elaborate_expr(Design*des, NetScope*) const;
+      virtual NetEBinary*elaborate_expr(Design*des, NetScope*,
+					bool sys_task_arg =false) const;
       virtual NetExpr*elaborate_pexpr(Design*des, NetScope*sc) const;
-      virtual verinum* eval_const(const Design*des, const string&path) const;
+      virtual verinum* eval_const(const Design*des, const NetScope*sc) const;
+      virtual verireal*eval_rconst(const Design*des, const NetScope*sc) const;
 
     private:
       char op_;
@@ -293,37 +398,42 @@ class PEBinary : public PExpr {
 
       NetEBinary*elaborate_expr_base_(Design*, NetExpr*lp, NetExpr*rp) const;
 
-      NetNet* elaborate_net_add_(Design*des, const string&path,
+      NetNet* elaborate_net_add_(Design*des, NetScope*scope,
 				 unsigned lwidth,
 				 unsigned long rise,
 				 unsigned long fall,
 				 unsigned long decay) const;
-      NetNet* elaborate_net_bit_(Design*des, const string&path,
+      NetNet* elaborate_net_bit_(Design*des, NetScope*scope,
 				 unsigned lwidth,
 				 unsigned long rise,
 				 unsigned long fall,
 				 unsigned long decay) const;
-      NetNet* elaborate_net_cmp_(Design*des, const string&path,
+      NetNet* elaborate_net_cmp_(Design*des, NetScope*scope,
 				 unsigned lwidth,
 				 unsigned long rise,
 				 unsigned long fall,
 				 unsigned long decay) const;
-      NetNet* elaborate_net_div_(Design*des, const string&path,
+      NetNet* elaborate_net_div_(Design*des, NetScope*scope,
 				 unsigned lwidth,
 				 unsigned long rise,
 				 unsigned long fall,
 				 unsigned long decay) const;
-      NetNet* elaborate_net_log_(Design*des, const string&path,
+      NetNet* elaborate_net_mod_(Design*des, NetScope*scope,
 				 unsigned lwidth,
 				 unsigned long rise,
 				 unsigned long fall,
 				 unsigned long decay) const;
-      NetNet* elaborate_net_mul_(Design*des, const string&path,
+      NetNet* elaborate_net_log_(Design*des, NetScope*scope,
 				 unsigned lwidth,
 				 unsigned long rise,
 				 unsigned long fall,
 				 unsigned long decay) const;
-      NetNet* elaborate_net_shift_(Design*des, const string&path,
+      NetNet* elaborate_net_mul_(Design*des, NetScope*scope,
+				 unsigned lwidth,
+				 unsigned long rise,
+				 unsigned long fall,
+				 unsigned long decay) const;
+      NetNet* elaborate_net_shift_(Design*des, NetScope*scope,
 				   unsigned lwidth,
 				   unsigned long rise,
 				   unsigned long fall,
@@ -343,15 +453,17 @@ class PETernary : public PExpr {
       virtual bool is_constant(Module*) const;
 
       virtual void dump(ostream&out) const;
-      virtual NetNet* elaborate_net(Design*des, const string&path,
+      virtual NetNet* elaborate_net(Design*des, NetScope*scope,
 				    unsigned width,
 				    unsigned long rise,
 				    unsigned long fall,
 				    unsigned long decay,
 				    Link::strength_t drive0,
 				    Link::strength_t drive1) const;
-      virtual NetETernary*elaborate_expr(Design*des, NetScope*) const;
-      virtual verinum* eval_const(const Design*des, const string&path) const;
+      virtual NetETernary*elaborate_expr(Design*des, NetScope*,
+					 bool sys_task_arg =false) const;
+      virtual NetETernary*elaborate_pexpr(Design*des, NetScope*sc) const;
+      virtual verinum* eval_const(const Design*des, const NetScope*sc) const;
 
     private:
       PExpr*expr_;
@@ -361,192 +473,85 @@ class PETernary : public PExpr {
 
 /*
  * This class represents a parsed call to a function, including calls
- * to system functions.
+ * to system functions. The parameters in the parms list are the
+ * expressions that are passed as input to the ports of the function.
  */
 class PECallFunction : public PExpr {
     public:
-      explicit PECallFunction(const char*n, const svector<PExpr *> &parms);
-      explicit PECallFunction(const char*n);
+      explicit PECallFunction(const hname_t&n, const svector<PExpr *> &parms);
+      explicit PECallFunction(const hname_t&n);
       ~PECallFunction();
 
       virtual void dump(ostream &) const;
-      virtual NetExpr*elaborate_expr(Design*des, NetScope*scope) const;
+      virtual NetNet* elaborate_net(Design*des, NetScope*scope,
+				    unsigned width,
+				    unsigned long rise,
+				    unsigned long fall,
+				    unsigned long decay,
+				    Link::strength_t drive0,
+				    Link::strength_t drive1) const;
+      virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
+				     bool sys_task_arg =false) const;
 
     private:
-      string name_;
+      hname_t path_;
       svector<PExpr *> parms_;
 
+      bool check_call_matches_definition_(Design*des, NetScope*dscope) const;
+
       NetExpr* elaborate_sfunc_(Design*des, NetScope*scope) const;
 };
 
 /*
  * $Log: PExpr.h,v $
- * Revision 1.40  2000/06/13 05:22:16  steve
- *  Support concatenation in parameter expressions.
+ * Revision 1.63  2002/11/09 19:20:48  steve
+ *  Port expressions for output ports are lnets, not nets.
  *
- * Revision 1.39  2000/06/01 02:31:39  steve
- *  Parameters can be strings.
+ * Revision 1.62  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
  *
- * Revision 1.38  2000/05/16 04:05:15  steve
- *  Module ports are really special PEIdent
- *  expressions, because a name can be used
- *  many places in the port list.
+ * Revision 1.61  2002/06/04 05:38:43  steve
+ *  Add support for memory words in l-value of
+ *  blocking assignments, and remove the special
+ *  NetAssignMem class.
  *
- * Revision 1.37  2000/05/07 04:37:56  steve
- *  Carry strength values from Verilog source to the
- *  pform and netlist for gates.
+ * Revision 1.60  2002/05/23 03:08:51  steve
+ *  Add language support for Verilog-2001 attribute
+ *  syntax. Hook this support into existing $attribute
+ *  handling, and add number and void value types.
  *
- *  Change vvm constants to use the driver_t to drive
- *  a constant value. This works better if there are
- *  multiple drivers on a signal.
+ *  Add to the ivl_target API new functions for access
+ *  of complex attributes attached to gates.
  *
- * Revision 1.36  2000/05/04 03:37:58  steve
- *  Add infrastructure for system functions, move
- *  $time to that structure and add $random.
+ * Revision 1.59  2002/04/23 03:53:59  steve
+ *  Add support for non-constant bit select.
  *
- * Revision 1.35  2000/04/12 04:23:57  steve
- *  Named events really should be expressed with PEIdent
- *  objects in the pform,
+ * Revision 1.58  2002/04/14 03:55:25  steve
+ *  Precalculate unary - if possible.
  *
- *  Handle named events within the mix of net events
- *  and edges. As a unified lot they get caught together.
- *  wait statements are broken into more complex statements
- *  that include a conditional.
+ * Revision 1.57  2002/04/13 02:33:17  steve
+ *  Detect missing indices to memories (PR#421)
  *
- *  Do not generate NetPEvent or NetNEvent objects in
- *  elaboration. NetEvent, NetEvWait and NetEvProbe
- *  take over those functions in the netlist.
+ * Revision 1.56  2002/03/09 04:02:26  steve
+ *  Constant expressions are not l-values for task ports.
  *
- * Revision 1.34  2000/04/01 21:40:22  steve
- *  Add support for integer division.
+ * Revision 1.55  2002/03/09 02:10:22  steve
+ *  Add the NetUserFunc netlist node.
  *
- * Revision 1.33  2000/04/01 19:31:57  steve
- *  Named events as far as the pform.
+ * Revision 1.54  2001/12/30 21:32:03  steve
+ *  Support elaborate_net for PEString objects.
  *
- * Revision 1.32  2000/03/12 18:22:11  steve
- *  Binary and unary operators in parameter expressions.
+ * Revision 1.53  2001/12/03 04:47:14  steve
+ *  Parser and pform use hierarchical names as hname_t
+ *  objects instead of encoded strings.
  *
- * Revision 1.31  2000/03/12 04:35:22  steve
- *  Allow parameter identifiers in parameter expressions.
+ * Revision 1.52  2001/11/08 05:15:50  steve
+ *  Remove string paths from PExpr elaboration.
  *
- * Revision 1.30  2000/03/08 04:36:53  steve
- *  Redesign the implementation of scopes and parameters.
- *  I now generate the scopes and notice the parameters
- *  in a separate pass over the pform. Once the scopes
- *  are generated, I can process overrides and evalutate
- *  paremeters before elaboration begins.
- *
- * Revision 1.29  2000/02/23 02:56:53  steve
- *  Macintosh compilers do not support ident.
- *
- * Revision 1.28  2000/02/16 03:58:27  steve
- *  Fix up width matching in structural bitwise operators.
- *
- * Revision 1.27  2000/01/13 03:35:35  steve
- *  Multiplication all the way to simulation.
- *
- * Revision 1.26  1999/12/16 03:46:39  steve
- *  Structural logical or.
- *
- * Revision 1.25  1999/11/21 00:13:08  steve
- *  Support memories in continuous assignments.
- *
- * Revision 1.24  1999/11/14 20:24:28  steve
- *  Add support for the LPM_CLSHIFT device.
- *
- * Revision 1.23  1999/11/05 21:45:19  steve
- *  Fix NetConst being set to zero width, and clean
- *  up elaborate_set_cmp_ for NetEBinary.
- *
- * Revision 1.22  1999/10/31 20:08:24  steve
- *  Include subtraction in LPM_ADD_SUB device.
- *
- * Revision 1.21  1999/10/31 04:11:27  steve
- *  Add to netlist links pin name and instance number,
- *  and arrange in vvm for pin connections by name
- *  and instance number.
- *
- * Revision 1.20  1999/09/25 02:57:29  steve
- *  Parse system function calls.
- *
- * Revision 1.19  1999/09/15 04:17:52  steve
- *  separate assign lval elaboration for error checking.
- *
- * Revision 1.18  1999/08/31 22:38:29  steve
- *  Elaborate and emit to vvm procedural functions.
- *
- * Revision 1.17  1999/08/01 21:18:55  steve
- *  elaborate rise/fall/decay for continuous assign.
- *
- * Revision 1.16  1999/07/31 19:14:47  steve
- *  Add functions up to elaboration (Ed Carter)
- *
- * Revision 1.15  1999/07/22 02:05:20  steve
- *  is_constant method for PEConcat.
- *
- * Revision 1.14  1999/07/17 19:50:59  steve
- *  netlist support for ternary operator.
- *
- * Revision 1.13  1999/06/16 03:13:29  steve
- *  More syntax parse with sorry stubs.
- *
- * Revision 1.12  1999/06/15 02:50:02  steve
- *  Add lexical support for real numbers.
- *
- * Revision 1.11  1999/06/10 04:03:52  steve
- *  Add support for the Ternary operator,
- *  Add support for repeat concatenation,
- *  Correct some seg faults cause by elaboration
- *  errors,
- *  Parse the casex anc casez statements.
- *
- * Revision 1.10  1999/06/09 03:00:05  steve
- *  Add support for procedural concatenation expression.
- *
- * Revision 1.9  1999/05/16 05:08:42  steve
- *  Redo constant expression detection to happen
- *  after parsing.
- *
- *  Parse more operators and expressions.
- *
- * Revision 1.8  1999/05/10 00:16:57  steve
- *  Parse and elaborate the concatenate operator
- *  in structural contexts, Replace vector<PExpr*>
- *  and list<PExpr*> with svector<PExpr*>, evaluate
- *  constant expressions with parameters, handle
- *  memories as lvalues.
- *
- *  Parse task declarations, integer types.
- *
- * Revision 1.7  1999/05/01 02:57:52  steve
- *  Handle much more complex event expressions.
- *
- * Revision 1.6  1999/04/29 02:16:26  steve
- *  Parse OR of event expressions.
- *
- * Revision 1.5  1999/04/19 01:59:36  steve
- *  Add memories to the parse and elaboration phases.
- *
- * Revision 1.4  1998/11/11 00:01:51  steve
- *  Check net ranges in declarations.
- *
- * Revision 1.3  1998/11/09 18:55:33  steve
- *  Add procedural while loops,
- *  Parse procedural for loops,
- *  Add procedural wait statements,
- *  Add constant nodes,
- *  Add XNOR logic gate,
- *  Make vvm output look a bit prettier.
- *
- * Revision 1.2  1998/11/07 17:05:05  steve
- *  Handle procedural conditional, and some
- *  of the conditional expressions.
- *
- *  Elaborate signals and identifiers differently,
- *  allowing the netlist to hold signal information.
- *
- * Revision 1.1  1998/11/03 23:28:54  steve
- *  Introduce verilog to CVS.
+ * Revision 1.51  2001/11/07 04:26:46  steve
+ *  elaborate_lnet uses scope instead of string path.
  *
+ * Revision 1.50  2001/11/07 04:01:59  steve
+ *  eval_const uses scope instead of a string path.
  */
 #endif

PFunction.cc

@@ -16,14 +16,16 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PFunction.cc,v 1.3 2000/02/23 02:56:53 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PFunction.cc,v 1.6 2002/08/12 01:34:58 steve Exp $"
 #endif
 
+# include "config.h"
+
 #include "PTask.h"
 
-PFunction::PFunction(svector<PWire*>*p, Statement*s)
-: out_(0), ports_(p), statement_(s)
+PFunction::PFunction()
+: out_(0), ports_(0), statement_(0)
 {
 }
 
@@ -31,6 +33,19 @@ PFunction::~PFunction()
 {
 }
 
+void PFunction::set_ports(svector<PWire *>*p)
+{
+      assert(ports_ == 0);
+      ports_ = p;
+}
+
+void PFunction::set_statement(Statement*s)
+{
+      assert(s != 0);
+      assert(statement_ == 0);
+      statement_ = s;
+}
+
 void PFunction::set_output(PWire*o)
 {
       assert(out_ == 0);
@@ -39,6 +54,16 @@ void PFunction::set_output(PWire*o)
 
 /*
  * $Log: PFunction.cc,v $
+ * Revision 1.6  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.5  2001/07/25 03:10:48  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
+ * Revision 1.4  2001/01/13 22:20:08  steve
+ *  Parse parameters within nested scopes.
+ *
  * Revision 1.3  2000/02/23 02:56:53  steve
  *  Macintosh compilers do not support ident.
  *

PGate.cc

@@ -16,10 +16,12 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PGate.cc,v 1.9 2000/05/06 15:41:56 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PGate.cc,v 1.14 2002/08/12 01:34:58 steve Exp $"
 #endif
 
+# include "config.h"
+
 # include  "PGate.h"
 # include  "PExpr.h"
 # include  "verinum.h"
@@ -88,12 +90,12 @@ void PGate::elaborate_scope(Design*, NetScope*) const
  * parameters. This method understands how to handle the different
  * numbers of expressions.
  */
-void PGate::eval_delays(Design*des, const string&path,
+void PGate::eval_delays(Design*des, NetScope*scope,
 			unsigned long&rise_time,
 			unsigned long&fall_time,
 			unsigned long&decay_time) const
 {
-      delay_.eval_delays(des, path, rise_time, fall_time, decay_time);
+      delay_.eval_delays(des, scope, rise_time, fall_time, decay_time);
 }
 
 PGAssign::PGAssign(svector<PExpr*>*pins)
@@ -140,17 +142,24 @@ void PGBuiltin::set_range(PExpr*msb, PExpr*lsb)
       lsb_ = lsb;
 }
 
-PGModule::PGModule(const string&type, const string&name, svector<PExpr*>*pins)
-: PGate(name, pins), type_(type), overrides_(0), pins_(0),
+PGModule::PGModule(const char*type, const string&name, svector<PExpr*>*pins)
+: PGate(name, pins), overrides_(0), pins_(0),
   npins_(0), parms_(0), nparms_(0), msb_(0), lsb_(0)
 {
+      type_ = strdup(type);
 }
 
-PGModule::PGModule(const string&type, const string&name,
+PGModule::PGModule(const char*type, const string&name,
 		   named<PExpr*>*pins, unsigned npins)
-: PGate(name, 0), type_(type), overrides_(0), pins_(pins),
+: PGate(name, 0), overrides_(0), pins_(pins),
   npins_(npins), parms_(0), nparms_(0), msb_(0), lsb_(0)
 {
+      type_ = strdup(type);
+}
+
+PGModule::~PGModule()
+{
+      free(type_);
 }
 
 void PGModule::set_parameters(svector<PExpr*>*o)
@@ -176,8 +185,29 @@ void PGModule::set_range(PExpr*msb, PExpr*lsb)
       lsb_ = lsb;
 }
 
+const char* PGModule::get_type()
+{
+      return type_;
+}
+
 /*
  * $Log: PGate.cc,v $
+ * Revision 1.14  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.13  2001/11/22 06:20:59  steve
+ *  Use NetScope instead of string for scope path.
+ *
+ * Revision 1.12  2001/10/21 00:42:47  steve
+ *  Module types in pform are char* instead of string.
+ *
+ * Revision 1.11  2001/10/19 01:55:32  steve
+ *  Method to get the type_ member
+ *
+ * Revision 1.10  2001/07/25 03:10:48  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
  * Revision 1.9  2000/05/06 15:41:56  steve
  *  Carry assignment strength to pform.
  *

PGate.h

@@ -18,8 +18,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PGate.h,v 1.18 2000/05/06 15:41:56 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PGate.h,v 1.24 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include  "svector.h"
@@ -65,7 +65,7 @@ class PGate : public LineInfo {
 
       const string& get_name() const { return name_; }
 
-      void eval_delays(Design*des, const string&path,
+      void eval_delays(Design*des, NetScope*scope,
 		       unsigned long&rise_time,
 		       unsigned long&fall_time,
 		       unsigned long&decay_time) const;
@@ -79,10 +79,10 @@ class PGate : public LineInfo {
       void strength0(strength_t);
       void strength1(strength_t);
 
-      map<string,string> attributes;
+      map<string,PExpr*> attributes;
 
       virtual void dump(ostream&out) const;
-      virtual void elaborate(Design*des, const string&path) const;
+      virtual void elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*sc) const;
       virtual bool elaborate_sig(Design*des, NetScope*scope) const;
 
@@ -116,7 +116,7 @@ class PGAssign  : public PGate {
       ~PGAssign();
 
       void dump(ostream&out) const;
-      virtual void elaborate(Design*des, const string&path) const;
+      virtual void elaborate(Design*des, NetScope*scope) const;
 
     private:
 };
@@ -153,7 +153,7 @@ class PGBuiltin  : public PGate {
       void set_range(PExpr*msb, PExpr*lsb);
 
       virtual void dump(ostream&out) const;
-      virtual void elaborate(Design*, const string&path) const;
+      virtual void elaborate(Design*, NetScope*scope) const;
 
     private:
       Type type_;
@@ -173,15 +173,17 @@ class PGModule  : public PGate {
     public:
 	// If the binding of ports is by position, this constructor
 	// builds everything all at once.
-      explicit PGModule(const string&type, const string&name,
+      explicit PGModule(const char*type, const string&name,
 			svector<PExpr*>*pins);
 
 	// If the binding of ports is by name, this constructor takes
 	// the bindings and stores them for later elaboration.
-      explicit PGModule(const string&type, const string&name,
+      explicit PGModule(const char*type, const string&name,
 			named<PExpr*>*pins, unsigned npins);
 
 
+      ~PGModule();
+
 	// Parameter overrides can come as an ordered list, or a set
 	// of named expressions.
       void set_parameters(svector<PExpr*>*o);
@@ -192,12 +194,14 @@ class PGModule  : public PGate {
       void set_range(PExpr*msb, PExpr*lsb);
 
       virtual void dump(ostream&out) const;
-      virtual void elaborate(Design*, const string&path) const;
+      virtual void elaborate(Design*, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*sc) const;
       virtual bool elaborate_sig(Design*des, NetScope*scope) const;
 
+      const char* get_type();
+
     private:
-      string type_;
+      char* type_;
       svector<PExpr*>*overrides_;
       named<PExpr*>*pins_;
       unsigned npins_;
@@ -210,15 +214,37 @@ class PGModule  : public PGate {
       PExpr*msb_;
       PExpr*lsb_;
 
-      void elaborate_mod_(Design*, Module*mod, const string&path) const;
-      void elaborate_sudp_(Design*, PUdp  *udp, const string&path) const;
-      void elaborate_cudp_(Design*, PUdp  *udp, const string&path) const;
+      void elaborate_mod_(Design*, Module*mod, NetScope*scope) const;
+      void elaborate_udp_(Design*, PUdp  *udp, NetScope*scope) const;
       void elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const;
       bool elaborate_sig_mod_(Design*des, NetScope*scope, Module*mod) const;
 };
 
 /*
  * $Log: PGate.h,v $
+ * Revision 1.24  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.23  2002/05/23 03:08:51  steve
+ *  Add language support for Verilog-2001 attribute
+ *  syntax. Hook this support into existing $attribute
+ *  handling, and add number and void value types.
+ *
+ *  Add to the ivl_target API new functions for access
+ *  of complex attributes attached to gates.
+ *
+ * Revision 1.22  2001/11/22 06:20:59  steve
+ *  Use NetScope instead of string for scope path.
+ *
+ * Revision 1.21  2001/10/21 00:42:47  steve
+ *  Module types in pform are char* instead of string.
+ *
+ * Revision 1.20  2001/10/19 01:55:32  steve
+ *  Method to get the type_ member
+ *
+ * Revision 1.19  2001/04/22 23:09:45  steve
+ *  More UDP consolidation from Stephan Boettcher.
+ *
  * Revision 1.18  2000/05/06 15:41:56  steve
  *  Carry assignment strength to pform.
  *

PTask.cc

@@ -16,14 +16,16 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PTask.cc,v 1.3 2000/02/23 02:56:53 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PTask.cc,v 1.7 2002/08/12 01:34:58 steve Exp $"
 #endif
 
+# include "config.h"
+
 # include  "PTask.h"
 
-PTask::PTask(svector<PWire*>*p, Statement*s)
-: ports_(p), statement_(s)
+PTask::PTask()
+: ports_(0), statement_(0)
 {
 }
 
@@ -31,8 +33,34 @@ PTask::~PTask()
 {
 }
 
+void PTask::set_ports(svector<PWire*>*p)
+{
+      assert(ports_ == 0);
+      ports_ = p;
+}
+
+void PTask::set_statement(Statement*s)
+{
+      assert(statement_ == 0);
+      statement_ = s;
+}
+
+
 /*
  * $Log: PTask.cc,v $
+ * Revision 1.7  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.6  2001/07/25 03:10:48  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
+ * Revision 1.5  2001/04/19 03:04:47  steve
+ *  Spurious assert of empty statemnt.
+ *
+ * Revision 1.4  2001/01/13 22:20:08  steve
+ *  Parse parameters within nested scopes.
+ *
  * Revision 1.3  2000/02/23 02:56:53  steve
  *  Macintosh compilers do not support ident.
  *

PTask.h

@@ -18,8 +18,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PTask.h,v 1.8 2000/03/08 04:36:53 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PTask.h,v 1.12 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include  "LineInfo.h"
@@ -36,17 +36,23 @@ class Statement;
 class PTask  : public LineInfo {
 
     public:
-      explicit PTask(svector<PWire*>*p, Statement*s);
+      explicit PTask();
       ~PTask();
 
+      void set_ports(svector<PWire *>*p);
+      void set_statement(Statement *s);
+
 	// Tasks introduce scope, to need to be handled during the
 	// scope elaboration pass. The scope passed is my scope,
 	// created by the containing scope. I fill it in with stuff if
 	// I need to.
       void elaborate_scope(Design*des, NetScope*scope) const;
 
-      void elaborate_1(Design*des, const string&path) const;
-      void elaborate_2(Design*des, const string&path) const;
+	// Bind the ports to the regs that are the ports.
+      void elaborate_sig(Design*des, NetScope*scope) const;
+
+	// Elaborate the statement to finish off the task definition.
+      void elaborate(Design*des, NetScope*scope) const;
 
       void dump(ostream&, unsigned) const;
 
@@ -67,16 +73,20 @@ class PTask  : public LineInfo {
 class PFunction : public LineInfo {
 
     public:
-      explicit PFunction(svector<PWire *>*p, Statement *s);
+      explicit PFunction();
       ~PFunction();
 
+      void set_ports(svector<PWire *>*p);
+      void set_statement(Statement *s);
       void set_output(PWire*);
 
       void elaborate_scope(Design*des, NetScope*scope) const;
 
-	/* Functions are elaborated in 2 passes. */
-      void elaborate_1(Design *des, NetScope*) const;
-      void elaborate_2(Design *des, NetScope*) const;
+	/* elaborate the ports and return value. */
+      void elaborate_sig(Design *des, NetScope*) const;
+
+	/* Elaborate the behavioral statement. */
+      void elaborate(Design *des, NetScope*) const;
 
       void dump(ostream&, unsigned) const;
 
@@ -88,6 +98,22 @@ class PFunction : public LineInfo {
 
 /*
  * $Log: PTask.h,v $
+ * Revision 1.12  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.11  2001/11/22 06:20:59  steve
+ *  Use NetScope instead of string for scope path.
+ *
+ * Revision 1.10  2001/01/13 22:20:08  steve
+ *  Parse parameters within nested scopes.
+ *
+ * Revision 1.9  2000/07/30 18:25:43  steve
+ *  Rearrange task and function elaboration so that the
+ *  NetTaskDef and NetFuncDef functions are created during
+ *  signal enaboration, and carry these objects in the
+ *  NetScope class instead of the extra, useless map in
+ *  the Design class.
+ *
  * Revision 1.8  2000/03/08 04:36:53  steve
  *  Redesign the implementation of scopes and parameters.
  *  I now generate the scopes and notice the parameters

PUdp.h

@@ -18,8 +18,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PUdp.h,v 1.4 2000/02/23 02:56:53 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PUdp.h,v 1.7 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include  <map>
@@ -27,6 +27,8 @@
 # include  <string>
 # include  "verinum.h"
 
+class PExpr;
+
 svector<string>::svector<string>(unsigned size)
 : nitems_(size), items_(new string[size])
 {
@@ -68,12 +70,12 @@ class PUdp {
 
       verinum::V initial;
 
-      map<string,string> attributes;
+      map<string,PExpr*> attributes;
 
       void dump(ostream&out) const;
 
-    private:
       const string name_;
+    private:
 
     private: // Not implemented
       PUdp(const PUdp&);
@@ -82,6 +84,20 @@ class PUdp {
 
 /*
  * $Log: PUdp.h,v $
+ * Revision 1.7  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.6  2002/05/23 03:08:51  steve
+ *  Add language support for Verilog-2001 attribute
+ *  syntax. Hook this support into existing $attribute
+ *  handling, and add number and void value types.
+ *
+ *  Add to the ivl_target API new functions for access
+ *  of complex attributes attached to gates.
+ *
+ * Revision 1.5  2001/04/22 23:09:45  steve
+ *  More UDP consolidation from Stephan Boettcher.
+ *
  * Revision 1.4  2000/02/23 02:56:53  steve
  *  Macintosh compilers do not support ident.
  *

PWire.cc

@@ -16,16 +16,34 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PWire.cc,v 1.3 2000/02/23 02:56:54 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PWire.cc,v 1.10 2002/08/12 01:34:58 steve Exp $"
 #endif
 
+# include "config.h"
 # include  "PWire.h"
 # include  <assert.h>
 
-PWire::PWire(const string&n, NetNet::Type t, NetNet::PortType pt)
-: name_(n), type_(t), port_type_(pt), lidx_(0), ridx_(0)
+PWire::PWire(const hname_t&n, NetNet::Type t, NetNet::PortType pt)
+: hname_(n), type_(t), port_type_(pt), signed_(false), isint_(false),
+lidx_(0), ridx_(0)
 {
+      if (t == NetNet::INTEGER) {
+	    type_ = NetNet::REG;
+	    signed_ = true;
+	    isint_ = true;
+      }
+}
+
+PWire::PWire(char*n, NetNet::Type t, NetNet::PortType pt)
+: hname_(n), type_(t), port_type_(pt), signed_(false), isint_(false),
+lidx_(0), ridx_(0)
+{
+      if (t == NetNet::INTEGER) {
+	    type_ = NetNet::REG;
+	    signed_ = true;
+	    isint_ = true;
+      }
 }
 
 NetNet::Type PWire::get_wire_type() const
@@ -33,6 +51,11 @@ NetNet::Type PWire::get_wire_type() const
       return type_;
 }
 
+const hname_t& PWire::path() const
+{
+      return hname_;
+}
+
 bool PWire::set_wire_type(NetNet::Type t)
 {
       assert(t != NetNet::IMPLICIT);
@@ -43,11 +66,13 @@ bool PWire::set_wire_type(NetNet::Type t)
 	    return true;
 	  case NetNet::IMPLICIT_REG:
 	    if (t == NetNet::REG) { type_ = t; return true; }
-	    if (t == NetNet::INTEGER) {type_ = t; return true; }
 	    return false;
 	  case NetNet::REG:
+	    if (t == NetNet::INTEGER) {
+		  isint_ = true;
+		  return true;
+	    }
 	    if (t == NetNet::REG) return true;
-	    if (t == NetNet::INTEGER) {type_ = t; return true; }
 	    return false;
 	  default:
 	    if (type_ != t)
@@ -83,6 +108,21 @@ bool PWire::set_port_type(NetNet::PortType pt)
       }
 }
 
+void PWire::set_signed(bool flag)
+{
+      signed_ = flag;
+}
+
+bool PWire::get_signed() const
+{
+      return signed_;
+}
+
+bool PWire::get_isint() const
+{
+      return isint_;
+}
+
 void PWire::set_range(PExpr*m, PExpr*l)
 {
       msb_ = svector<PExpr*>(msb_,m);
@@ -93,13 +133,37 @@ void PWire::set_memory_idx(PExpr*ldx, PExpr*rdx)
 {
       assert(lidx_ == 0);
       assert(ridx_ == 0);
-      assert((type_ == NetNet::REG) || (type_ == NetNet::INTEGER));
+      assert(type_ == NetNet::REG);
       lidx_ = ldx;
       ridx_ = rdx;
 }
 
 /*
  * $Log: PWire.cc,v $
+ * Revision 1.10  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.9  2002/06/21 04:59:35  steve
+ *  Carry integerness throughout the compilation.
+ *
+ * Revision 1.8  2002/01/26 05:28:28  steve
+ *  Detect scalar/vector declarion mismatch.
+ *
+ * Revision 1.7  2001/12/03 04:47:14  steve
+ *  Parser and pform use hierarchical names as hname_t
+ *  objects instead of encoded strings.
+ *
+ * Revision 1.6  2001/07/25 03:10:48  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
+ * Revision 1.5  2001/01/06 02:29:35  steve
+ *  Support arrays of integers.
+ *
+ * Revision 1.4  2000/12/11 00:31:43  steve
+ *  Add support for signed reg variables,
+ *  simulate in t-vvm signed comparisons.
+ *
  * Revision 1.3  2000/02/23 02:56:54  steve
  *  Macintosh compilers do not support ident.
  *

PWire.h

@@ -18,15 +18,21 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PWire.h,v 1.8 2000/05/02 16:27:38 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PWire.h,v 1.14 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include  "netlist.h"
 # include  "LineInfo.h"
-# include <map>
+# include  <map>
 # include  "svector.h"
+
+#ifdef HAVE_IOSFWD
+# include  <iosfwd>
+#else
 class ostream;
+#endif
+
 class PExpr;
 class Design;
 
@@ -34,14 +40,21 @@ class Design;
  * Wires include nets, registers and ports. A net or register becomes
  * a port by declaration, so ports are not seperate. The module
  * identifies a port by keeping it in its port list.
+ *
+ * The hname parameter to the constructor is a hierarchical name. It
+ * is an array of strings starting with the root, running towards
+ * the base name, and terminated by a null pointer. The environment
+ * allocates the memory for me.
  */
 class PWire : public LineInfo {
 
     public:
-      PWire(const string&n, NetNet::Type t, NetNet::PortType pt);
+      PWire(const hname_t&hname, NetNet::Type t, NetNet::PortType pt);
+      PWire(char*name, NetNet::Type t, NetNet::PortType pt);
 
-
-      const string&name() const { return name_; }
+	// Return a hierarchical name.
+	//const string name() const;
+      const hname_t&path() const;
 
       NetNet::Type get_wire_type() const;
       bool set_wire_type(NetNet::Type);
@@ -49,11 +62,15 @@ class PWire : public LineInfo {
       NetNet::PortType get_port_type() const;
       bool set_port_type(NetNet::PortType);
 
+      void set_signed(bool flag);
+      bool get_signed() const;
+      bool get_isint() const;
+
       void set_range(PExpr*msb, PExpr*lsb);
 
       void set_memory_idx(PExpr*ldx, PExpr*rdx);
 
-      map<string,string> attributes;
+      map<string,PExpr*> attributes;
 
 	// Write myself to the specified stream.
       void dump(ostream&out) const;
@@ -61,9 +78,11 @@ class PWire : public LineInfo {
       void elaborate_sig(Design*, NetScope*scope) const;
 
     private:
-      string name_;
+      hname_t hname_;
       NetNet::Type type_;
       NetNet::PortType port_type_;
+      bool signed_;
+      bool isint_;		// original type of integer
 
 	// These members hold expressions for the bit width of the
 	// wire. If they do not exist, the wire is 1 bit wide.
@@ -82,6 +101,31 @@ class PWire : public LineInfo {
 
 /*
  * $Log: PWire.h,v $
+ * Revision 1.14  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.13  2002/06/21 04:59:35  steve
+ *  Carry integerness throughout the compilation.
+ *
+ * Revision 1.12  2002/05/23 03:08:51  steve
+ *  Add language support for Verilog-2001 attribute
+ *  syntax. Hook this support into existing $attribute
+ *  handling, and add number and void value types.
+ *
+ *  Add to the ivl_target API new functions for access
+ *  of complex attributes attached to gates.
+ *
+ * Revision 1.11  2001/12/03 04:47:14  steve
+ *  Parser and pform use hierarchical names as hname_t
+ *  objects instead of encoded strings.
+ *
+ * Revision 1.10  2001/01/16 02:44:18  steve
+ *  Use the iosfwd header if available.
+ *
+ * Revision 1.9  2000/12/11 00:31:43  steve
+ *  Add support for signed reg variables,
+ *  simulate in t-vvm signed comparisons.
+ *
  * Revision 1.8  2000/05/02 16:27:38  steve
  *  Move signal elaboration to a seperate pass.
  *

QUICK_START.txt

@@ -0,0 +1,83 @@
+
+* Getting Started with Icarus Verilog
+
+Icarus Verilog is a Verilog compiler. It is suitable for use as a
+simulator, and, to some degree, synthesizer. Icarus Verilog runs under
+Linux and a variety of UNIX systems, as well as Windows as a command
+line tool, so the instructions are generally applicable to all
+environments. Note that this is only a quick start. For more detailed
+documentation, see the manual page for the iverilog command.
+
+
+* Hello, World!
+
+The first thing you want to do as a user is learn how to compile and
+execute even the most trivial design. For the purposes of simulation,
+we use as our example *the* most trivial simulation:
+
+  module main;
+ 
+  initial 
+    begin
+      $display("Hello, World");
+      $finish ;
+    end
+
+  endmodule
+
+By a text editor (or copy hello.vl from the Icarus Verilog examples
+directory) arrange for this program to be in a text file, "hello.vl".
+Next, compile this program with a command like this:
+
+	% iverilog -o hello hello.vl
+
+The results of this compile are placed into the file "hello", as the
+"-o" flag tells the compiler where to place the compiled result. Next,
+execute the compiled program like so:
+
+	% vvp hello
+	Hello, World
+
+And there it is, the program has been executed. So what happened? The
+first step, the "iverilog" command, read and interpreted the source
+file, then generated a compiled result. The compiled form may be
+selected by command line switches, but the default form is the VVP
+format, which is actually run by the "vvp" command.
+
+The "iverilog" and "vvp" commands are the only commands that users
+use to invoke Icarus Verilog. What the compiler actually does is
+controlled by command line switches. In our little example, we asked
+the compiler to compile the source program to the default vvp form,
+which is in turn executed by the vvp program.
+
+
+* Windows Install
+
+The easiest way to install under Windows is to get a precompiled
+installer for the version you wish to install. Icarus Verilog is
+distributed for Windows users as a self-installing .exe. Just execute
+the installer and follow the instructions. During the install, take
+note of the directory where the program is installed: for example,
+C:\iverilog is a good place to install.
+
+Once the binary is installed, you need to add the bin directory to
+your execution path. The executables you need are in C:\iverilog\bin,
+where the "C:\iverilog" part is actually the root of where you
+installed the package. The programs are in the bin subdirectory. Put
+this directory in your PATH environment variable, and the above
+commands become accessible to you at the command line prompt, or even
+in batch files.
+
+
+* Linux Install
+
+Under Linux, the install is even easier. For RedHat and Mandrake based
+systems, there is the appropriate RPM file. Just install the package
+with the "rpm -U <file>" command. Debian users should get Icarus
+Verilog packages from the main Debian software site.
+
+
+* Install From Source
+
+In this case, see the readme and other documentation that comes with
+the source.

README.txt

@@ -1,22 +1,25 @@
 		THE ICARUS VERILOG COMPILATION SYSTEM 
-			   September 18, 1999		
+			   September 17, 2000	
 
 
 1.0 What is ICARUS Verilog?
 
-Icarus Verilog is intended to compile ALL of the Verilog HDL as described
-in the IEEE-1364 standard. Of course, it's not quite there yet. It does
-currently handle a mix of structural and behavioral constructs. For a
-view of the current state of Icarus Verilog, see its home page at
-<http://www.icarus.com/eda/verilog>.
+Icarus Verilog is intended to compile ALL of the Verilog HDL as
+described in the IEEE-1364 standard. Of course, it's not quite there
+yet. It does currently handle a mix of structural and behavioral
+constructs. For a view of the current state of Icarus Verilog, see its
+home page at <http://www.icarus.com/eda/verilog>.
  
 Icarus Verilog is not aimed at being a simulator in the traditional
 sense, but a compiler that generates code employed by back-end
-tools. These back- end tools currently include a simulator written in
-C++ called VVM and an XNF (Xilinx Netlist Format) generator. See
-"vvm.txt" and "xnf.txt" for further details on these back-end
-processors. In the future, backends are expected for EDIF/LPM,
-structural Verilog, etc.
+tools. These back-end tools currently include a simulator engine
+called VVP, an XNF (Xilinx Netlist Format) generator and an EDIF fpga
+netlist generator. In the future, backends are expected for EDIF/LPM,
+structural Verilog, VHDL, etc.
+
+    For instructions on how to run Icarus Verilog,
+    see the ``iverilog'' man page.
+
 
 2.0 Building/Installing Icarus Verilog From Source
 
@@ -26,22 +29,26 @@ system and C/C++ compilation should be able to build the source
 distribution with little effort. Some actual programming skills are
 not required, but helpful in case of problems.
 
+If you are building for Windows, see the mingw.txt file.
+
 2.1 Compile Time Prerequisites
 
 You need the following software to compile Icarus Verilog from source
 on a UNIX-like system:
 
 	- GNU Make
-	  The Makefiles use some GNU extensions to, so a basic POSIX
+	  The Makefiles use some GNU extensions, so a basic POSIX
 	  make will not work. Linux systems typically come with a
-	  satisfactory make.
+	  satisfactory make. BSD based systems (i.e., NetBSD, FreeBSD)
+	  typically have GNU make as the gmake program.
 
 	- ISO C++ Compiler
-	  The ivl and ivlpp programs are written in C++ and makes use
-	  of templates and some of the standard C++ library. egcs
-	  compilers with the associated libstdc++ are known to work.
+	  The ivl and ivlpp programs are written in C++ and make use
+	  of templates and some of the standard C++ library. egcs and
+	  recent gcc compilers with the associated libstdc++ are known
+	  to work. MSVC++ 5 and 6 are known to definitely *not* work.
 
-	- bison
+	- bison and flex
 
 	- gperf 2.7
 	  The lexical analyzer doesn't recognize keywords directly,
@@ -49,6 +56,9 @@ on a UNIX-like system:
 	  table in order to get the proper lexical code. The gperf
 	  program generates the lookup table.
 
+	  A version problem with this program is the most common cause
+	  of difficulty. See the Icarus Verilog FAQ.
+
 2.2 Compilation
 
 Unpack the tar-ball and cd into the verilog-######### directory
@@ -58,15 +68,48 @@ with the commands:
   ./configure
   make
 
-2.3 Installation
+Normally, this command automatically figures out every thing it needs
+to know. It generally works pretty well. There are a few flags to the
+configure script that modify its behavior:
+
+	--without-ipal
+	    This turns off support for Icarus PAL, whether ipal
+	    libraries are installed or not.
+
+	--prefix=<root>
+	    The default is /usr/local, which causes the tool suite to
+	    be compiled for install in /usr/local/bin,
+	    /usr/local/share/ivl, etc.
+
+	    I recommend that if you are configuring for precompiled
+	    binaries, use --prefix=/usr.  On Solaris systems, it is
+	    common to use --prefix=/opt.  You can configure for a non-root
+	    install with --prefix=$HOME.
+
+2.3 (Optional) Testing
+
+To run a simple test before installation, execute
+
+  make check
+
+The commands printed by this run might help you in running Icarus
+Verilog on your own Verilog sources before the package is installed
+by root.
+
+2.4 Installation
 
 Now install the files in an appropriate place. (The makefiles by
 default install in /usr/local unless you specify a different prefix
-with the --prefix=<path> flag to the configure command.) Do this as
-root.
+with the --prefix=<path> flag to the configure command.) You may need
+to do this as root to gain access to installation directories.
 
   make install
 
+2.5 Uninstallation
+
+The generated Makefiles also include the uninstall target. This should
+remove all the files that ``make install'' creates.
+
 3.0 How Icarus Verilog Works
 
 This tool includes a parser which reads in Verilog (plus extensions)
@@ -86,15 +129,15 @@ only sees a single input file. See ivlpp/ivlpp.txt for details.
 
 3.2 Parse
 
-The verilog compiler starts by parsing the verilog source file. The
+The Verilog compiler starts by parsing the Verilog source file. The
 output of the parse in a list of Module objects in PFORM. The pform
 (see pform.h) is mostly a direct reflection of the compilation
 step. There may be dangling references, and it is not yet clear which
 module is the root.
 
 One can see a human readable version of the final PFORM by using the
-``-P <path>'' flag to the compiler. This will cause ivl to dump the
-PFORM into the file named <path>.
+``-P <path>'' flag to the compiler. This will cause iverilog to dump
+the PFORM into the file named <path>.
 
 3.3 Elaboration
 
@@ -102,16 +145,17 @@ This phase takes the pform and generates a netlist. The driver selects
 (by user request or lucky guess) the root module to elaborate,
 resolves references and expands the instantiations to form the design
 netlist. (See netlist.txt.) Final semantic checks are performed during
-elaboration, and some simple optimizations are performed.
+elaboration, and some simple optimizations are performed. The netlist
+includes all the behavioral descriptions, as well as gates and wires.
 
 The elaborate() function performs the elaboration.
 
 One can see a human readable version of the final, elaborated and
 optimized netlist by using the ``-N <path>'' flag to the compiler. If
-elaboration succeeds, the final netlist (i.e. after optimizations but
+elaboration succeeds, the final netlist (i.e., after optimizations but
 before code generation) will be dumped into the file named <path>.
 
-Elaboration is actually performed it two steps: scopes and parameters
+Elaboration is actually performed in two steps: scopes and parameters
 first, followed by the structural and behavioral elaboration.
 
 3.3.1 Scope Elaboration
@@ -140,108 +184,34 @@ simply passing through the pform.
 
 This is actually a collection of processing steps that perform
 optimizations that do not depend on the target technology. Examples of
-some useful transformations would be,
+some useful transformations are
 
-	- eliminate null effect circuitry,
+	- eliminate null effect circuitry
 	- combinational reduction
-	- Constant propagation
+	- constant propagation
 
-The actual functions performed are specified on the command line by
-the -F flags (See below).
+The actual functions performed are specified on the ivl command line by
+the -F flags (see below).
 
 3.5 Code Generation
 
 This step takes the design netlist and uses it to drive the code
-generator. (See target.h.) This may require transforming the
+generator (see target.h). This may require transforming the
 design to suit the technology.
 
 The emit() method of the Design class performs this step. It runs
 through the design elements, calling target functions as need arises
 to generate actual output.
 
-The target code generator to used is given by the -t flag on the
+The user selects the target code generator with the -t flag on the
 command line.
 
-4.0 Running Verilog
+3.6 ATTRIBUTES
 
-The preferred way to invoke the compiler with the iverilog(1)
-command. This program invokes the preprocessor (ivlpp) and the
-compiler (ivl) with the proper command line options to get the job
-done in a friendly way. See the iverilog(1) man page for usage details.
+    NOTE: The $attribute syntax will soon be deprecated in favor of the
+    Verilog-2001 attribute syntax, which is cleaner and standardized.
 
-4.1 Running IVL Directly
-
-The ivl command is the compiler driver, that invokes the parser,
-optimization functions and the code generator, but not the preprocessor.
-
-Usage: ivl <options>... file
-       ivl -h
-
--F <name>
-	Use this flag to request an optimization function be applied
-	to the netlist before it is sent to the target output
-	stage. Any number of -F options may be given, to specify a
-	variety of processing steps. The steps will be applied in
-	order, with the output of one uses as the input to the next.
-
-	The function is specified by name. Use the "ivl -h" command to
-	get a list of configured function names.
-
--f <assign>
-	Use this flag to set a parameter value. The format of the
-	assignment is <key>=<value> where key is any string up to the
-	first '=', and <value> is the rest of the option. If the '='
-	is omitted, then the key is assigned the empty string.
-
-	The useful keys are defined by the functions and the target in
-	use. These assignments are specifically useful for passing
-	target specific information to the target back-end, or
-	options/parameters to optimization functions, if any are defined.
-
--m <module>
-	Cause a named VPI module to be included in the module
-	list. This parameter appends the named module to the end of
-	the VPI_MODULE_LIST. This is an ordered list of modules to be
-	loaded into the simulation at runtime.
-
-	This list can also be set with -fVPI_MODULE_LIST=<list> which
-	sets the list completely. Then, -m after this will append
-	module names to the list sp specified. The default list
-	includes "system".
-
--N <file>
-	Dump the elaborated netlist to the named file. The netlist is
-	the folly elaborated netlist, after all the function modules
-	are applied and right before the output generator is
-	called. This is an aid for debugging the compiler, and the
-	output generator in particular.
-
--o <file>
-	Normally, the generated result is sent to standard
-	output. Use the -o flag to specify an output file for the
-	generated result.
-
--P <file>
-	Write the PForm of the parsed input to the specified file.
-	The pform is the compiler's understanding of the input after
-	parsing and before elaboration. This is an aid for debugging
-	the compiler.
-
--s <module>
-	Normally, ivl will elaborate the only module in the source
-	file. If there are multiple modules, use this option to select
-	the module to be used as the top-level module.
-
--t <name>
-	Select the output format for the compiled result. Use the
-	"ivl -h" command to get a list of configured targets.
-
--v
-	Print version and copyright information for ivl.
-
-ATTRIBUTES
-
-The parser accepts as an extension to Verilog the $attribute module
+The parser accepts, as an extension to Verilog, the $attribute module
 item. The syntax of the $attribute item is:
 
 	$attribute (<identifier>, <key>, <value>);
@@ -269,6 +239,19 @@ between processing steps. Processing steps that are aware of others
 may place attributes on netlist objects to communicate information to
 later steps.
 
+Icarus Verilog also accepts the Verilog 2001 syntax for
+attributes. They have the same general meaning as with the $attribute
+syntax, but they are attached to objects by position instead of by
+name. Also, the key is a Verilog identifier instead of a string.
+
+4.0 Running iverilog
+
+The preferred way to invoke the compiler is with the iverilog(1)
+command. This program invokes the preprocessor (ivlpp) and the
+compiler (ivl) with the proper command line options to get the job
+done in a friendly way. See the iverilog(1) man page for usage details.
+
+
 4.1 EXAMPLES
 
 Example: Compiling "hello.vl"
@@ -286,65 +269,151 @@ endmodule
 
 --------------------------------------------------------------
 
-Insure that "iverilog" is on your search path, and the vpi library 
+Ensure that "iverilog" is on your search path, and the vpi library 
 is available.
 
-For csh - 
+To compile the program:
 
   iverilog hello.vl
 
 (The above presumes that /usr/local/include and /usr/local/lib are
 part of the compiler search path, which is usually the case for gcc.)
 
-To run the program
+To run the program:
 
   ./a.out
 
+You can use the "-o" switch to name the output command to be generated
+by the compiler. See the iverilog(1) man page.
 
 5.0 Unsupported Constructs
 
-IVL is in development - as such it still only supports a (growing) subset
-of Verilog.  Below is a description of some of the currently unsupported
-verilog features. This list is not exhaustive, and does not account
-for errors in the compiler. See the Icarus Verilog web page for the
-current state of support for Verilog.
+Icarus Verilog is in development - as such it still only supports a
+(growing) subset of Verilog.  Below is a description of some of the
+currently unsupported Verilog features. This list is not exhaustive,
+and does not account for errors in the compiler. See the Icarus
+Verilog web page for the current state of support for Verilog, and in
+particular, browse the bug report database for reported unsupported
+constructs.
 
-  - Min/Typ/Max expressions: Example:  a = (1 : 6 : 14);
-
-  - `timescale directive
-
-  - block disable not supported, i.e.:
-
-            begin : foo
-	        [...]
-		disable foo; // sorry
-		[...]
-	    end
-
-  - Functions in structural contexts are not supported.
-
-            assign foo = user_function(a,b); // sorry
-	    always @(a or b) foo = user_function(a,b); // OK
-
-  - real data type not supported.
+  - real data types not supported. This includes real and
+    realtime. However, floating point constants in delay expressions
+    are supported so that `timescale works properly.
 
   - System functions are supported, but the compiler presumes that
     they return 32 bits. This is the typical case.
 
-  - non-constant delay expressions, i.e.:
-
-            reg [7:0] del;
-	    always #(reg) $display($time,,"del = %d", del); // sorry
-
   - Specify blocks are parsed but ignored in general.
 
+  - trireg is not supported. tri0 and tri1 are supported.
+
+  - tran primitives, i.e. tran, tranif1, tranif0, rtran, rtranif1
+    and rtranif0 are not supported.
+
+  - Module instance arrays are not supported, although gate instance
+    arrays do work.
+
+  - Net delays, of the form "wire #N foo;" do not work. Delays in
+    every other context do work properly, including the V2001 form
+    "wire #5 foo = bar;"
+
+  - Event controls inside non-blocking assignments are not supported.
+    i.e.: a <= @(posedge clk) b;
+
+  - Lists of named events of the form @(event_1 or event_2) are not
+    supported. Named events are otherwise supported, and lists of
+    other kinds of events are also supported.
+
+  - Macro arguments are not supported. `define macros are supported,
+    but they cannot take arguments.
+
+5.1 Nonstandard Constructs or Behaviors
+
+Icarus Verilog includes some features that are not part of the
+IEEE1364 standard, but have well defined meaning, and also sometimes
+gives nonstandard (but extended) meanings to some features of the
+language that are defined.
+
+    $sizeof(<expr>)
+    $bits(<expr>)
+	The $bits system function returns the size in bits of the
+	expression that is its argument. The result of this
+	function is undefined if the argument doesn't have a
+	self-determined size.
+
+	The $sizeof function is deprecated in favor of $bits, which is
+	the same thing, but included in the SystemVerilog definition.
+
+    Builtin system functions
+
+	Certain of the system functions have well defined meanings, so
+	can theoretically be evaluated at compile time, instead of
+	using runtime VPI code. Doing so means that VPI cannot
+	override the definitions of functions handled in this
+	manner. On the other hand, this makes them synthesizeable, and
+	also allows for more aggressive constant propagation. The
+	functions handled in this manner are:
+
+		$bits
+		$signed
+		$sizeof
+		$unsigned
+
+	Implementations of these system functions in VPI modules will
+	be ignored.
+
+    Preprocessing Library Modules
+
+	Icarus Verilog does preprocess modules that are loaded from
+	libraries via the -y mechanism. However, the only macros
+	defined during compilation of that file are those that it
+	defines itself (or includes) or that are defined on the
+	command line or command file.
+
+	Specifically, macros defined in the non-library source files
+	are not remembered when the library module is loaded. This is
+	intentional. If it were otherwise, then compilation results
+	might vary depending on the order that libraries are loaded,
+	and that is too unpredictable.
+
+	It is said that some commercial compilers do allow macro
+	definitions to span library modules. That's just plain weird.
+
+    Width in %t Time Formats
+
+	Standard Verilog does not allow width fields in the %t formats
+	of display strings. For example, this is illegal:
+
+		$display("Time is %0t", %time);
+
+	Standard Verilog instead relies on the $timeformat to
+	completely specify the format.
+
+	Icarus Verilog allows the programmer to specify the field
+	with. The "%t" format in Icarus Verilog works exactly as it
+	does in standard Verilog. However, if the programmer chooses
+	to specify a minimum width (i.e., "%5t"), then for that display
+	Icarus Verilog will override the $timeformat minimum width and
+	use the explicit minimum width.
+
+    vpiScope iterator on vpiScope objects.
+
+	In the VPI, the normal way to iterate over vpiScope objects
+	contained within a vpiScope object, is the vpiInternalScope
+	iterator. Icarus Verilog adds support for the vpiScope
+	iterator of a vpiScope object, that iterates over *everything*
+	the is contained in the current scope. This is useful in cases
+	where one wants to iterate over all the objects in a scope
+	without iterating over all the contained types explicitly.
+
 
 6.0 CREDITS
 
-Except where otherwise noted, ivl and ivlpp are Copyright Stephen
-Williams. The proper notices are in the head of each file. However,
-I have received aid in the form of fixes, Verilog guidance, and
-especially testing from many people, including (in alphabetical order):
+Except where otherwise noted, Icarus Verilog, ivl and ivlpp are
+Copyright Stephen Williams. The proper notices are in the head of each
+file. However, I have early on received aid in the form of fixes,
+Verilog guidance, and especially testing from many people, including
+(in alphabetical order):
 
 	Eric Aardoom <[email protected]>
 	Stephan I. Boettcher <[email protected]>
@@ -352,17 +421,71 @@ especially testing from many people, including (in alphabetical order):
 	Larry Doolittle <[email protected]>
 	Guy Hutchison <[email protected]>
 	Ales Hvezda <[email protected]>
-	Yasuhisa Kato <ykato@mac.com>
-        James Lee <[email protected]>
+	Venkat Iyer <venkat@comit.com>
+	Yasuhisa Kato <[email protected]>
+        James Lee <[email protected]>
 	Peter Monta <[email protected]>
 	Daniel H. Nelsen <[email protected]>
 	Stefan Petersen <[email protected]>
+	Michael Ruff <[email protected]>
+	Mike Runyan <[email protected]>
 	Jason Schonberg <[email protected]>
 	Stuart Sutherland <[email protected]>
 	Stephen Tell <[email protected]>
         Stefan Theide <[email protected]>
+	Tom Verbeure
 	Steve Wilson <[email protected]>
 
 and others. Testers in particular include a larger community of people
 interested in a GPL Verilog for Linux. Special thanks to Steve Wilson
 for collecting and organizing the test suite code for all those testers.
+
+
+6.1 PORT MAINTAINERS
+
+This is a list of people who have created ports and precompiled
+packages for various operating systems. These folks have graciously
+taken on the task of building Icarus Verilog on their systems and
+bundled it into neat packages.(+) If you want to be added to the list (or
+removed from the list) send e-mail to me.
+
+      FreeBSD/{Intel,alpha}
+	Ying-Chieh Liao <[email protected]>
+
+      Linux/{alpha,Intel} (RPMS)
+	Stephen Williams <[email protected]>
+
+      Linux/* (.debs)
+	Hamish Moffatt <[email protected]>
+
+      Macintosh -- MacO/S
+	Yasuhisa Kato <[email protected]>
+
+      Mac O/S X
+        Timothy J. Wood <[email protected]>
+
+      NetBSD/*
+	Dan McMahill <[email protected]>
+
+      Solaris/SPARC packages (.pkg)
+	Dan McMahill <[email protected]>
+
+      Cygwin32/*
+        Venkat Iyer <[email protected]>
+
+      Mingw32
+        Venkat Iyer <[email protected]>
+
+(+) These are not the only systems where Icarus Verilog has been run,
+just the systems where precompiled binaries are publicly available.
+
+
+6.2 TEST SUITE MANAGER
+
+Steve Wilson <[email protected]> has taken on the large task of managing
+the test suite. He has maintained the regression test scripts, the
+driver list, received submissions from myself and others, and has
+written a great many tests on his own. Any compiler writer, for any
+language, will tell you that the test suite is at least as important
+as the compiler code itself.
+

Statement.cc

@@ -16,10 +16,12 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: Statement.cc,v 1.21 2000/05/11 23:37:26 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: Statement.cc,v 1.28 2002/08/12 01:34:58 steve Exp $"
 #endif
 
+# include "config.h"
+
 # include  "Statement.h"
 # include  "PExpr.h"
 
@@ -30,17 +32,19 @@ Statement::~Statement()
 PAssign_::PAssign_(PExpr*lval, PExpr*ex)
 : event_(0), lval_(lval), rval_(ex)
 {
+      delay_ = 0;
 }
 
 PAssign_::PAssign_(PExpr*lval, PExpr*de, PExpr*ex)
 : event_(0), lval_(lval), rval_(ex)
 {
-      if (de) delay_.set_delay(de);
+      delay_ = de;
 }
 
 PAssign_::PAssign_(PExpr*lval, PEventStatement*ev, PExpr*ex)
 : event_(ev), lval_(lval), rval_(ex)
 {
+      delay_ = 0;
 }
 
 PAssign_::~PAssign_()
@@ -103,11 +107,20 @@ PBlock::~PBlock()
 	    delete list_[idx];
 }
 
-PCallTask::PCallTask(const string&n, const svector<PExpr*>&p)
-: name_(n), parms_(p)
+PCallTask::PCallTask(const hname_t&n, const svector<PExpr*>&p)
+: path_(n), parms_(p)
 {
 }
 
+PCallTask::~PCallTask()
+{
+}
+
+const hname_t& PCallTask::path() const
+{
+      return path_;
+}
+
 PCase::PCase(NetCase::TYPE t, PExpr*ex, svector<PCase::Item*>*l)
 : type_(t), expr_(ex), items_(l)
 {
@@ -165,10 +178,19 @@ PDelayStatement::~PDelayStatement()
 {
 }
 
+PDisable::PDisable(const hname_t&sc)
+: scope_(sc)
+{
+}
+
+PDisable::~PDisable()
+{
+}
 
 PEventStatement::PEventStatement(const svector<PEEvent*>&ee)
 : expr_(ee), statement_(0)
 {
+      assert(expr_.count() > 0);
 }
 
 
@@ -178,6 +200,11 @@ PEventStatement::PEventStatement(PEEvent*ee)
       expr_[0] = ee;
 }
 
+PEventStatement::PEventStatement(void)
+: statement_(0)
+{
+}
+
 PEventStatement::~PEventStatement()
 {
 	// delete the events and the statement?
@@ -209,6 +236,17 @@ PForever::~PForever()
       delete statement_;
 }
 
+PForStatement::PForStatement(PExpr*n1, PExpr*e1, PExpr*cond,
+			     PExpr*n2, PExpr*e2, Statement*st)
+: name1_(n1), expr1_(e1), cond_(cond), name2_(n2), expr2_(e2),
+  statement_(st)
+{
+}
+
+PForStatement::~PForStatement()
+{
+}
+
 PProcess::~PProcess()
 {
       delete statement_;
@@ -235,7 +273,7 @@ PRepeat::~PRepeat()
       delete statement_;
 }
 
-PTrigger::PTrigger(const string&e)
+PTrigger::PTrigger(const hname_t&e)
 : event_(e)
 {
 }
@@ -244,6 +282,11 @@ PTrigger::~PTrigger()
 {
 }
 
+PWhile::PWhile(PExpr*e1, Statement*st)
+: cond_(e1), statement_(st)
+{
+}
+
 PWhile::~PWhile()
 {
       delete cond_;
@@ -252,102 +295,28 @@ PWhile::~PWhile()
 
 /*
  * $Log: Statement.cc,v $
- * Revision 1.21  2000/05/11 23:37:26  steve
- *  Add support for procedural continuous assignment.
+ * Revision 1.28  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
  *
- * Revision 1.20  2000/04/22 04:20:19  steve
- *  Add support for force assignment.
+ * Revision 1.27  2002/04/21 22:31:02  steve
+ *  Redo handling of assignment internal delays.
+ *  Leave it possible for them to be calculated
+ *  at run time.
  *
- * Revision 1.19  2000/04/12 04:23:57  steve
- *  Named events really should be expressed with PEIdent
- *  objects in the pform,
+ * Revision 1.26  2002/04/21 04:59:07  steve
+ *  Add support for conbinational events by finding
+ *  the inputs to expressions and some statements.
+ *  Get case and assignment statements working.
  *
- *  Handle named events within the mix of net events
- *  and edges. As a unified lot they get caught together.
- *  wait statements are broken into more complex statements
- *  that include a conditional.
+ * Revision 1.25  2001/12/03 04:47:14  steve
+ *  Parser and pform use hierarchical names as hname_t
+ *  objects instead of encoded strings.
  *
- *  Do not generate NetPEvent or NetNEvent objects in
- *  elaboration. NetEvent, NetEvWait and NetEvProbe
- *  take over those functions in the netlist.
- *
- * Revision 1.18  2000/04/01 19:31:57  steve
- *  Named events as far as the pform.
- *
- * Revision 1.17  2000/02/23 02:56:54  steve
- *  Macintosh compilers do not support ident.
- *
- * Revision 1.16  1999/09/29 18:36:02  steve
- *  Full case support
- *
- * Revision 1.15  1999/09/22 02:00:48  steve
- *  assignment with blocking event delay.
- *
- * Revision 1.14  1999/09/04 19:11:46  steve
- *  Add support for delayed non-blocking assignments.
- *
- * Revision 1.13  1999/09/02 01:59:27  steve
- *  Parse non-blocking assignment delays.
- *
- * Revision 1.12  1999/07/12 00:59:36  steve
- *  procedural blocking assignment delays.
- *
- * Revision 1.11  1999/06/24 04:24:18  steve
- *  Handle expression widths for EEE and NEE operators,
- *  add named blocks and scope handling,
- *  add registers declared in named blocks.
- *
- * Revision 1.10  1999/06/19 21:06:16  steve
- *  Elaborate and supprort to vvm the forever
- *  and repeat statements.
- *
- * Revision 1.9  1999/06/15 05:38:39  steve
- *  Support case expression lists.
- *
- * Revision 1.8  1999/06/13 23:51:16  steve
- *  l-value part select for procedural assignments.
- *
- * Revision 1.7  1999/06/06 20:45:38  steve
- *  Add parse and elaboration of non-blocking assignments,
- *  Replace list<PCase::Item*> with an svector version,
- *  Add integer support.
- *
- * Revision 1.6  1999/05/10 00:16:58  steve
- *  Parse and elaborate the concatenate operator
- *  in structural contexts, Replace vector<PExpr*>
- *  and list<PExpr*> with svector<PExpr*>, evaluate
- *  constant expressions with parameters, handle
- *  memories as lvalues.
- *
- *  Parse task declarations, integer types.
- *
- * Revision 1.5  1999/02/03 04:20:11  steve
- *  Parse and elaborate the Verilog CASE statement.
- *
- * Revision 1.4  1999/01/25 05:45:56  steve
- *  Add the LineInfo class to carry the source file
- *  location of things. PGate, Statement and PProcess.
- *
- *  elaborate handles module parameter mismatches,
- *  missing or incorrect lvalues for procedural
- *  assignment, and errors are propogated to the
- *  top of the elaboration call tree.
- *
- *  Attach line numbers to processes, gates and
- *  assignment statements.
- *
- * Revision 1.3  1998/11/11 03:13:04  steve
- *  Handle while loops.
- *
- * Revision 1.2  1998/11/07 17:05:05  steve
- *  Handle procedural conditional, and some
- *  of the conditional expressions.
- *
- *  Elaborate signals and identifiers differently,
- *  allowing the netlist to hold signal information.
- *
- * Revision 1.1  1998/11/03 23:28:55  steve
- *  Introduce verilog to CVS.
+ * Revision 1.24  2001/11/22 06:20:59  steve
+ *  Use NetScope instead of string for scope path.
  *
+ * Revision 1.23  2001/07/25 03:10:48  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
  */
 

Statement.h

@@ -18,19 +18,21 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: Statement.h,v 1.26 2000/05/11 23:37:26 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: Statement.h,v 1.36 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include  <string>
 # include  "svector.h"
 # include  "PDelays.h"
 # include  "PExpr.h"
+# include  "HName.h"
 # include  "LineInfo.h"
 class PExpr;
 class Statement;
 class PEventStatement;
 class Design;
+class NetAssign_;
 class NetCAssign;
 class NetDeassign;
 class NetScope;
@@ -54,6 +56,8 @@ class PProcess : public LineInfo {
       Type type() const { return type_; }
       Statement*statement() { return statement_; }
 
+      map<string,PExpr*> attributes;
+
       virtual void dump(ostream&out, unsigned ind) const;
 
     private:
@@ -73,7 +77,7 @@ class Statement : public LineInfo {
       virtual ~Statement() =0;
 
       virtual void dump(ostream&out, unsigned ind) const;
-      virtual NetProc* elaborate(Design*des, const string&path) const;
+      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
 };
 
@@ -93,11 +97,9 @@ class PAssign_  : public Statement {
       const PExpr* rval() const  { return rval_; }
 
     protected:
-      NetNet*elaborate_lval(Design*, const string&path,
-			    unsigned&lsb, unsigned&msb,
-			    NetExpr*&mux) const;
+      NetAssign_* elaborate_lval(Design*, NetScope*scope) const;
 
-      PDelays delay_;
+      PExpr* delay_;
       PEventStatement*event_;
 
     private:
@@ -114,11 +116,9 @@ class PAssign  : public PAssign_ {
       ~PAssign();
 
       virtual void dump(ostream&out, unsigned ind) const;
-      virtual NetProc* elaborate(Design*des, const string&path) const;
+      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
 
     private:
-      NetProc*assign_to_memory_(class NetMemory*, PExpr*,
-				Design*des, const string&path) const;
 };
 
 class PAssignNB  : public PAssign_ {
@@ -129,11 +129,11 @@ class PAssignNB  : public PAssign_ {
       ~PAssignNB();
 
       virtual void dump(ostream&out, unsigned ind) const;
-      virtual NetProc* elaborate(Design*des, const string&path) const;
+      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
 
     private:
       NetProc*assign_to_memory_(class NetMemory*, PExpr*,
-				Design*des, const string&path) const;
+				Design*des, NetScope*scope) const;
 };
 
 /*
@@ -155,11 +155,9 @@ class PBlock  : public Statement {
 
       BL_TYPE bl_type() const { return bl_type_; }
 
-	//unsigned size() const { return list_.count(); }
-	//const Statement*stat(unsigned idx) const { return list_[idx]; }
 
       virtual void dump(ostream&out, unsigned ind) const;
-      virtual NetProc* elaborate(Design*des, const string&path) const;
+      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
 
     private:
@@ -171,9 +169,10 @@ class PBlock  : public Statement {
 class PCallTask  : public Statement {
 
     public:
-      explicit PCallTask(const string&n, const svector<PExpr*>&parms);
+      explicit PCallTask(const hname_t&n, const svector<PExpr*>&parms);
+      ~PCallTask();
 
-      string name() const { return name_; }
+      const hname_t& path() const;
 
       unsigned nparms() const { return parms_.count(); }
 
@@ -188,13 +187,13 @@ class PCallTask  : public Statement {
 	    }
 
       virtual void dump(ostream&out, unsigned ind) const;
-      virtual NetProc* elaborate(Design*des, const string&path) const;
+      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
 
     private:
-      NetProc* elaborate_sys(Design*des, const string&path) const;
-      NetProc* elaborate_usr(Design*des, const string&path) const;
+      NetProc* elaborate_sys(Design*des, NetScope*scope) const;
+      NetProc* elaborate_usr(Design*des, NetScope*scope) const;
 
-      const string name_;
+      hname_t path_;
       svector<PExpr*> parms_;
 };
 
@@ -209,7 +208,7 @@ class PCase  : public Statement {
       PCase(NetCase::TYPE, PExpr*ex, svector<Item*>*);
       ~PCase();
 
-      virtual NetProc* elaborate(Design*des, const string&path) const;
+      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
       virtual void dump(ostream&out, unsigned ind) const;
 
@@ -230,7 +229,7 @@ class PCAssign  : public Statement {
       explicit PCAssign(PExpr*l, PExpr*r);
       ~PCAssign();
 
-      virtual NetCAssign* elaborate(Design*des, const string&path) const;
+      virtual NetCAssign* elaborate(Design*des, NetScope*scope) const;
       virtual void dump(ostream&out, unsigned ind) const;
 
     private:
@@ -244,7 +243,7 @@ class PCondit  : public Statement {
       PCondit(PExpr*ex, Statement*i, Statement*e);
       ~PCondit();
 
-      virtual NetProc* elaborate(Design*des, const string&path) const;
+      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
       virtual void dump(ostream&out, unsigned ind) const;
 
@@ -264,7 +263,7 @@ class PDeassign  : public Statement {
       explicit PDeassign(PExpr*l);
       ~PDeassign();
 
-      virtual NetDeassign* elaborate(Design*des, const string&path) const;
+      virtual NetDeassign* elaborate(Design*des, NetScope*scope) const;
       virtual void dump(ostream&out, unsigned ind) const;
 
     private:
@@ -278,7 +277,7 @@ class PDelayStatement  : public Statement {
       ~PDelayStatement();
 
       virtual void dump(ostream&out, unsigned ind) const;
-      virtual NetProc* elaborate(Design*des, const string&path) const;
+      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
 
     private:
@@ -286,12 +285,30 @@ class PDelayStatement  : public Statement {
       Statement*statement_;
 };
 
+
+/*
+ * This represends the parsing of a disable <scope> statement.
+ */
+class PDisable  : public Statement {
+
+    public:
+      explicit PDisable(const hname_t&sc);
+      ~PDisable();
+
+      virtual void dump(ostream&out, unsigned ind) const;
+      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
+
+    private:
+      hname_t scope_;
+};
+
 /*
  * The event statement represents the event delay in behavioral
  * code. It comes from such things as:
  *
  *      @name <statement>;
  *      @(expr) <statement>;
+ *      @* <statement>;
  */
 class PEventStatement  : public Statement {
 
@@ -299,18 +316,20 @@ class PEventStatement  : public Statement {
 
       explicit PEventStatement(const svector<PEEvent*>&ee);
       explicit PEventStatement(PEEvent*ee);
+	// Make an @* statement.
+      explicit PEventStatement(void);
 
       ~PEventStatement();
 
       void set_statement(Statement*st);
 
       virtual void dump(ostream&out, unsigned ind) const;
-      virtual NetProc* elaborate(Design*des, const string&path) const;
+      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
 
 	// This method is used to elaborate, but attach a previously
 	// elaborated statement to the event.
-      NetProc* elaborate_st(Design*des, const string&path, NetProc*st) const;
+      NetProc* elaborate_st(Design*des, NetScope*scope, NetProc*st) const;
 
     private:
       svector<PEEvent*>expr_;
@@ -323,7 +342,7 @@ class PForce  : public Statement {
       explicit PForce(PExpr*l, PExpr*r);
       ~PForce();
 
-      virtual NetProc* elaborate(Design*des, const string&path) const;
+      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void dump(ostream&out, unsigned ind) const;
 
     private:
@@ -336,7 +355,7 @@ class PForever : public Statement {
       explicit PForever(Statement*s);
       ~PForever();
 
-      virtual NetProc* elaborate(Design*des, const string&path) const;
+      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
       virtual void dump(ostream&out, unsigned ind) const;
 
@@ -348,12 +367,10 @@ class PForStatement  : public Statement {
 
     public:
       PForStatement(PExpr*n1, PExpr*e1, PExpr*cond,
-		    PExpr*n2, PExpr*e2, Statement*st)
-      : name1_(n1), expr1_(e1), cond_(cond), name2_(n2), expr2_(e2),
-	statement_(st)
-      { }
+		    PExpr*n2, PExpr*e2, Statement*st);
+      ~PForStatement();
 
-      virtual NetProc* elaborate(Design*des, const string&path) const;
+      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
       virtual void dump(ostream&out, unsigned ind) const;
 
@@ -380,7 +397,7 @@ class PRepeat : public Statement {
       explicit PRepeat(PExpr*expr, Statement*s);
       ~PRepeat();
 
-      virtual NetProc* elaborate(Design*des, const string&path) const;
+      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
       virtual void dump(ostream&out, unsigned ind) const;
 
@@ -395,7 +412,7 @@ class PRelease  : public Statement {
       explicit PRelease(PExpr*l);
       ~PRelease();
 
-      virtual NetProc* elaborate(Design*des, const string&path) const;
+      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void dump(ostream&out, unsigned ind) const;
 
     private:
@@ -409,24 +426,23 @@ class PRelease  : public Statement {
 class PTrigger  : public Statement {
 
     public:
-      explicit PTrigger(const string&ev);
+      explicit PTrigger(const hname_t&ev);
       ~PTrigger();
 
-      virtual NetProc* elaborate(Design*des, const string&path) const;
+      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void dump(ostream&out, unsigned ind) const;
 
     private:
-      string event_;
+      hname_t event_;
 };
 
 class PWhile  : public Statement {
 
     public:
-      PWhile(PExpr*e1, Statement*st)
-      : cond_(e1), statement_(st) { }
+      PWhile(PExpr*e1, Statement*st);
       ~PWhile();
 
-      virtual NetProc* elaborate(Design*des, const string&path) const;
+      virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
       virtual void dump(ostream&out, unsigned ind) const;
 
@@ -437,6 +453,47 @@ class PWhile  : public Statement {
 
 /*
  * $Log: Statement.h,v $
+ * Revision 1.36  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.35  2002/06/04 05:38:44  steve
+ *  Add support for memory words in l-value of
+ *  blocking assignments, and remove the special
+ *  NetAssignMem class.
+ *
+ * Revision 1.34  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
+ * Revision 1.33  2002/04/21 22:31:02  steve
+ *  Redo handling of assignment internal delays.
+ *  Leave it possible for them to be calculated
+ *  at run time.
+ *
+ * Revision 1.32  2002/04/21 04:59:07  steve
+ *  Add support for conbinational events by finding
+ *  the inputs to expressions and some statements.
+ *  Get case and assignment statements working.
+ *
+ * Revision 1.31  2001/12/03 04:47:14  steve
+ *  Parser and pform use hierarchical names as hname_t
+ *  objects instead of encoded strings.
+ *
+ * Revision 1.30  2001/11/22 06:20:59  steve
+ *  Use NetScope instead of string for scope path.
+ *
+ * Revision 1.29  2000/09/09 15:21:26  steve
+ *  move lval elaboration to PExpr virtual methods.
+ *
+ * Revision 1.28  2000/09/03 17:58:35  steve
+ *  Change elaborate_lval to return NetAssign_ objects.
+ *
+ * Revision 1.27  2000/07/26 05:08:07  steve
+ *  Parse disable statements to pform.
+ *
  * Revision 1.26  2000/05/11 23:37:26  steve
  *  Add support for procedural continuous assignment.
  *
@@ -455,104 +512,5 @@ class PWhile  : public Statement {
  *  Do not generate NetPEvent or NetNEvent objects in
  *  elaboration. NetEvent, NetEvWait and NetEvProbe
  *  take over those functions in the netlist.
- *
- * Revision 1.23  2000/04/01 19:31:57  steve
- *  Named events as far as the pform.
- *
- * Revision 1.22  2000/03/11 03:25:51  steve
- *  Locate scopes in statements.
- *
- * Revision 1.21  2000/02/23 02:56:54  steve
- *  Macintosh compilers do not support ident.
- *
- * Revision 1.20  1999/09/29 18:36:02  steve
- *  Full case support
- *
- * Revision 1.19  1999/09/22 02:00:48  steve
- *  assignment with blocking event delay.
- *
- * Revision 1.18  1999/09/15 01:55:06  steve
- *  Elaborate non-blocking assignment to memories.
- *
- * Revision 1.17  1999/09/04 19:11:46  steve
- *  Add support for delayed non-blocking assignments.
- *
- * Revision 1.16  1999/09/02 01:59:27  steve
- *  Parse non-blocking assignment delays.
- *
- * Revision 1.15  1999/07/12 00:59:36  steve
- *  procedural blocking assignment delays.
- *
- * Revision 1.14  1999/07/03 02:12:51  steve
- *  Elaborate user defined tasks.
- *
- * Revision 1.13  1999/06/24 04:24:18  steve
- *  Handle expression widths for EEE and NEE operators,
- *  add named blocks and scope handling,
- *  add registers declared in named blocks.
- *
- * Revision 1.12  1999/06/19 21:06:16  steve
- *  Elaborate and supprort to vvm the forever
- *  and repeat statements.
- *
- * Revision 1.11  1999/06/15 05:38:39  steve
- *  Support case expression lists.
- *
- * Revision 1.10  1999/06/13 23:51:16  steve
- *  l-value part select for procedural assignments.
- *
- * Revision 1.9  1999/06/06 20:45:38  steve
- *  Add parse and elaboration of non-blocking assignments,
- *  Replace list<PCase::Item*> with an svector version,
- *  Add integer support.
- *
- * Revision 1.8  1999/05/10 00:16:58  steve
- *  Parse and elaborate the concatenate operator
- *  in structural contexts, Replace vector<PExpr*>
- *  and list<PExpr*> with svector<PExpr*>, evaluate
- *  constant expressions with parameters, handle
- *  memories as lvalues.
- *
- *  Parse task declarations, integer types.
- *
- * Revision 1.7  1999/04/29 02:16:26  steve
- *  Parse OR of event expressions.
- *
- * Revision 1.6  1999/02/03 04:20:11  steve
- *  Parse and elaborate the Verilog CASE statement.
- *
- * Revision 1.5  1999/01/25 05:45:56  steve
- *  Add the LineInfo class to carry the source file
- *  location of things. PGate, Statement and PProcess.
- *
- *  elaborate handles module parameter mismatches,
- *  missing or incorrect lvalues for procedural
- *  assignment, and errors are propogated to the
- *  top of the elaboration call tree.
- *
- *  Attach line numbers to processes, gates and
- *  assignment statements.
- *
- * Revision 1.4  1998/11/11 03:13:04  steve
- *  Handle while loops.
- *
- * Revision 1.3  1998/11/09 18:55:33  steve
- *  Add procedural while loops,
- *  Parse procedural for loops,
- *  Add procedural wait statements,
- *  Add constant nodes,
- *  Add XNOR logic gate,
- *  Make vvm output look a bit prettier.
- *
- * Revision 1.2  1998/11/07 17:05:05  steve
- *  Handle procedural conditional, and some
- *  of the conditional expressions.
- *
- *  Elaborate signals and identifiers differently,
- *  allowing the netlist to hold signal information.
- *
- * Revision 1.1  1998/11/03 23:28:56  steve
- *  Introduce verilog to CVS.
- *
  */
 #endif

StringHeap.cc

@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2002 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ *  ---
+ *    You should also have recieved a copy of the Picture Elements
+ *    Binary Software License offer along with the source. This offer
+ *    allows you to obtain the right to redistribute the software in
+ *    binary (compiled) form. If you have not received it, contact
+ *    Picture Elements, Inc., 777 Panoramic Way, Berkeley, CA 94704.
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: StringHeap.cc,v 1.2 2002/08/12 01:34:58 steve Exp $"
+#endif
+
+# include  "StringHeap.h"
+#ifdef HAVE_MALLOC_H
+# include  <malloc.h>
+#endif
+# include  <stdlib.h>
+# include  <string.h>
+# include  <assert.h>
+
+StringHeap::StringHeap()
+{
+      cell_base_ = 0;
+      cell_ptr_ = HEAPCELL;
+}
+
+StringHeap::~StringHeap()
+{
+	// This is a planned memory leak. The string heap is indended
+	// to hold permanently-allocated strings.
+}
+
+const char* StringHeap::add(const char*text)
+{
+      unsigned len = strlen(text);
+      assert((len+1) <= HEAPCELL);
+
+      unsigned rem = HEAPCELL - cell_ptr_;
+      if (rem < (len+1)) {
+	    cell_base_ = (char*)malloc(HEAPCELL);
+	    cell_ptr_ = 0;
+      }
+
+      char*res = cell_base_ + cell_ptr_;
+      memcpy(res, text, len);
+      cell_ptr_ += len;
+      cell_base_[cell_ptr_++] = 0;
+
+      return res;
+}
+
+/*
+ * $Log: StringHeap.cc,v $
+ * Revision 1.2  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.1  2002/08/04 19:13:16  steve
+ *  dll uses StringHeap for named items.
+ *
+ */
+

StringHeap.h

@@ -0,0 +1,53 @@
+#ifndef __StringHeap_H
+#define __StringHeap_H
+/*
+ * Copyright (c) 2002 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: StringHeap.h,v 1.2 2002/08/12 01:34:58 steve Exp $"
+#endif
+
+class StringHeap {
+
+    public:
+      StringHeap();
+      ~StringHeap();
+
+      const char*add(const char*);
+
+    private:
+      enum { HEAPCELL = 0x10000 };
+
+      char*cell_base_;
+      unsigned cell_ptr_;
+
+    private: // not implemented
+      StringHeap(const StringHeap&);
+      StringHeap& operator= (const StringHeap&);
+};
+
+/*
+ * $Log: StringHeap.h,v $
+ * Revision 1.2  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.1  2002/08/04 19:13:16  steve
+ *  dll uses StringHeap for named items.
+ *
+ */
+#endif

acc_user.h

@@ -0,0 +1,159 @@
+#ifndef __acc_user_H
+#define __acc_user_H
+/*
+ * Copyright (c) 2002 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: acc_user.h,v 1.6 2002/08/12 01:34:58 steve Exp $"
+#endif
+
+/*
+ * This header file contains the definitions and declarations needed
+ * by an Icarus Verilog user using acc_ routines.
+ *
+ * NOTE: Icarus Verilog does not support acc_ routines. This is just a
+ * stub. The functions that are implemented here are actually
+ * implemented using VPI routines.
+ */
+
+#ifdef __cplusplus
+# define EXTERN_C_START extern "C" {
+# define EXTERN_C_END }
+#else
+# define EXTERN_C_START
+# define EXTERN_C_END
+# define bool int
+#endif
+
+EXTERN_C_START
+
+/*
+ * This is a declaration of the "handle" type that is compatible with
+ * the vpiHandle from vpi_user.h.
+ */
+typedef struct __vpiHandle *handle;
+
+/* OBJECT TYPES */
+#define accScope   21
+#define accScalar  300
+#define accVector  302
+
+/* type VALUES FOR t_setval_delay STRUCTURE */
+#define accNoDelay  0
+#define accInertialDelay 1
+#define accTransportDelay 2
+#define accPureTransportDelay 3
+#define accForceFlag 4
+#define accReleaseFlag 5
+
+/* type VALUES FOR t_setval_value STRUCTURE */
+#define accBinStrVal 1
+#define accOctStrVal 2
+#define accDecStrVal 3
+#define accHexStrVal 4
+#define accScalarVal 5
+#define accIntVal 6
+#define accRealVal 7
+#define accStringVal 8
+#define accVectorVal 9
+
+/* type VALUES FOR t_acc_time STRUCTURE */
+#define accTime 1
+#define accSimTime 2
+#define accRealTime 3
+
+
+typedef struct t_acc_time {
+      int type;
+      int low, high;
+      double real;
+} s_acc_time, *p_acc_time;
+
+typedef struct t_setval_delay {
+      s_acc_time time;
+      int model;
+} s_setval_delay, *p_setval_delay;
+
+typedef struct t_acc_vecval {
+      int aval;
+      int bval;
+} s_acc_vecval, *p_acc_vecval;
+
+typedef struct t_setval_value {
+      int format;
+      union {
+	    char*str;
+	    int scalar;
+	    int integer;
+	    double real;
+	    p_acc_vecval vector;
+      } value;
+} s_setval_value, *p_setval_value, s_acc_value, *p_acc_value;
+
+extern int acc_error_flag;
+
+extern int acc_initialize(void);
+
+extern void acc_close(void);
+
+extern int   acc_fetch_argc(void);
+extern char**acc_fetch_argv(void);
+
+extern char* acc_fetch_fullname(handle obj);
+
+extern int   acc_fetch_tfarg_int(int n);
+extern char* acc_fetch_tfarg_str(int n);
+
+extern handle acc_handle_tfarg(int n);
+
+extern handle acc_next_topmod(handle prev_topmod);
+
+extern int acc_object_of_type(handle object, int type);
+
+extern char*acc_product_version(void);
+
+extern int acc_set_value(handle obj, p_setval_value value,
+			 p_setval_delay delay);
+
+extern char* acc_version(void);
+
+EXTERN_C_END
+
+/*
+ * $Log: acc_user.h,v $
+ * Revision 1.6  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.5  2002/06/11 15:19:12  steve
+ *  Add acc_fetch_argc/argv/version (mruff)
+ *
+ * Revision 1.4  2002/06/07 02:58:58  steve
+ *  Add a bunch of acc/tf functions. (mruff)
+ *
+ * Revision 1.3  2002/06/02 19:03:29  steve
+ *  Add acc_handle_tfarg and acc_next_topmode
+ *
+ * Revision 1.2  2002/05/30 02:06:05  steve
+ *  Implement acc_product_version.
+ *
+ * Revision 1.1  2002/05/23 03:46:42  steve
+ *  Add the acc_user.h header file.
+ *
+ */
+
+#endif

async.cc

@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2002 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: async.cc,v 1.4 2002/08/18 22:07:16 steve Exp $"
+#endif
+
+# include "config.h"
+
+# include  "functor.h"
+# include  "netlist.h"
+# include  <assert.h>
+
+bool NetAssign::is_asynchronous()
+{
+      return true;
+}
+
+bool NetCondit::is_asynchronous()
+{
+      return false;
+}
+
+bool NetEvWait::is_asynchronous()
+{
+	/* The "sense" set contains the set of Nexa that are in the
+	   sensitivity list. We also presume here that the list is
+	   only LEVEL sensitive. */
+      NexusSet*sense = new NexusSet;
+      for (unsigned idx = 0 ;  idx < nevents_ ;  idx += 1) {
+	    NexusSet*tmp = event(idx)->nex_async_();
+	    if (tmp == 0) {
+		  delete sense;
+		  return false;
+	    }
+
+	    sense->add(*tmp);
+	    delete tmp;
+      }
+
+      NexusSet*inputs = statement_->nex_input();
+
+      if (! sense->contains(*inputs)) {
+	    delete sense;
+	    delete inputs;
+	    return false;
+      }
+
+      delete sense;
+      delete inputs;
+      return true;
+}
+
+bool NetProc::is_asynchronous()
+{
+      return false;
+}
+
+bool NetProcTop::is_asynchronous()
+{
+      if (type_ == NetProcTop::KINITIAL)
+	    return false;
+
+      return statement_->is_asynchronous();
+}
+
+/*
+ * $Log: async.cc,v $
+ * Revision 1.4  2002/08/18 22:07:16  steve
+ *  Detect temporaries in sequential block synthesis.
+ *
+ * Revision 1.3  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.2  2002/07/04 00:24:16  steve
+ *  initial statements are not asynchronous.
+ *
+ * Revision 1.1  2002/06/30 02:21:31  steve
+ *  Add structure for asynchronous logic synthesis.
+ *
+ */
+

attributes.txt

@@ -0,0 +1,49 @@
+
+ATTRIBUTES TO CONTROL SYNTHESIS
+
+The following is a summary of Verilog attributes that Icarus Verilog
+understands within Verilog source files to control synthesis
+behavior. This section documents generic synthesis attributes. For
+target specific attributes, see target specific documentation.
+
+These attributes only effect the behavior of the synthesizer. For
+example, the ivl_combinational will not generate an error message
+if the Verilog is being compiled for simulation. (It may generate a
+warning.)
+
+
+* Attributes for "always" and "initial" statements
+
+(* ivl_combinational *)
+
+    This attribute tells the compiler that the statement models
+    combinational logic. If the compiler finds that it cannot make
+    combinational logic out of a marked always statement, it will
+    report an error.
+
+    This attribute can be used to prevent accidentally inferring
+    latches or flip-flops where the user intended combinational
+    logic.
+
+(* ivl_synthesis_on *)
+
+    This attribute tells the compiler that the marked always statement
+    is synthesizeable. The compiler will attempt to synthesize the
+    code in the marked "always" statement. If it cannot in any way
+    synthesize it, then it will report an error.
+
+(* ivl_synthesis_off *)
+
+    If this value is attached to an "always" statement, then the
+    compiler will *not* synthesize the "always" statment. This can be
+    used, for example, to mark embedded test bench code.
+
+
+* Attributes for signals (wire/reg/integer/tri/etc.)
+
+[ none defined yet ]
+
+
+* Other Attributes
+
+[ none defined yet ]

autoconf.sh

@@ -0,0 +1,19 @@
+#!/bin/sh
+
+#
+# This shell script exists to run autoconf on source distributions
+# that are pulled from CVS. The configure scripts are not included
+# in CVS, and there are several configure.in files, so it is easiest
+# to just run this script to autoconf wherever needed.
+#
+echo "Autoconf in root..."
+autoconf
+
+for dir in vpip vvp tgt-vvp tgt-fpga libveriuser
+do
+    echo "Autoconf in $dir..."
+    ( cd ./$dir ; autoconf )
+done
+
+echo "Precompiling lexor_keyword.gperf"
+gperf -o -i 7 -C -k 1-3,\$ -L ANSI-C -H keyword_hash -N check_identifier -t ./lexor_keyword.gperf > lexor_keyword.cc

check.conf

@@ -0,0 +1,9 @@
+
+# The make check target uses this to check the compilation of the
+# compiler.
+
+[-tvvm-check]
+<ivl>./ivl %W %[s-s%s] %[N-N%N] %[T-T%T] -tvvm -Fcprop -Fnodangle -fVPI_MODULE_PATH=vpi %f %m -o%o.cc -- -
+
+[-tvvp-check]
+<ivl>./ivl %W %[s-s%s] %[N-N%N] %[T-T%T] -tdll -fDLL=./tgt-vvp/vvp.tgt -Fcprop -Fnodangle -fVPI_MODULE_PATH=vpi %f %m -o%o -- -

compiler.h

@@ -18,10 +18,12 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: compiler.h,v 1.3 2000/03/17 21:50:25 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: compiler.h,v 1.13 2002/08/12 01:34:58 steve Exp $"
 #endif
 
+# include  <list>
+
 /*
  * This defines constants and defaults for the compiler in general.
  */
@@ -33,6 +35,30 @@
 # define INTEGER_WIDTH 32
 #endif
 
+/* The TIME_WIDTH is the width of time variables. */
+#ifndef TIME_WIDTH
+# define TIME_WIDTH 64
+#endif
+
+/*
+ * When doing dynamic linking, we need a uniform way to identify the
+ * symbol. Some compilers put leading _, some trailing _. The
+ * configure script figures out which is the local convention and
+ * defines NEED_LU and NEED_TU as required.
+ */
+#ifdef NEED_LU
+#define LU "_"
+#else
+#define LU ""
+#endif
+
+#ifdef NEED_TU
+#define TU "_"
+#else
+#define TU ""
+#endif
+
+
 /*
  * These are flags to enable various sorts of warnings. By default all
  * the warnings are of, the -W<list> parameter arranges for each to be
@@ -41,17 +67,56 @@
 
 /* Implicit definitions of wires. */
 extern bool warn_implicit;
+extern bool error_implicit;
+
+/* inherit timescales accross files. */
+extern bool warn_timescale;
+
+/* This is true if verbose output is requested. */
+extern bool verbose_flag;
+
+/* This is an ordered list of library suffixxes to search. */
+extern list<const char*>library_suff;
+extern int build_library_index(const char*path, bool key_case_sensitive);
+
+/* This is the generation of Verilog that the compiler is asked to
+   support. */
+enum generation_t {
+      GN_VER1995  = 1,
+      GN_VER2001  = 2,
+      GN_SYSVER30 = 3,
+      GN_DEFAULT  = 3
+};
+
+extern generation_t generation_flag;
+
+  /* This is the string to use to invoke the preprocessor. */
+extern char*ivlpp_string;
 
 /*
  * $Log: compiler.h,v $
- * Revision 1.3  2000/03/17 21:50:25  steve
- *  Switch to control warnings.
+ * Revision 1.13  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
  *
- * Revision 1.2  2000/02/23 02:56:54  steve
- *  Macintosh compilers do not support ident.
+ * Revision 1.12  2002/05/28 20:40:37  steve
+ *  ivl indexes the search path for libraries, and
+ *  supports case insensitive module-to-file lookup.
  *
- * Revision 1.1  1999/06/06 20:42:48  steve
- *  Make compiler width a compile time constant.
+ * Revision 1.11  2002/05/28 00:50:39  steve
+ *  Add the ivl -C flag for bulk configuration
+ *  from the driver, and use that to run library
+ *  modules through the preprocessor.
  *
+ * Revision 1.10  2002/05/24 01:13:00  steve
+ *  Support language generation flag -g.
+ *
+ * Revision 1.9  2002/04/22 00:53:39  steve
+ *  Do not allow implicit wires in sensitivity lists.
+ *
+ * Revision 1.8  2002/04/15 00:04:22  steve
+ *  Timescale warnings.
+ *
+ * Revision 1.7  2001/11/16 05:07:19  steve
+ *  Add support for +libext+ in command files.
  */
 #endif

config.guess

@@ -1,6 +1,7 @@
 #! /bin/sh
 # Attempt to guess a canonical system name.
-#   Copyright (C) 1992, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
+#   Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
+#   Free Software Foundation, Inc.
 #
 # This file is free software; you can redistribute it and/or modify it
 # under the terms of the GNU General Public License as published by
@@ -22,7 +23,7 @@
 # the same distribution terms that you use for the rest of that program.
 
 # Written by Per Bothner <[email protected]>.
-# The master version of this file is at the FSF in /home/gd/gnu/lib.
+# Please send patches to <[email protected]>.
 #
 # This script attempts to guess a canonical system name similar to
 # config.sub.  If it succeeds, it prints the system name on stdout, and
@@ -35,6 +36,20 @@
 # (but try to keep the structure clean).
 #
 
+# Use $HOST_CC if defined. $CC may point to a cross-compiler
+if test x"$CC_FOR_BUILD" = x; then
+  if test x"$HOST_CC" != x; then
+    CC_FOR_BUILD="$HOST_CC"
+  else
+    if test x"$CC" != x; then
+      CC_FOR_BUILD="$CC"
+    else
+      CC_FOR_BUILD=cc
+    fi
+  fi
+fi
+
+
 # This is needed to find uname on a Pyramid OSx when run in the BSD universe.
 # ([email protected] 8/24/94.)
 if (test -f /.attbin/uname) >/dev/null 2>&1 ; then
@@ -46,11 +61,49 @@ UNAME_RELEASE=`(uname -r) 2>/dev/null` || UNAME_RELEASE=unknown
 UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown
 UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown
 
-trap 'rm -f dummy.c dummy.o dummy; exit 1' 1 2 15
+dummy=dummy-$$
+trap 'rm -f $dummy.c $dummy.o $dummy; exit 1' 1 2 15
 
 # Note: order is significant - the case branches are not exclusive.
 
 case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in
+    *:NetBSD:*:*)
+	# Netbsd (nbsd) targets should (where applicable) match one or
+	# more of the tupples: *-*-netbsdelf*, *-*-netbsdaout*,
+	# *-*-netbsdecoff* and *-*-netbsd*.  For targets that recently
+	# switched to ELF, *-*-netbsd* would select the old
+	# object file format.  This provides both forward
+	# compatibility and a consistent mechanism for selecting the
+	# object file format.
+	# Determine the machine/vendor (is the vendor relevant).
+	case "${UNAME_MACHINE}" in
+	    amiga) machine=m68k-cbm ;;
+	    arm32) machine=arm-unknown ;;
+	    atari*) machine=m68k-atari ;;
+	    sun3*) machine=m68k-sun ;;
+	    mac68k) machine=m68k-apple ;;
+	    macppc) machine=powerpc-apple ;;
+	    hp3[0-9][05]) machine=m68k-hp ;;
+	    ibmrt|romp-ibm) machine=romp-ibm ;;
+	    *) machine=${UNAME_MACHINE}-unknown ;;
+	esac
+	# The Operating System including object format.
+	if echo __ELF__ | $CC_FOR_BUILD -E - 2>/dev/null \
+		| grep __ELF__ >/dev/null
+	then
+	    # Once all utilities can be ECOFF (netbsdecoff) or a.out (netbsdaout).
+	    # Return netbsd for either.  FIX?
+	    os=netbsd
+	else
+	    os=netbsdelf
+	fi
+	# The OS release
+	release=`echo ${UNAME_RELEASE}|sed -e 's/[-_].*/\./'`
+	# Since CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM:
+	# contains redundant information, the shorter form:
+	# CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM is used.
+	echo "${machine}-${os}${release}"
+	exit 0 ;;
     alpha:OSF1:*:*)
 	if test $UNAME_RELEASE = "V4.0"; then
 		UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $3}'`
@@ -59,46 +112,62 @@ case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in
 	# A Tn.n version is a released field test version.
 	# A Xn.n version is an unreleased experimental baselevel.
 	# 1.2 uses "1.2" for uname -r.
-	cat <<EOF >dummy.s
+	cat <<EOF >$dummy.s
+	.data
+\$Lformat:
+	.byte 37,100,45,37,120,10,0	# "%d-%x\n"
+
+	.text
 	.globl main
+	.align 4
 	.ent main
 main:
-	.frame \$30,0,\$26,0
-	.prologue 0
-	.long 0x47e03d80 # implver $0
-	lda \$2,259
-	.long 0x47e20c21 # amask $2,$1
-	srl \$1,8,\$2
-	sll \$2,2,\$2
-	sll \$0,3,\$0
-	addl \$1,\$0,\$0
-	addl \$2,\$0,\$0
-	ret \$31,(\$26),1
+	.frame \$30,16,\$26,0
+	ldgp \$29,0(\$27)
+	.prologue 1
+	.long 0x47e03d80 # implver \$0
+	lda \$2,-1
+	.long 0x47e20c21 # amask \$2,\$1
+	lda \$16,\$Lformat
+	mov \$0,\$17
+	not \$1,\$18
+	jsr \$26,printf
+	ldgp \$29,0(\$26)
+	mov 0,\$16
+	jsr \$26,exit
 	.end main
 EOF
-	${CC-cc} dummy.s -o dummy 2>/dev/null
+	$CC_FOR_BUILD $dummy.s -o $dummy 2>/dev/null
 	if test "$?" = 0 ; then
-		./dummy
-		case "$?" in
-			7)
+		case `./$dummy` in
+			0-0)
 				UNAME_MACHINE="alpha"
 				;;
-			15)
+			1-0)
 				UNAME_MACHINE="alphaev5"
 				;;
-			14)
+			1-1)
 				UNAME_MACHINE="alphaev56"
 				;;
-			10)
+			1-101)
 				UNAME_MACHINE="alphapca56"
 				;;
-			16)
+			2-303)
 				UNAME_MACHINE="alphaev6"
 				;;
+			2-307)
+				UNAME_MACHINE="alphaev67"
+				;;
 		esac
 	fi
-	rm -f dummy.s dummy
-	echo ${UNAME_MACHINE}-dec-osf`echo ${UNAME_RELEASE} | sed -e 's/^[VTX]//' | tr [[A-Z]] [[a-z]]`
+	rm -f $dummy.s $dummy
+	echo ${UNAME_MACHINE}-dec-osf`echo ${UNAME_RELEASE} | sed -e 's/^[VTX]//' | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'`
+	exit 0 ;;
+    Alpha\ *:Windows_NT*:*)
+	# How do we know it's Interix rather than the generic POSIX subsystem?
+	# Should we change UNAME_MACHINE based on the output of uname instead
+	# of the specific Alpha model?
+	echo alpha-pc-interix
 	exit 0 ;;
     21064:Windows_NT:50:3)
 	echo alpha-dec-winnt3.5
@@ -106,12 +175,12 @@ EOF
     Amiga*:UNIX_System_V:4.0:*)
 	echo m68k-cbm-sysv4
 	exit 0;;
-    amiga:NetBSD:*:*)
-      echo m68k-cbm-netbsd${UNAME_RELEASE}
-      exit 0 ;;
     amiga:OpenBSD:*:*)
 	echo m68k-unknown-openbsd${UNAME_RELEASE}
 	exit 0 ;;
+    *:[Aa]miga[Oo][Ss]:*:*)
+	echo ${UNAME_MACHINE}-unknown-amigaos
+	exit 0 ;;
     arc64:OpenBSD:*:*)
 	echo mips64el-unknown-openbsd${UNAME_RELEASE}
 	exit 0 ;;
@@ -130,16 +199,16 @@ EOF
     wgrisc:OpenBSD:*:*)
 	echo mipsel-unknown-openbsd${UNAME_RELEASE}
 	exit 0 ;;
+    *:OS/390:*:*)
+	echo i370-ibm-openedition
+	exit 0 ;;
     arm:RISC*:1.[012]*:*|arm:riscix:1.[012]*:*)
 	echo arm-acorn-riscix${UNAME_RELEASE}
 	exit 0;;
-    arm32:NetBSD:*:*)
-	echo arm-unknown-netbsd`echo ${UNAME_RELEASE}|sed -e 's/[-_].*/\./'`
-	exit 0 ;;
     SR2?01:HI-UX/MPP:*:*)
 	echo hppa1.1-hitachi-hiuxmpp
 	exit 0;;
-    Pyramid*:OSx*:*:*|MIS*:OSx*:*:*)
+    Pyramid*:OSx*:*:* | MIS*:OSx*:*:* | MIS*:SMP_DC-OSx*:*:*)
 	# [email protected] (Earle F. Ake) contributed MIS and NILE.
 	if test "`(/bin/universe) 2>/dev/null`" = att ; then
 		echo pyramid-pyramid-sysv3
@@ -147,9 +216,12 @@ EOF
 		echo pyramid-pyramid-bsd
 	fi
 	exit 0 ;;
-    NILE:*:*:dcosx)
+    NILE*:*:*:dcosx)
 	echo pyramid-pyramid-svr4
 	exit 0 ;;
+    sun4H:SunOS:5.*:*)
+	echo sparc-hal-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
+	exit 0 ;;
     sun4*:SunOS:5.*:* | tadpole*:SunOS:5.*:*)
 	echo sparc-sun-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
 	exit 0 ;;
@@ -189,21 +261,38 @@ EOF
     aushp:SunOS:*:*)
 	echo sparc-auspex-sunos${UNAME_RELEASE}
 	exit 0 ;;
-    atari*:NetBSD:*:*)
-	echo m68k-atari-netbsd${UNAME_RELEASE}
-	exit 0 ;;
     atari*:OpenBSD:*:*)
 	echo m68k-unknown-openbsd${UNAME_RELEASE}
 	exit 0 ;;
-    sun3*:NetBSD:*:*)
-	echo m68k-sun-netbsd${UNAME_RELEASE}
+    # The situation for MiNT is a little confusing.  The machine name
+    # can be virtually everything (everything which is not
+    # "atarist" or "atariste" at least should have a processor
+    # > m68000).  The system name ranges from "MiNT" over "FreeMiNT"
+    # to the lowercase version "mint" (or "freemint").  Finally
+    # the system name "TOS" denotes a system which is actually not
+    # MiNT.  But MiNT is downward compatible to TOS, so this should
+    # be no problem.
+    atarist[e]:*MiNT:*:* | atarist[e]:*mint:*:* | atarist[e]:*TOS:*:*)
+        echo m68k-atari-mint${UNAME_RELEASE}
 	exit 0 ;;
+    atari*:*MiNT:*:* | atari*:*mint:*:* | atarist[e]:*TOS:*:*)
+	echo m68k-atari-mint${UNAME_RELEASE}
+        exit 0 ;;
+    *falcon*:*MiNT:*:* | *falcon*:*mint:*:* | *falcon*:*TOS:*:*)
+        echo m68k-atari-mint${UNAME_RELEASE}
+	exit 0 ;;
+    milan*:*MiNT:*:* | milan*:*mint:*:* | *milan*:*TOS:*:*)
+        echo m68k-milan-mint${UNAME_RELEASE}
+        exit 0 ;;
+    hades*:*MiNT:*:* | hades*:*mint:*:* | *hades*:*TOS:*:*)
+        echo m68k-hades-mint${UNAME_RELEASE}
+        exit 0 ;;
+    *:*MiNT:*:* | *:*mint:*:* | *:*TOS:*:*)
+        echo m68k-unknown-mint${UNAME_RELEASE}
+        exit 0 ;;
     sun3*:OpenBSD:*:*)
 	echo m68k-unknown-openbsd${UNAME_RELEASE}
 	exit 0 ;;
-    mac68k:NetBSD:*:*)
-	echo m68k-apple-netbsd${UNAME_RELEASE}
-	exit 0 ;;
     mac68k:OpenBSD:*:*)
 	echo m68k-unknown-openbsd${UNAME_RELEASE}
 	exit 0 ;;
@@ -225,12 +314,17 @@ EOF
     VAX*:ULTRIX*:*:*)
 	echo vax-dec-ultrix${UNAME_RELEASE}
 	exit 0 ;;
-    2020:CLIX:*:*)
+    2020:CLIX:*:* | 2430:CLIX:*:*)
 	echo clipper-intergraph-clix${UNAME_RELEASE}
 	exit 0 ;;
     mips:*:*:UMIPS | mips:*:*:RISCos)
-	sed 's/^	//' << EOF >dummy.c
-	int main (argc, argv) int argc; char **argv; {
+	sed 's/^	//' << EOF >$dummy.c
+#ifdef __cplusplus
+#include <stdio.h>  /* for printf() prototype */
+	int main (int argc, char *argv[]) {
+#else
+	int main (argc, argv) int argc; char *argv[]; {
+#endif
 	#if defined (host_mips) && defined (MIPSEB)
 	#if defined (SYSTYPE_SYSV)
 	  printf ("mips-mips-riscos%ssysv\n", argv[1]); exit (0);
@@ -245,10 +339,10 @@ EOF
 	  exit (-1);
 	}
 EOF
-	${CC-cc} dummy.c -o dummy \
-	  && ./dummy `echo "${UNAME_RELEASE}" | sed -n 's/\([0-9]*\).*/\1/p'` \
-	  && rm dummy.c dummy && exit 0
-	rm -f dummy.c dummy
+	$CC_FOR_BUILD $dummy.c -o $dummy \
+	  && ./$dummy `echo "${UNAME_RELEASE}" | sed -n 's/\([0-9]*\).*/\1/p'` \
+	  && rm $dummy.c $dummy && exit 0
+	rm -f $dummy.c $dummy
 	echo mips-mips-riscos${UNAME_RELEASE}
 	exit 0 ;;
     Night_Hawk:Power_UNIX:*:*)
@@ -266,15 +360,18 @@ EOF
     AViiON:dgux:*:*)
         # DG/UX returns AViiON for all architectures
         UNAME_PROCESSOR=`/usr/bin/uname -p`
-        if [ $UNAME_PROCESSOR = mc88100 -o $UNAME_PROCESSOR = mc88110 ] ; then
-	if [ ${TARGET_BINARY_INTERFACE}x = m88kdguxelfx \
-	     -o ${TARGET_BINARY_INTERFACE}x = x ] ; then
+	if [ $UNAME_PROCESSOR = mc88100 ] || [ $UNAME_PROCESSOR = mc88110 ]
+	then
+	    if [ ${TARGET_BINARY_INTERFACE}x = m88kdguxelfx ] || \
+	       [ ${TARGET_BINARY_INTERFACE}x = x ]
+	    then
 		echo m88k-dg-dgux${UNAME_RELEASE}
-	else
+	    else
 		echo m88k-dg-dguxbcs${UNAME_RELEASE}
+	    fi
+	else
+	    echo i586-dg-dgux${UNAME_RELEASE}
 	fi
-        else echo i586-dg-dgux${UNAME_RELEASE}
-        fi
  	exit 0 ;;
     M88*:DolphinOS:*:*)	# DolphinOS (SVR3)
 	echo m88k-dolphin-sysv3
@@ -300,7 +397,7 @@ EOF
 	exit 0 ;;
     *:AIX:2:3)
 	if grep bos325 /usr/include/stdio.h >/dev/null 2>&1; then
-		sed 's/^		//' << EOF >dummy.c
+		sed 's/^		//' << EOF >$dummy.c
 		#include <sys/systemcfg.h>
 
 		main()
@@ -311,8 +408,8 @@ EOF
 			exit(0);
 			}
 EOF
-		${CC-cc} dummy.c -o dummy && ./dummy && rm dummy.c dummy && exit 0
-		rm -f dummy.c dummy
+		$CC_FOR_BUILD $dummy.c -o $dummy && ./$dummy && rm $dummy.c $dummy && exit 0
+		rm -f $dummy.c $dummy
 		echo rs6000-ibm-aix3.2.5
 	elif grep bos324 /usr/include/stdio.h >/dev/null 2>&1; then
 		echo rs6000-ibm-aix3.2.4
@@ -321,7 +418,8 @@ EOF
 	fi
 	exit 0 ;;
     *:AIX:*:4)
-	if /usr/sbin/lsattr -EHl proc0 | grep POWER >/dev/null 2>&1; then
+	IBM_CPU_ID=`/usr/sbin/lsdev -C -c processor -S available | head -1 | awk '{ print $1 }'`
+	if /usr/sbin/lsattr -EHl ${IBM_CPU_ID} | grep POWER >/dev/null 2>&1; then
 		IBM_ARCH=rs6000
 	else
 		IBM_ARCH=powerpc
@@ -339,7 +437,7 @@ EOF
     ibmrt:4.4BSD:*|romp-ibm:BSD:*)
 	echo romp-ibm-bsd4.4
 	exit 0 ;;
-    ibmrt:*BSD:*|romp-ibm:BSD:*)            # covers RT/PC NetBSD and
+    ibmrt:*BSD:*|romp-ibm:BSD:*)            # covers RT/PC BSD and
 	echo romp-ibm-bsd${UNAME_RELEASE}   # 4.3 with uname added to
 	exit 0 ;;                           # report: romp-ibm BSD 4.3
     *:BOSX:*:*)
@@ -354,18 +452,52 @@ EOF
     hp300:4.4BSD:*:* | 9000/[34]??:4.3bsd:2.*:*)
 	echo m68k-hp-bsd4.4
 	exit 0 ;;
-    9000/[3478]??:HP-UX:*:*)
+    9000/[34678]??:HP-UX:*:*)
 	case "${UNAME_MACHINE}" in
 	    9000/31? )            HP_ARCH=m68000 ;;
 	    9000/[34]?? )         HP_ARCH=m68k ;;
-	    9000/7?? | 9000/8?[1679] ) HP_ARCH=hppa1.1 ;;
-	    9000/8?? )            HP_ARCH=hppa1.0 ;;
+	    9000/[678][0-9][0-9])
+              sed 's/^              //' << EOF >$dummy.c
+
+              #define _HPUX_SOURCE
+              #include <stdlib.h>
+              #include <unistd.h>
+
+              int main ()
+              {
+              #if defined(_SC_KERNEL_BITS)
+                  long bits = sysconf(_SC_KERNEL_BITS);
+              #endif
+                  long cpu  = sysconf (_SC_CPU_VERSION);
+
+                  switch (cpu)
+              	{
+              	case CPU_PA_RISC1_0: puts ("hppa1.0"); break;
+              	case CPU_PA_RISC1_1: puts ("hppa1.1"); break;
+              	case CPU_PA_RISC2_0:
+              #if defined(_SC_KERNEL_BITS)
+              	    switch (bits)
+              		{
+              		case 64: puts ("hppa2.0w"); break;
+              		case 32: puts ("hppa2.0n"); break;
+              		default: puts ("hppa2.0"); break;
+              		} break;
+              #else  /* !defined(_SC_KERNEL_BITS) */
+              	    puts ("hppa2.0"); break;
+              #endif
+              	default: puts ("hppa1.0"); break;
+              	}
+                  exit (0);
+              }
+EOF
+	(CCOPTS= $CC_FOR_BUILD $dummy.c -o $dummy 2>/dev/null ) && HP_ARCH=`./$dummy`
+	rm -f $dummy.c $dummy
 	esac
 	HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'`
 	echo ${HP_ARCH}-hp-hpux${HPUX_REV}
 	exit 0 ;;
     3050*:HI-UX:*:*)
-	sed 's/^	//' << EOF >dummy.c
+	sed 's/^	//' << EOF >$dummy.c
 	#include <unistd.h>
 	int
 	main ()
@@ -390,8 +522,8 @@ EOF
 	  exit (0);
 	}
 EOF
-	${CC-cc} dummy.c -o dummy && ./dummy && rm dummy.c dummy && exit 0
-	rm -f dummy.c dummy
+	$CC_FOR_BUILD $dummy.c -o $dummy && ./$dummy && rm $dummy.c $dummy && exit 0
+	rm -f $dummy.c $dummy
 	echo unknown-hitachi-hiuxwe2
 	exit 0 ;;
     9000/7??:4.3bsd:*:* | 9000/8?[79]:4.3bsd:*:* )
@@ -400,6 +532,9 @@ EOF
     9000/8??:4.3bsd:*:*)
 	echo hppa1.0-hp-bsd
 	exit 0 ;;
+    *9??*:MPE/iX:*:*)
+	echo hppa1.0-hp-mpeix
+	exit 0 ;;
     hp7??:OSF1:*:* | hp8?[79]:OSF1:*:* )
 	echo hppa1.1-hp-osf
 	exit 0 ;;
@@ -416,6 +551,9 @@ EOF
     parisc*:Lites*:*:*)
 	echo hppa1.1-hp-lites
 	exit 0 ;;
+    hppa*:OpenBSD:*:*)
+	echo hppa-unknown-openbsd
+	exit 0 ;;
     C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*)
 	echo c1-convex-bsd
         exit 0 ;;
@@ -446,45 +584,60 @@ EOF
 	      -e y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/
 	exit 0 ;;
     CRAY*TS:*:*:*)
-	echo t90-cray-unicos${UNAME_RELEASE}
+	echo t90-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/'
+	exit 0 ;;
+    CRAY*T3E:*:*:*)
+	echo alpha-cray-unicosmk${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/'
+	exit 0 ;;
+    CRAY*SV1:*:*:*)
+	echo sv1-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/'
 	exit 0 ;;
     CRAY-2:*:*:*)
 	echo cray2-cray-unicos
         exit 0 ;;
     F300:UNIX_System_V:*:*)
-        FUJITSU_SYS=`uname -p | tr [A-Z] [a-z] | sed -e 's/\///'`
+        FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'`
         FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'`
         echo "f300-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}"
         exit 0 ;;
     F301:UNIX_System_V:*:*)
        echo f301-fujitsu-uxpv`echo $UNAME_RELEASE | sed 's/ .*//'`
        exit 0 ;;
-    hp3[0-9][05]:NetBSD:*:*)
-	echo m68k-hp-netbsd${UNAME_RELEASE}
-	exit 0 ;;
     hp300:OpenBSD:*:*)
 	echo m68k-unknown-openbsd${UNAME_RELEASE}
 	exit 0 ;;
-    i?86:BSD/386:*:* | *:BSD/OS:*:*)
+    i?86:BSD/386:*:* | i?86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*)
 	echo ${UNAME_MACHINE}-pc-bsdi${UNAME_RELEASE}
 	exit 0 ;;
+    sparc*:BSD/OS:*:*)
+	echo sparc-unknown-bsdi${UNAME_RELEASE}
+	exit 0 ;;
+    *:BSD/OS:*:*)
+	echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE}
+	exit 0 ;;
     *:FreeBSD:*:*)
 	echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`
 	exit 0 ;;
-    *:NetBSD:*:*)
-	echo ${UNAME_MACHINE}-unknown-netbsd`echo ${UNAME_RELEASE}|sed -e 's/[-_].*/\./'`
-	exit 0 ;;
     *:OpenBSD:*:*)
 	echo ${UNAME_MACHINE}-unknown-openbsd`echo ${UNAME_RELEASE}|sed -e 's/[-_].*/\./'`
 	exit 0 ;;
     i*:CYGWIN*:*)
-	echo i386-pc-cygwin32
+	echo ${UNAME_MACHINE}-pc-cygwin
 	exit 0 ;;
     i*:MINGW*:*)
-	echo i386-pc-mingw32
+	echo ${UNAME_MACHINE}-pc-mingw32
+	exit 0 ;;
+    i*:Windows_NT*:* | Pentium*:Windows_NT*:*)
+	# How do we know it's Interix rather than the generic POSIX subsystem?
+	# It also conflicts with pre-2.0 versions of AT&T UWIN. Should we
+	# UNAME_MACHINE based on the output of uname instead of i386?
+	echo i386-pc-interix
+	exit 0 ;;
+    i*:UWIN*:*)
+	echo ${UNAME_MACHINE}-pc-uwin
 	exit 0 ;;
     p*:CYGWIN*:*)
-	echo powerpcle-unknown-cygwin32
+	echo powerpcle-unknown-cygwin
 	exit 0 ;;
     prep*:SunOS:5.*:*)
 	echo powerpcle-unknown-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
@@ -493,9 +646,11 @@ EOF
 	echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'`
 	exit 0 ;;
     *:Linux:*:*)
+
 	# The BFD linker knows what the default object file format is, so
-	# first see if it will tell us.
-	ld_help_string=`ld --help 2>&1`
+	# first see if it will tell us. cd to the root directory to prevent
+	# problems with other programs or directories called `ld' in the path.
+	ld_help_string=`cd /; ld --help 2>&1`
 	ld_supported_emulations=`echo $ld_help_string \
 			 | sed -ne '/supported emulations:/!d
 				    s/[ 	][ 	]*/ /g
@@ -503,13 +658,45 @@ EOF
 				    s/ .*//
 				    p'`
         case "$ld_supported_emulations" in
-	  i?86linux)  echo "${UNAME_MACHINE}-pc-linux-gnuaout"      ; exit 0 ;;
-	  i?86coff)   echo "${UNAME_MACHINE}-pc-linux-gnucoff"      ; exit 0 ;;
-	  sparclinux) echo "${UNAME_MACHINE}-unknown-linux-gnuaout" ; exit 0 ;;
-	  m68klinux)  echo "${UNAME_MACHINE}-unknown-linux-gnuaout" ; exit 0 ;;
-	  elf32ppc)
+	  *ia64)
+		echo "${UNAME_MACHINE}-unknown-linux"
+		exit 0
+		;;
+	  i?86linux)
+		echo "${UNAME_MACHINE}-pc-linux-gnuaout"
+		exit 0
+		;;
+	  elf_i?86)
+		echo "${UNAME_MACHINE}-pc-linux"
+		exit 0
+		;;
+	  i?86coff)
+		echo "${UNAME_MACHINE}-pc-linux-gnucoff"
+		exit 0
+		;;
+	  sparclinux)
+		echo "${UNAME_MACHINE}-unknown-linux-gnuaout"
+		exit 0
+		;;
+	  armlinux)
+		echo "${UNAME_MACHINE}-unknown-linux-gnuaout"
+		exit 0
+		;;
+	  elf32arm*)
+		echo "${UNAME_MACHINE}-unknown-linux-gnuoldld"
+		exit 0
+		;;
+	  armelf_linux*)
+		echo "${UNAME_MACHINE}-unknown-linux-gnu"
+		exit 0
+		;;
+	  m68klinux)
+		echo "${UNAME_MACHINE}-unknown-linux-gnuaout"
+		exit 0
+		;;
+	  elf32ppc | elf32ppclinux)
 		# Determine Lib Version
-		cat >dummy.c <<EOF
+		cat >$dummy.c <<EOF
 #include <features.h>
 #if defined(__GLIBC__)
 extern char __libc_version[];
@@ -528,71 +715,85 @@ main(argc, argv)
 }
 EOF
 		LIBC=""
-		${CC-cc} dummy.c -o dummy 2>/dev/null
+		$CC_FOR_BUILD $dummy.c -o $dummy 2>/dev/null
 		if test "$?" = 0 ; then
-			./dummy | grep 1\.99 > /dev/null
+			./$dummy | grep 1\.99 > /dev/null
 			if test "$?" = 0 ; then
 				LIBC="libc1"
 			fi
-		fi	
-		rm -f dummy.c dummy
-		echo powerpc-unknown-linux-gnu${LIBC} ; exit 0 ;;
+		fi
+		rm -f $dummy.c $dummy
+		echo powerpc-unknown-linux-gnu${LIBC}
+		exit 0
+		;;
 	esac
 
 	if test "${UNAME_MACHINE}" = "alpha" ; then
-		sed 's/^	//'  <<EOF >dummy.s
-		.globl main
-		.ent main
-	main:
-		.frame \$30,0,\$26,0
-		.prologue 0
-		.long 0x47e03d80 # implver $0
-		lda \$2,259
-		.long 0x47e20c21 # amask $2,$1
-		srl \$1,8,\$2
-		sll \$2,2,\$2
-		sll \$0,3,\$0
-		addl \$1,\$0,\$0
-		addl \$2,\$0,\$0
-		ret \$31,(\$26),1
-		.end main
+		cat <<EOF >$dummy.s
+			.data
+		\$Lformat:
+			.byte 37,100,45,37,120,10,0	# "%d-%x\n"
+
+			.text
+			.globl main
+			.align 4
+			.ent main
+		main:
+			.frame \$30,16,\$26,0
+			ldgp \$29,0(\$27)
+			.prologue 1
+			.long 0x47e03d80 # implver \$0
+			lda \$2,-1
+			.long 0x47e20c21 # amask \$2,\$1
+			lda \$16,\$Lformat
+			mov \$0,\$17
+			not \$1,\$18
+			jsr \$26,printf
+			ldgp \$29,0(\$26)
+			mov 0,\$16
+			jsr \$26,exit
+			.end main
 EOF
 		LIBC=""
-		${CC-cc} dummy.s -o dummy 2>/dev/null
+		$CC_FOR_BUILD $dummy.s -o $dummy 2>/dev/null
 		if test "$?" = 0 ; then
-			./dummy
-			case "$?" in
-			7)
+			case `./$dummy` in
+			0-0)
 				UNAME_MACHINE="alpha"
 				;;
-			15)
+			1-0)
 				UNAME_MACHINE="alphaev5"
 				;;
-			14)
+			1-1)
 				UNAME_MACHINE="alphaev56"
 				;;
-			10)
+			1-101)
 				UNAME_MACHINE="alphapca56"
 				;;
-			16)
+			2-303)
 				UNAME_MACHINE="alphaev6"
 				;;
-			esac	
+			2-307)
+				UNAME_MACHINE="alphaev67"
+				;;
+			esac
 
-			objdump --private-headers dummy | \
+			objdump --private-headers $dummy | \
 			  grep ld.so.1 > /dev/null
 			if test "$?" = 0 ; then
 				LIBC="libc1"
 			fi
-		fi	
-		rm -f dummy.s dummy
+		fi
+		rm -f $dummy.s $dummy
 		echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC} ; exit 0
 	elif test "${UNAME_MACHINE}" = "mips" ; then
-	  cat >dummy.c <<EOF
-main(argc, argv)
-     int argc;
-     char *argv[];
-{
+	  cat >$dummy.c <<EOF
+#ifdef __cplusplus
+#include <stdio.h>  /* for printf() prototype */
+	int main (int argc, char *argv[]) {
+#else
+	int main (argc, argv) int argc; char *argv[]; {
+#endif
 #ifdef __MIPSEB__
   printf ("%s-unknown-linux-gnu\n", argv[1]);
 #endif
@@ -602,8 +803,10 @@ main(argc, argv)
   return 0;
 }
 EOF
-	  ${CC-cc} dummy.c -o dummy 2>/dev/null && ./dummy "${UNAME_MACHINE}" && rm dummy.c dummy && exit 0
-	  rm -f dummy.c dummy
+	  $CC_FOR_BUILD $dummy.c -o $dummy 2>/dev/null && ./$dummy "${UNAME_MACHINE}" && rm $dummy.c $dummy && exit 0
+	  rm -f $dummy.c $dummy
+	elif test "${UNAME_MACHINE}" = "s390"; then
+	  echo s390-ibm-linux && exit 0
 	else
 	  # Either a pre-BFD a.out linker (linux-gnuoldld)
 	  # or one that does not give us useful --help.
@@ -622,12 +825,14 @@ EOF
 	    ;;
 	  esac
 	  # Determine whether the default compiler is a.out or elf
-	  cat >dummy.c <<EOF
+	  cat >$dummy.c <<EOF
 #include <features.h>
-main(argc, argv)
-     int argc;
-     char *argv[];
-{
+#ifdef __cplusplus
+#include <stdio.h>  /* for printf() prototype */
+	int main (int argc, char *argv[]) {
+#else
+	int main (argc, argv) int argc; char *argv[]; {
+#endif
 #ifdef __ELF__
 # ifdef __GLIBC__
 #  if __GLIBC__ >= 2
@@ -644,8 +849,8 @@ main(argc, argv)
   return 0;
 }
 EOF
-	  ${CC-cc} dummy.c -o dummy 2>/dev/null && ./dummy "${UNAME_MACHINE}" && rm dummy.c dummy && exit 0
-	  rm -f dummy.c dummy
+	  $CC_FOR_BUILD $dummy.c -o $dummy 2>/dev/null && ./$dummy "${UNAME_MACHINE}" && rm $dummy.c $dummy && exit 0
+	  rm -f $dummy.c $dummy
 	fi ;;
 # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there.  earlier versions
 # are messed up and put the nodename in both sysname and nodename.
@@ -661,10 +866,20 @@ EOF
 	echo ${UNAME_MACHINE}-pc-sysv4.2uw${UNAME_VERSION}
 	exit 0 ;;
     i?86:*:4.*:* | i?86:SYSTEM_V:4.*:*)
+	UNAME_REL=`echo ${UNAME_RELEASE} | sed 's/\/MP$//'`
 	if grep Novell /usr/include/link.h >/dev/null 2>/dev/null; then
-		echo ${UNAME_MACHINE}-univel-sysv${UNAME_RELEASE}
+		echo ${UNAME_MACHINE}-univel-sysv${UNAME_REL}
 	else
-		echo ${UNAME_MACHINE}-pc-sysv${UNAME_RELEASE}
+		echo ${UNAME_MACHINE}-pc-sysv${UNAME_REL}
+	fi
+	exit 0 ;;
+    i?86:*:5:7*)
+        # Fixed at (any) Pentium or better
+        UNAME_MACHINE=i586
+        if [ ${UNAME_SYSTEM} = "UnixWare" ] ; then
+	    echo ${UNAME_MACHINE}-sco-sysv${UNAME_RELEASE}uw${UNAME_VERSION}
+	else
+	    echo ${UNAME_MACHINE}-pc-sysv${UNAME_RELEASE}
 	fi
 	exit 0 ;;
     i?86:*:3.2:*)
@@ -676,12 +891,20 @@ EOF
 		(/bin/uname -X|egrep i80486 >/dev/null) && UNAME_MACHINE=i486
 		(/bin/uname -X|egrep '^Machine.*Pentium' >/dev/null) \
 			&& UNAME_MACHINE=i586
+		(/bin/uname -X|egrep '^Machine.*Pent ?II' >/dev/null) \
+			&& UNAME_MACHINE=i686
+		(/bin/uname -X|egrep '^Machine.*Pentium Pro' >/dev/null) \
+			&& UNAME_MACHINE=i686
 		echo ${UNAME_MACHINE}-pc-sco$UNAME_REL
 	else
 		echo ${UNAME_MACHINE}-pc-sysv32
 	fi
 	exit 0 ;;
+    i?86:*DOS:*:*)
+	echo ${UNAME_MACHINE}-pc-msdosdjgpp
+	exit 0 ;;
     pc:*:*:*)
+	# Left here for compatibility:
         # uname -m prints for DJGPP always 'pc', but it prints nothing about
         # the processor, so we play safe by assuming i386.
 	echo i386-pc-msdosdjgpp
@@ -722,7 +945,7 @@ EOF
     mc68030:UNIX_System_V:4.*:*)
 	echo m68k-atari-sysv4
 	exit 0 ;;
-    i?86:LynxOS:2.*:*)
+    i?86:LynxOS:2.*:* | i?86:LynxOS:3.[01]*:*)
 	echo i386-unknown-lynxos${UNAME_RELEASE}
 	exit 0 ;;
     TSUNAMI:LynxOS:2.*:*)
@@ -734,6 +957,9 @@ EOF
     SM[BE]S:UNIX_SV:*:*)
 	echo mips-dde-sysv${UNAME_RELEASE}
 	exit 0 ;;
+    RM*:ReliantUNIX-*:*:*)
+	echo mips-sni-sysv4
+	exit 0 ;;
     RM*:SINIX-*:*:*)
 	echo mips-sni-sysv4
 	exit 0 ;;
@@ -764,19 +990,61 @@ EOF
     news*:NEWS-OS:*:6*)
 	echo mips-sony-newsos6
 	exit 0 ;;
-    R3000:*System_V*:*:* | R4000:UNIX_SYSV:*:*)
+    R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*)
 	if [ -d /usr/nec ]; then
 	        echo mips-nec-sysv${UNAME_RELEASE}
 	else
 	        echo mips-unknown-sysv${UNAME_RELEASE}
 	fi
         exit 0 ;;
+    BeBox:BeOS:*:*)	# BeOS running on hardware made by Be, PPC only.
+	echo powerpc-be-beos
+	exit 0 ;;
+    BeMac:BeOS:*:*)	# BeOS running on Mac or Mac clone, PPC only.
+	echo powerpc-apple-beos
+	exit 0 ;;
+    BePC:BeOS:*:*)	# BeOS running on Intel PC compatible.
+	echo i586-pc-beos
+	exit 0 ;;
+    SX-4:SUPER-UX:*:*)
+	echo sx4-nec-superux${UNAME_RELEASE}
+	exit 0 ;;
+    SX-5:SUPER-UX:*:*)
+	echo sx5-nec-superux${UNAME_RELEASE}
+	exit 0 ;;
+    Power*:Rhapsody:*:*)
+	echo powerpc-apple-rhapsody${UNAME_RELEASE}
+	exit 0 ;;
+    *:Rhapsody:*:*)
+	echo ${UNAME_MACHINE}-apple-rhapsody${UNAME_RELEASE}
+	exit 0 ;;
+    *:Darwin:*:*)
+	echo `uname -p`-apple-darwin${UNAME_RELEASE}
+	exit 0 ;;
+    *:procnto*:*:* | *:QNX:[0123456789]*:*)
+	if test "${UNAME_MACHINE}" = "x86pc"; then
+		UNAME_MACHINE=pc
+	fi
+	echo `uname -p`-${UNAME_MACHINE}-nto-qnx
+	exit 0 ;;
+    *:QNX:*:4*)
+	echo i386-pc-qnx
+	exit 0 ;;
+    NSR-W:NONSTOP_KERNEL:*:*)
+	echo nsr-tandem-nsk${UNAME_RELEASE}
+	exit 0 ;;
+    BS2000:POSIX*:*:*)
+	echo bs2000-siemens-sysv
+	exit 0 ;;
+    DS/*:UNIX_System_V:*:*)
+	echo ${UNAME_MACHINE}-${UNAME_SYSTEM}-${UNAME_RELEASE}
+	exit 0 ;;
 esac
 
 #echo '(No uname command or uname output not recognized.)' 1>&2
 #echo "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" 1>&2
 
-cat >dummy.c <<EOF
+cat >$dummy.c <<EOF
 #ifdef _SEQUENT_
 # include <sys/types.h>
 # include <sys/utsname.h>
@@ -814,7 +1082,10 @@ main ()
 #endif
   int version;
   version=`(hostinfo | sed -n 's/.*NeXT Mach \([0-9]*\).*/\1/p') 2>/dev/null`;
-  printf ("%s-next-nextstep%d\n", __ARCHITECTURE__, version);
+  if (version < 4)
+    printf ("%s-next-nextstep%d\n", __ARCHITECTURE__, version);
+  else
+    printf ("%s-next-openstep%d\n", __ARCHITECTURE__, version);
   exit (0);
 #endif
 
@@ -874,8 +1145,8 @@ main ()
 }
 EOF
 
-${CC-cc} dummy.c -o dummy 2>/dev/null && ./dummy && rm dummy.c dummy && exit 0
-rm -f dummy.c dummy
+$CC_FOR_BUILD $dummy.c -o $dummy 2>/dev/null && ./$dummy && rm $dummy.c $dummy && exit 0
+rm -f $dummy.c $dummy
 
 # Apollos put the system type in the environment.
 

config.h.in

@@ -0,0 +1,66 @@
+#ifndef __config_H                                           /* -*- c++ -*- */
+#define __config_H
+/*
+ * Copyright (c) 2001 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#if !defined(WINNT)
+#ident "$Id: config.h.in,v 1.5 2002/08/11 23:39:33 steve Exp $"
+#endif
+
+#if defined(__cplusplus)
+#  if !defined(__GNUC__)
+     using namespace std;
+#  elif (__GNUC__ == 3)
+     using namespace std;
+#  endif
+#endif
+
+# undef NEED_LU
+# undef NEED_TU  
+# undef WLU
+# undef WTU
+# undef HAVE_TIMES
+# undef HAVE_IOSFWD
+# undef HAVE_GETOPT_H
+# undef HAVE_MALLOC_H
+# undef HAVE_DLFCN_H
+# undef HAVE_DL_H
+# undef HAVE_FCHMOD
+# undef HAVE_LIBREADLINE
+# undef HAVE_SYS_WAIT_H
+
+/*
+ * $Log: config.h.in,v $
+ * Revision 1.5  2002/08/11 23:39:33  steve
+ *  Remove VVM option.
+ *
+ * Revision 1.4  2002/02/16 03:18:53  steve
+ *  Make vvm optional, normally off.
+ *
+ * Revision 1.3  2001/10/18 16:16:23  steve
+ *  Include HAVE_SYS_WAIT in config.h (PR#306)
+ *
+ * Revision 1.2  2001/09/15 18:27:04  steve
+ *  Make configure detect malloc.h
+ *
+ * Revision 1.1  2001/07/25 03:10:48  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
+ */
+#endif // __config_H

config.sub

@@ -1,6 +1,8 @@
 #! /bin/sh
 # Configuration validation subroutine script, version 1.1.
-#   Copyright (C) 1991, 92, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
+#   Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
+#   Free Software Foundation, Inc.
+#
 # This file is (in principle) common to ALL GNU software.
 # The presence of a machine in this file suggests that SOME GNU software
 # can handle that machine.  It does not imply ALL GNU software can.
@@ -25,6 +27,9 @@
 # configuration script generated by Autoconf, you may include it under
 # the same distribution terms that you use for the rest of that program.
 
+# Written by Per Bothner <[email protected]>.
+# Please send patches to <[email protected]>.
+#
 # Configuration subroutine to validate and canonicalize a configuration type.
 # Supply the specified configuration type as an argument.
 # If it is invalid, we print an error message on stderr and exit with code 1.
@@ -68,7 +73,7 @@ esac
 # Here we must recognize all the valid KERNEL-OS combinations.
 maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'`
 case $maybe_os in
-  linux-gnu*)
+  nto-qnx* | linux-gnu*)
     os=-$maybe_os
     basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'`
     ;;
@@ -98,21 +103,21 @@ case $os in
 		os=
 		basic_machine=$1
 		;;
-	-sim | -cisco | -oki | -wec | -winbond )	# CYGNUS LOCAL
+	-sim | -cisco | -oki | -wec | -winbond)
 		os=
 		basic_machine=$1
 		;;
-	-scout)						# CYGNUS LOCAL
+	-scout)
 		;;
-	-wrs)						# CYGNUS LOCAL
-		os=vxworks
+	-wrs)
+		os=-vxworks
 		basic_machine=$1
 		;;
 	-hiux*)
 		os=-hiuxwe2
 		;;
 	-sco5)
-		os=sco3.2v5
+		os=-sco3.2v5
 		basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
 		;;
 	-sco4)
@@ -131,6 +136,9 @@ case $os in
 		os=-sco3.2v2
 		basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
 		;;
+	-udk*)
+		basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
+		;;
 	-isc)
 		os=-isc2.2
 		basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
@@ -153,44 +161,40 @@ case $os in
 	-psos*)
 		os=-psos
 		;;
+	-mint | -mint[0-9]*)
+		basic_machine=m68k-atari
+		os=-mint
+		;;
 esac
 
 # Decode aliases for certain CPU-COMPANY combinations.
 case $basic_machine in
 	# Recognize the basic CPU types without company name.
 	# Some are omitted here because they have special meanings below.
-	tahoe | i860 | m32r | m68k | m68000 | m88k | ns32k | arc | arm \
-		| arme[lb] | pyramid | mn10200 | mn10300 \
-		| tron | a29k | 580 | i960 | h8300 | hppa | hppa1.0 | hppa1.1 \
-		| alpha | alphaev5 | alphaev56 | we32k | ns16k | clipper \
-		| i370 | sh | powerpc | powerpcle | 1750a | dsp16xx | pdp11 \
-		| mips64 | mipsel | mips64el | mips64orion | mips64orionel \
-		| mipstx39 | mipstx39el \
-		| sparc | sparclet | sparclite | sparc64 | v850)
+	tahoe | i860 | ia64 | m32r | m68k | m68000 | m88k | ns32k | arc | arm \
+		| arme[lb] | pyramid | mn10200 | mn10300 | tron | a29k \
+		| 580 | i960 | h8300 \
+		| x86 | ppcbe | mipsbe | mipsle | shbe | shle | armbe | armle \
+		| hppa | hppa1.0 | hppa1.1 | hppa2.0 | hppa2.0w | hppa2.0n \
+		| hppa64 \
+		| alpha | alphaev[4-8] | alphaev56 | alphapca5[67] \
+		| alphaev6[78] \
+		| we32k | ns16k | clipper | i370 | sh | powerpc | powerpcle \
+		| 1750a | dsp16xx | pdp11 | mips16 | mips64 | mipsel | mips64el \
+		| mips64orion | mips64orionel | mipstx39 | mipstx39el \
+		| mips64vr4300 | mips64vr4300el | mips64vr4100 | mips64vr4100el \
+		| mips64vr5000 | miprs64vr5000el | mcore \
+		| sparc | sparclet | sparclite | sparc64 | sparcv9 | v850 | c4x \
+		| thumb | d10v | fr30 | avr)
 		basic_machine=$basic_machine-unknown
 		;;
-	m88110 | m680[01234]0 | m683?2 | m68360 | z8k | v70 | h8500 | w65) # CYGNUS LOCAL
-		basic_machine=$basic_machine-unknown
-		;;
-	mips64vr4300 | mips64vr4300el) # CYGNUS LOCAL jsmith/vr4300
-		basic_machine=$basic_machine-unknown
-		;;
-	mips64vr4100 | mips64vr4100el) # CYGNUS LOCAL jsmith/vr4100
-		basic_machine=$basic_machine-unknown
-		;;
-	mips64vr5000 | mips64vr5000el) # CYGNUS LOCAL ian/vr5000
-		basic_machine=$basic_machine-unknown
-		;;
-	mips16) # CYGNUS LOCAL krk/mips16
-		basic_machine=$basic_machine-unknown
-		;;
-	d10v)				# CYGNUS LOCAL meissner/d10v
-		basic_machine=$basic_machine-unknown
+	m88110 | m680[12346]0 | m683?2 | m68360 | m5200 | z8k | v70 | h8500 | w65 | pj | pjl)
 		;;
+
 	# We use `pc' rather than `unknown'
 	# because (1) that's what they normally are, and
 	# (2) the word "unknown" tends to confuse beginning users.
-	i[3456]86)
+	i[34567]86)
 	  basic_machine=$basic_machine-pc
 	  ;;
 	# Object if more than one company name word.
@@ -199,30 +203,32 @@ case $basic_machine in
 		exit 1
 		;;
 	# Recognize the basic CPU types with company name.
-	vax-* | tahoe-* | i[3456]86-* | i860-* | m32r-* | m68k-* | m68000-* \
+	# FIXME: clean up the formatting here.
+	vax-* | tahoe-* | i[34567]86-* | i860-* | ia64-* | m32r-* | m68k-* | m68000-* \
 	      | m88k-* | sparc-* | ns32k-* | fx80-* | arc-* | arm-* | c[123]* \
 	      | mips-* | pyramid-* | tron-* | a29k-* | romp-* | rs6000-* \
-	      | power-* | none-* | 580-* | cray2-* | h8300-* | i960-* \
-	      | xmp-* | ymp-* | hppa-* | hppa1.0-* | hppa1.1-* \
-	      | alpha-* | alphaev5-* | alphaev56-* | we32k-* | cydra-* \
-	      | ns16k-* | pn-* | np1-* | xps100-* | clipper-* | orion-* \
+	      | power-* | none-* | 580-* | cray2-* | h8300-* | h8500-* | i960-* \
+	      | xmp-* | ymp-* \
+	      | x86-* | ppcbe-* | mipsbe-* | mipsle-* | shbe-* | shle-* | armbe-* | armle-* \
+	      | hppa-* | hppa1.0-* | hppa1.1-* | hppa2.0-* | hppa2.0w-* \
+	      | hppa2.0n-* | hppa64-* \
+	      | alpha-* | alphaev[4-8]-* | alphaev56-* | alphapca5[67]-* \
+	      | alphaev6[78]-* \
+	      | we32k-* | cydra-* | ns16k-* | pn-* | np1-* | xps100-* \
+	      | clipper-* | orion-* \
 	      | sparclite-* | pdp11-* | sh-* | powerpc-* | powerpcle-* \
-	      | sparc64-* | mips64-* | mipsel-* \
+	      | sparc64-* | sparcv9-* | sparc86x-* | mips16-* | mips64-* | mipsel-* \
 	      | mips64el-* | mips64orion-* | mips64orionel-* \
-	      | mipstx39-* | mipstx39el-* \
-	      | f301-*)
-		;;
-	m88110-* | m680[01234]0-* | m683?2-* | m68360-* | z8k-* | h8500-* | d10v-*) # CYGNUS LOCAL
-		;;
-	mips64vr4300-* | mips64vr4300el-*) # CYGNUS LOCAL jsmith/vr4300
-		;;
-	mips64vr4100-* | mips64vr4100el-*) # CYGNUS LOCAL jsmith/vr4100
-		;;
-	mips16-*) # CYGNUS LOCAL krk/mips16
+	      | mips64vr4100-* | mips64vr4100el-* | mips64vr4300-* | mips64vr4300el-* \
+	      | mipstx39-* | mipstx39el-* | mcore-* \
+	      | f301-* | armv*-* | s390-* | sv1-* | t3e-* \
+	      | m88110-* | m680[01234]0-* | m683?2-* | m68360-* | z8k-* | d10v-* \
+	      | thumb-* | v850-* | d30v-* | tic30-* | c30-* | fr30-* \
+	      | bs2000-*)
 		;;
 	# Recognize the various machine names and aliases which stand
 	# for a CPU type and a company and sometimes even an OS.
-	386bsd)						# CYGNUS LOCAL
+	386bsd)
 		basic_machine=i386-unknown
 		os=-bsd
 		;;
@@ -232,11 +238,11 @@ case $basic_machine in
 	3b*)
 		basic_machine=we32k-att
 		;;
-	a29khif)					# CYGNUS LOCAL
+	a29khif)
 		basic_machine=a29k-amd
 		os=-udi
 		;;
-	adobe68k)					# CYGNUS LOCAL
+	adobe68k)
 		basic_machine=m68010-adobe
 		os=-scout
 		;;
@@ -269,7 +275,7 @@ case $basic_machine in
 		basic_machine=m68k-apollo
 		os=-sysv
 		;;
-	apollo68bsd)					# CYGNUS LOCAL
+	apollo68bsd)
 		basic_machine=m68k-apollo
 		os=-bsd
 		;;
@@ -349,7 +355,7 @@ case $basic_machine in
 	encore | umax | mmax)
 		basic_machine=ns32k-encore
 		;;
-	es1800 | OSE68k | ose68k | ose | OSE)		# CYGNUS LOCAL
+	es1800 | OSE68k | ose68k | ose | OSE)
 		basic_machine=m68k-ericsson
 		os=-ose
 		;;
@@ -371,11 +377,11 @@ case $basic_machine in
 		basic_machine=h8300-hitachi
 		os=-hms
 		;;
-	h8300xray)					# CYGNUS LOCAL
+	h8300xray)
 		basic_machine=h8300-hitachi
 		os=-xray
 		;;
-	h8500hms)					# CYGNUS LOCAL
+	h8500hms)
 		basic_machine=h8500-hitachi
 		os=-hms
 		;;
@@ -394,29 +400,30 @@ case $basic_machine in
 		basic_machine=m68k-hp
 		os=-hpux
 		;;
-        w89k-*)						# CYGNUS LOCAL
-                basic_machine=hppa1.1-winbond
-                os=-proelf
-                ;;
-        op50n-*)					# CYGNUS LOCAL
-                basic_machine=hppa1.1-oki
-                os=-proelf
-                ;;
-        op60c-*)					# CYGNUS LOCAL
-                basic_machine=hppa1.1-oki
-                os=-proelf
-                ;;
-        hppro)						# CYGNUS LOCAL
-                basic_machine=hppa1.1-hp
-                os=-proelf
-                ;;
+	hp3k9[0-9][0-9] | hp9[0-9][0-9])
+		basic_machine=hppa1.0-hp
+		;;
 	hp9k2[0-9][0-9] | hp9k31[0-9])
 		basic_machine=m68000-hp
 		;;
 	hp9k3[2-9][0-9])
 		basic_machine=m68k-hp
 		;;
-	hp9k7[0-9][0-9] | hp7[0-9][0-9] | hp9k8[0-9]7 | hp8[0-9]7)
+	hp9k6[0-9][0-9] | hp6[0-9][0-9])
+		basic_machine=hppa1.0-hp
+		;;
+	hp9k7[0-79][0-9] | hp7[0-79][0-9])
+		basic_machine=hppa1.1-hp
+		;;
+	hp9k78[0-9] | hp78[0-9])
+		# FIXME: really hppa2.0-hp
+		basic_machine=hppa1.1-hp
+		;;
+	hp9k8[67]1 | hp8[67]1 | hp9k80[24] | hp80[24] | hp9k8[78]9 | hp8[78]9 | hp9k893 | hp893)
+		# FIXME: really hppa2.0-hp
+		basic_machine=hppa1.1-hp
+		;;
+	hp9k8[0-9][13679] | hp8[0-9][13679])
 		basic_machine=hppa1.1-hp
 		;;
 	hp9k8[0-9][0-9] | hp8[0-9][0-9])
@@ -425,43 +432,50 @@ case $basic_machine in
 	hppa-next)
 		os=-nextstep3
 		;;
-	hppaosf)					# CYGNUS LOCAL
+	hppaosf)
 		basic_machine=hppa1.1-hp
 		os=-osf
 		;;
+	hppro)
+		basic_machine=hppa1.1-hp
+		os=-proelf
+		;;
 	i370-ibm* | ibm*)
 		basic_machine=i370-ibm
-		os=-mvs
 		;;
 # I'm not sure what "Sysv32" means.  Should this be sysv3.2?
-	i[3456]86v32)
+	i[34567]86v32)
 		basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'`
 		os=-sysv32
 		;;
-	i[3456]86v4*)
+	i[34567]86v4*)
 		basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'`
 		os=-sysv4
 		;;
-	i[3456]86v)
+	i[34567]86v)
 		basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'`
 		os=-sysv
 		;;
-	i[3456]86sol2)
+	i[34567]86sol2)
 		basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'`
 		os=-solaris2
 		;;
-	i386mach)					# CYGNUS LOCAL
+	i386mach)
 		basic_machine=i386-mach
 		os=-mach
 		;;
-	i386-vsta | vsta)				# CYGNUS LOCAL
+	i386-vsta | vsta)
 		basic_machine=i386-unknown
 		os=-vsta
 		;;
-	i386-go32 | go32)				# CYGNUS LOCAL
+	i386-go32 | go32)
 		basic_machine=i386-unknown
 		os=-go32
 		;;
+	i386-mingw32 | mingw32)
+		basic_machine=i386-unknown
+		os=-mingw32
+		;;
 	iris | iris4d)
 		basic_machine=mips-sgi
 		case $os in
@@ -490,6 +504,10 @@ case $basic_machine in
 	miniframe)
 		basic_machine=m68000-convergent
 		;;
+	*mint | -mint[0-9]* | *MiNT | *MiNT[0-9]*)
+		basic_machine=m68k-atari
+		os=-mint
+		;;
 	mipsel*-linux*)
 		basic_machine=mipsel-unknown
 		os=-linux-gnu
@@ -504,22 +522,34 @@ case $basic_machine in
 	mips3*)
 		basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`-unknown
 		;;
-	monitor)					# CYGNUS LOCAL
+	mmix*)
+		basic_machine=mmix-knuth
+		os=-mmixware
+		;;
+	monitor)
 		basic_machine=m68k-rom68k
 		os=-coff
 		;;
-	msdos)						# CYGNUS LOCAL
-		basic_machine=i386-unknown	
+	msdos)
+		basic_machine=i386-unknown
 		os=-msdos
 		;;
+	mvs)
+		basic_machine=i370-ibm
+		os=-mvs
+		;;
 	ncr3000)
 		basic_machine=i486-ncr
 		os=-sysv4
 		;;
 	netbsd386)
-		basic_machine=i386-unknown		# CYGNUS LOCAL
+		basic_machine=i386-unknown
 		os=-netbsd
 		;;
+	netwinder)
+		basic_machine=armv4l-rebel
+		os=-linux
+		;;
 	news | news700 | news800 | news900)
 		basic_machine=m68k-sony
 		os=-newsos
@@ -532,7 +562,7 @@ case $basic_machine in
 		basic_machine=mips-sony
 		os=-newsos
 		;;
-	necv70)						# CYGNUS LOCAL
+	necv70)
 		basic_machine=v70-nec
 		os=-sysv
 		;;
@@ -561,18 +591,25 @@ case $basic_machine in
 		basic_machine=i960-intel
 		os=-nindy
 		;;
-	mon960)						# CYGNUS LOCAL
+	mon960)
 		basic_machine=i960-intel
 		os=-mon960
 		;;
 	np1)
 		basic_machine=np1-gould
 		;;
-	OSE68000 | ose68000)				# CYGNUS LOCAL
+	nsr-tandem)
+		basic_machine=nsr-tandem
+		;;
+	op50n-* | op60c-*)
+		basic_machine=hppa1.1-oki
+		os=-proelf
+		;;
+	OSE68000 | ose68000)
 		basic_machine=m68000-ericsson
 		os=-ose
 		;;
-	os68k)						# CYGNUS LOCAL
+	os68k)
 		basic_machine=m68k-none
 		os=-os68k
 		;;
@@ -593,25 +630,23 @@ case $basic_machine in
         pc532 | pc532-*)
 		basic_machine=ns32k-pc532
 		;;
-	pentium | p5)
-		basic_machine=i586-intel
+	pentium | p5 | k5 | k6 | nexen)
+		basic_machine=i586-pc
 		;;
-	pentiumpro | p6)
-		basic_machine=i686-intel
+	pentiumpro | p6 | 6x86)
+		basic_machine=i686-pc
 		;;
-	pentium-* | p5-*)
+	pentiumii | pentium2)
+		basic_machine=i786-pc
+		;;
+	pentium-* | p5-* | k5-* | k6-* | nexen-*)
 		basic_machine=i586-`echo $basic_machine | sed 's/^[^-]*-//'`
 		;;
-	pentiumpro-* | p6-*)
+	pentiumpro-* | p6-* | 6x86-*)
 		basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'`
 		;;
-	k5)
-		# We don't have specific support for AMD's K5 yet, so just call it a Pentium
-		basic_machine=i586-amd
-		;;
-	nexen)
-		# We don't have specific support for Nexgen yet, so just call it a Pentium
-		basic_machine=i586-nexgen
+	pentiumii-* | pentium2-*)
+		basic_machine=i786-`echo $basic_machine | sed 's/^[^-]*-//'`
 		;;
 	pn)
 		basic_machine=pn-gould
@@ -631,7 +666,7 @@ case $basic_machine in
 	ps2)
 		basic_machine=i386-ibm
 		;;
-	rom68k)						# CYGNUS LOCAL
+	rom68k)
 		basic_machine=m68k-rom68k
 		os=-coff
 		;;
@@ -641,7 +676,7 @@ case $basic_machine in
 	rtpc | rtpc-*)
 		basic_machine=romp-ibm
 		;;
-	sa29200)					# CYGNUS LOCAL
+	sa29200)
 		basic_machine=a29k-amd
 		os=-udi
 		;;
@@ -652,7 +687,7 @@ case $basic_machine in
 		basic_machine=sh-hitachi
 		os=-hms
 		;;
-	sparclite-wrs)					# CYGNUS LOCAL
+	sparclite-wrs)
 		basic_machine=sparclite-wrs
 		os=-vxworks
 		;;
@@ -663,10 +698,10 @@ case $basic_machine in
 	spur)
 		basic_machine=spur-unknown
 		;;
-	st2000)						# CYGNUS LOCAL
+	st2000)
 		basic_machine=m68k-tandem
 		;;
-	stratus)					# CYGNUS LOCAL
+	stratus)
 		basic_machine=i860-stratus
 		os=-sysv4
 		;;
@@ -710,10 +745,18 @@ case $basic_machine in
 	sun386 | sun386i | roadrunner)
 		basic_machine=i386-sun
 		;;
+	sv1)
+		basic_machine=sv1-cray
+		os=-unicos
+		;;
 	symmetry)
 		basic_machine=i386-sequent
 		os=-dynix
 		;;
+	t3e)
+		basic_machine=t3e-cray
+		os=-unicos
+		;;
 	tx39)
 		basic_machine=mipstx39-unknown
 		;;
@@ -731,7 +774,7 @@ case $basic_machine in
 		basic_machine=a29k-nyu
 		os=-sym1
 		;;
-	v810 | necv810)					# CYGNUS LOCAL
+	v810 | necv810)
 		basic_machine=v810-nec
 		os=-none
 		;;
@@ -758,9 +801,13 @@ case $basic_machine in
 		basic_machine=a29k-wrs
 		os=-vxworks
 		;;
-	w65*)						# CYGNUS LOCAL
- 		basic_machine=w65-wdc
- 		os=-none
+	w65*)
+		basic_machine=w65-wdc
+		os=-none
+		;;
+	w89k-*)
+		basic_machine=hppa1.1-winbond
+		os=-proelf
 		;;
 	xmp)
 		basic_machine=xmp-cray
@@ -769,7 +816,7 @@ case $basic_machine in
         xps | xps100)
 		basic_machine=xps100-honeywell
 		;;
-	z8k-*-coff)					# CYGNUS LOCAL
+	z8k-*-coff)
 		basic_machine=z8k-unknown
 		os=-sim
 		;;
@@ -780,13 +827,13 @@ case $basic_machine in
 
 # Here we handle the default manufacturer of certain CPU types.  It is in
 # some cases the only manufacturer, in others, it is the most popular.
-	w89k)						# CYGNUS LOCAL
+	w89k)
 		basic_machine=hppa1.1-winbond
 		;;
-	op50n)						# CYGNUS LOCAL
+	op50n)
 		basic_machine=hppa1.1-oki
 		;;
-	op60c)						# CYGNUS LOCAL
+	op60c)
 		basic_machine=hppa1.1-oki
 		;;
 	mips)
@@ -811,7 +858,7 @@ case $basic_machine in
 	we32k)
 		basic_machine=we32k-att
 		;;
-	sparc)
+	sparc | sparcv9)
 		basic_machine=sparc-sun
 		;;
         cydra)
@@ -823,12 +870,16 @@ case $basic_machine in
 	orion105)
 		basic_machine=clipper-highlevel
 		;;
-	mac | mpw | mac-mpw)				# CYGNUS LOCAL
+	mac | mpw | mac-mpw)
 		basic_machine=m68k-apple
 		;;
-	pmac | pmac-mpw)				# CYGNUS LOCAL
+	pmac | pmac-mpw)
 		basic_machine=powerpc-apple
 		;;
+	c4x*)
+		basic_machine=c4x-none
+		os=-coff
+		;;
 	*)
 		echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2
 		exit 1
@@ -861,9 +912,12 @@ case $os in
 	-solaris)
 		os=-solaris2
 		;;
-	-unixware* | svr4*)
+	-svr4*)
 		os=-sysv4
 		;;
+	-unixware*)
+		os=-sysv4.2uw
+		;;
 	-gnu/linux*)
 		os=`echo $os | sed -e 's|gnu/linux|linux-gnu|'`
 		;;
@@ -879,22 +933,34 @@ case $os in
 	      | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \
 	      | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \
 	      | -hiux* | -386bsd* | -netbsd* | -openbsd* | -freebsd* | -riscix* \
-	      | -lynxos* | -bosx* | -nextstep* | -cxux* | -aout* | -elf* \
+	      | -lynxos* | -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \
 	      | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \
 	      | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \
-	      | -cygwin32* | -pe* | -psos* | -moss* | -proelf* | -rtems* \
-	      | -mingw32* | -linux-gnu* | -uxpv*)
+	      | -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \
+	      | -mingw32* | -linux-gnu* | -uxpv* | -beos* | -mpeix* | -udk* \
+	      | -interix* | -uwin* | -rhapsody* | -darwin* | -opened* \
+	      | -openstep* | -oskit*)
 	# Remember, each alternative MUST END IN *, to match a version number.
 		;;
-	# CYGNUS LOCAL
+	-qnx*)
+		case $basic_machine in
+		    x86-* | i[34567]86-*)
+			;;
+		    *)
+			os=-nto$os
+			;;
+		esac
+		;;
+	-nto*)
+		os=-nto-qnx
+		;;
 	-sim | -es1800* | -hms* | -xray | -os68k* | -none* | -v88r* \
-	      | -windows* | -osx | -abug |  -netware* | -os9* | -beos* \
-	      | -macos* | -mpw* | -magic* | -mon960* | -lnews* )
+	      | -windows* | -osx | -abug | -netware* | -os9* | -beos* \
+	      | -macos* | -mpw* | -magic* | -mmixware* | -mon960* | -lnews*)
 		;;
 	-mac*)
 		os=`echo $os | sed -e 's|mac|macos|'`
 		;;
-	# END CYGNUS LOCAL
 	-linux*)
 		os=`echo $os | sed -e 's|linux|linux-gnu|'`
 		;;
@@ -904,6 +970,12 @@ case $os in
 	-sunos6*)
 		os=`echo $os | sed -e 's|sunos6|solaris3|'`
 		;;
+	-opened*)
+		os=-openedition
+		;;
+	-wince*)
+		os=-wince
+		;;
 	-osfrose*)
 		os=-osfrose
 		;;
@@ -919,7 +991,7 @@ case $os in
 	-acis*)
 		os=-aos
 		;;
-	-386bsd)					# CYGNUS LOCAL
+	-386bsd)
 		os=-bsd
 		;;
 	-ctix* | -uts*)
@@ -928,6 +1000,9 @@ case $os in
 	-ns2 )
 	        os=-nextstep2
 		;;
+	-nsk)
+		os=-nsk
+		;;
 	# Preserve the version number of sinix5.
 	-sinix5.*)
 		os=`echo $os | sed -e 's|sinix|sysv|'`
@@ -953,15 +1028,18 @@ case $os in
 	# This must come after -sysvr4.
 	-sysv*)
 		;;
-	-ose*)						# CYGNUS LOCAL
+	-ose*)
 		os=-ose
 		;;
-	-es1800*)					# CYGNUS LOCAL
+	-es1800*)
 		os=-ose
 		;;
 	-xenix)
 		os=-xenix
 		;;
+        -*mint | -*MiNT)
+	        os=-mint
+		;;
 	-none)
 		;;
 	*)
@@ -987,6 +1065,9 @@ case $basic_machine in
 	*-acorn)
 		os=-riscix1.2
 		;;
+	arm*-rebel)
+		os=-linux
+		;;
 	arm*-semi)
 		os=-aout
 		;;
@@ -1008,34 +1089,34 @@ case $basic_machine in
 		# default.
 		# os=-sunos4
 		;;
-	m68*-cisco)					# CYGNUS LOCAL
+	m68*-cisco)
 		os=-aout
 		;;
-	mips*-cisco)					# CYGNUS LOCAL
+	mips*-cisco)
+		os=-elf
+		;;
+	mips*-*)
 		os=-elf
 		;;
-        mips*-*)                                        # CYGNUS LOCAL
-                os=-elf
-                ;;
 	*-tti)	# must be before sparc entry or we get the wrong os.
 		os=-sysv3
 		;;
 	sparc-* | *-sun)
 		os=-sunos4.1.1
 		;;
-	*-be)						# CYGNUS LOCAL
+	*-be)
 		os=-beos
 		;;
 	*-ibm)
 		os=-aix
 		;;
-	*-wec)						# CYGNUS LOCAL
+	*-wec)
 		os=-proelf
 		;;
-	*-winbond)					# CYGNUS LOCAL
+	*-winbond)
 		os=-proelf
 		;;
-	*-oki)						# CYGNUS LOCAL
+	*-oki)
 		os=-proelf
 		;;
 	*-hp)
@@ -1101,15 +1182,18 @@ case $basic_machine in
 	f301-fujitsu)
 		os=-uxpv
 		;;
-	*-rom68k)					# CYGNUS LOCAL
+	*-rom68k)
 		os=-coff
 		;;
-	*-*bug)						# CYGNUS LOCAL
+	*-*bug)
 		os=-coff
 		;;
-	*-apple)					# CYGNUS LOCAL
+	*-apple)
 		os=-macos
 		;;
+	*-atari*)
+		os=-mint
+		;;
 	*)
 		os=-none
 		;;
@@ -1131,12 +1215,15 @@ case $basic_machine in
 			-aix*)
 				vendor=ibm
 				;;
-			-beos*)						# CYGNUS LOCAL
+			-beos*)
 				vendor=be
 				;;
 			-hpux*)
 				vendor=hp
 				;;
+			-mpeix*)
+				vendor=hp
+				;;
 			-hiux*)
 				vendor=hitachi
 				;;
@@ -1152,7 +1239,7 @@ case $basic_machine in
 			-genix*)
 				vendor=ns
 				;;
-			-mvs*)
+			-mvs* | -opened*)
 				vendor=ibm
 				;;
 			-ptx*)
@@ -1164,12 +1251,15 @@ case $basic_machine in
 			-aux*)
 				vendor=apple
 				;;
-			-hms*)				# CYGNUS LOCAL
+			-hms*)
 				vendor=hitachi
 				;;
-			-mpw* | -macos*)		# CYGNUS LOCAL
+			-mpw* | -macos*)
 				vendor=apple
 				;;
+			-*mint | -*MiNT)
+				vendor=atari
+				;;
 		esac
 		basic_machine=`echo $basic_machine | sed "s/unknown/$vendor/"`
 		;;

configure.in

@@ -1,33 +1,214 @@
 dnl Process this file with autoconf to produce a configure script.
 AC_INIT(netlist.h)
+AC_CONFIG_HEADER(config.h)
 
 dnl Checks for programs.
 AC_PROG_CC
 AC_PROG_CXX
 AC_CHECK_TOOL(STRIP, strip, true)
-AC_CHECK_HEADERS(getopt.h)
-AC_PROG_INSTALL
-AC_CHECK_LIB(dl,main,[DLLIB=-ldl])
+AC_CHECK_PROGS(XGPERF,gperf,none)
+if test "$XGPERF" = "none"
+then
+        echo "*** Error: No suitable gperf found. ***"
+        echo "    Please install the 'gperf' package."
+        exit 1
+fi
+
+AC_CHECK_PROGS(LEX,flex,none)
+if test "$LEX" = "none"
+then
+	echo "*** Error: No suitable flex found. ***"
+        echo "    Please install the 'flex' package."
+        exit 1
+fi
+
+AC_CHECK_PROGS(YACC,bison,none)
+if test "$YACC" = "none"
+then
+	echo "*** Error: No suitable bison found. ***"
+        echo "    Please install the 'bison' package."
+        exit 1
+fi
+
+AC_LANG_CPLUSPLUS
+
+AC_CHECK_HEADERS(getopt.h malloc.h iosfwd sys/wait.h)
+
+AC_MSG_CHECKING(for sys/times)
+AC_TRY_LINK(
+#include <unistd.h>
+#include <sys/times.h>
+,{clock_t a = times(0)/sysconf(_SC_CLK_TCK);},
+do_times=yes
+AC_DEFINE(HAVE_TIMES,1),
+do_times=no
+)
+AC_MSG_RESULT($do_times)
+
+AC_CHECK_HEADER(ipal.h, HAVE_IPAL=yes, HAVE_IPAL=)
+AC_ARG_WITH(ipal,
+    [  --with-ipal             enable PAL target],
+if test "$with_ipal" = no; then
+       echo Disabling ipal support
+       HAVE_IPAL=
+fi
+)
+AC_SUBST(HAVE_IPAL)
+
+# --
+# Look for a dl library to use. First look for the standard dlopen
+# functions, and failing that look for the HP specific shl_load function.
+
+AC_CHECK_HEADERS(dlfcn.h dl.h, break)
+
+DLLIB=''
+AC_CHECK_LIB(dl,dlopen,[DLLIB=-ldl])
+if test -z "$DLLIB" ; then
+AC_CHECK_LIB(dld,shl_load,[DLLIB=-ldld])
+fi
 AC_SUBST(DLLIB)
+
+AC_PROG_INSTALL
+
+AC_LANG_C
+
 AC_CANONICAL_HOST
-$host
+# $host
+
+# The -fPIC flag is used to tell the compiler to make position
+# independent code. It is needed when making shared objects.
+
+AC_MSG_CHECKING("for flag to make position independent code")
+PICFLAG=-fPIC
+case "${host}" in
+
+     *-*-cygwin*)
+	PICFLAG=
+	;;
+
+     *-*-hpux*)
+	PICFLAG=+z
+	;;
+
+esac
+AC_SUBST(PICFLAG)
+AC_MSG_RESULT($PICFLAG)
+
+
+# mingw needs to link with libiberty.a, cygwin can tolerate it
+
+AC_MSG_CHECKING("for extra libs needed")
+EXTRALIBS=
+case "${host}" in
+     *-*-cygwin*)
+	EXTRALIBS="-liberty"
+	;;
+esac
+AC_SUBST(EXTRALIBS)
+AC_MSG_RESULT($EXTRALIBS)
+   
+# Darwin requires -no-cpp-precomp
+case "${host}" in
+    *-*-darwin*)
+	CPPFLAGS="-no-cpp-precomp"
+	CFLAGS="-no-cpp-precomp"
+	;;
+esac
+
+# The -rdynamic flag is used by iverilog when compiling the target,
+# to know how to export symbols of the main program to loadable modules
+# that are brought in by -ldl
+AC_MSG_CHECKING("for -rdynamic compiler flag")
+
+rdynamic=-rdynamic
+case "${host}" in
+
+    *-*-netbsd*)
+	rdynamic="-Wl,--export-dynamic"
+	;;
+
+    *-*-solaris*)
+	rdynamic=""
+	;;
+
+    *-*-cygwin*)
+	rdynamic=""
+	;;
+
+    *-*-hpux*)
+	rdynamic="-E"
+	;;
+
+    *-*-darwin*)
+	rdynamic="-Wl,-all_load"
+	strip_dynamic="-SX"
+	;;
+
+esac
+AC_SUBST(rdynamic)
+AC_MSG_RESULT($rdynamic)
+AC_SUBST(strip_dynamic)
+AC_MSG_RESULT($strip_dynamic)
+
+AC_MSG_CHECKING("for shared library link flag")
+shared=-shared
+case "${host}" in
+
+     *-*-cygwin*)
+        shared="-shared -Wl,--enable-auto-image-base"
+	;;
+
+     *-*-hpux*)
+	shared="-b"
+	;;
+
+     *-*-darwin1.[0123])
+	shared="-bundle -undefined suppress"
+	;;
+
+     *-*-darwin*)
+	shared="-bundle -undefined suppress -flat_namespace"
+	;;
+esac
+
+AC_SUBST(shared)
+AC_MSG_RESULT($shared)
 
 #######################
-## test for underscores. The vpi module loader in vvm needs to know this
+## test for underscores. The vpi module loader needs to know this
 ## in order to know the name of the start symbol for the .vpi module.
 #######################
 
+AC_CYGWIN
+AC_EXEEXT
+AC_MINGW32
+
+
+WIN32=no
+AC_MSG_CHECKING("Checking for windows")
+if test "$CYGWIN" = "yes" -o "$MINGW32" = "yes"
+then
+    WIN32=yes
+fi
+
+AC_SUBST(MINGW32)
+AC_SUBST(WIN32)
+AC_MSG_RESULT($WIN32)
+AC_SUBST(EXEEXT)
+
+
 AC_MSG_CHECKING("for leading and/or trailing underscores")
 cat << EOF > underscore.c
        void underscore(void){}
 EOF
-$CC -c underscore.c > /dev/null 2>&1
+
+$CC $shared -c underscore.c > /dev/null 2>&1
 
 CC_LEADING_UNDERSCORE=no
 CC_TRAILING_UNDERSCORE=no
 
 output=`nm underscore.o|grep _underscore 2>&1`
-if test ! -z "$output"; then
+if test ! -z "$output" -a "$CYGWIN" != "yes" -a "$MINGW32" != "yes"; then
   CC_LEADING_UNDERSCORE=yes
   AC_DEFINE(NEED_LU)
 fi
@@ -53,26 +234,27 @@ AC_MSG_RESULT("$CC_LEADING_UNDERSCORE $CC_TRAILING_UNDERSCORE")
 ## end of test for underscores
 #######################
 
-# The -rdynamic flag is used by iverilog when compiling the target,
-# to know how to export symbols of the main program to loadable modules
-# that are brought in by -ldl
-AC_MSG_CHECKING("for -rdynamic compiler flag")
-
-rdynamic=-rdynamic
+AC_MSG_CHECKING("for ident support in C compiler")
+ident_support='-DHAVE_CVS_IDENT=1'
 case "${host}" in
 
-    *-*-netbsd*)
-	rdynamic="-Wl,--export-dynamic"
+     *-*-cygwin*)
+	ident_support=
 	;;
 
-    *-*-solaris*)
-	rdynamic=""
+     *-*-darwin*)
+	ident_support=
 	;;
 
+     *-*-machten*)
+	ident_support=
+	;;
 esac
 
-AC_DEFINE_UNQUOTED(RDYNAMIC,"${rdynamic}")
+AC_SUBST(ident_support)
+AC_MSG_RESULT($ident_support)
 
-AC_MSG_RESULT("$RDYNAMIC")
 
-AC_OUTPUT(Makefile vpi/Makefile ivlpp/Makefile vvm/Makefile)
+AC_CONFIG_SUBDIRS(vvp tgt-vvp tgt-fpga libveriuser)
+
+AC_OUTPUT(Makefile vpi/Makefile ivlpp/Makefile driver/Makefile driver-vpi/Makefile tgt-null/Makefile tgt-stub/Makefile tgt-verilog/Makefile tgt-pal/Makefile)

cygwin.txt

@@ -0,0 +1,29 @@
+
+This file describes the build procedure under cygwin32 (Windows 95/98/NT/2K)
+----------------------------------------------------------------------------
+To build using cygwin:
+
+Prerequisites:
+
+ o Latest net release (1.1.4) of cygwin (sources.redhat.com/cygwin)
+
+Procedure:
+ o Get the source code - see the main icarus verilog page for how to 
+   do this
+ o cd to the verilog directory
+ o autoconf.sh
+ o ./configure
+ o make
+ o make install
+
+That's all that's needed.  
+
+To build your own extensions - just include vpi_user.h and link with
+a command like this:
+
+ $(CC) -shared -o <dllname> <objects> -Wl,--enable-auto-image-base -L../vvm -lvvm -lvpip
+
+ - Venkat Iyer <[email protected]>
+
+
+

design_dump.cc

@@ -16,10 +16,12 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: design_dump.cc,v 1.86 2000/06/13 03:24:48 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: design_dump.cc,v 1.135 2002/10/23 01:47:17 steve Exp $"
 #endif
 
+# include "config.h"
+
 /*
  * This file contains all the dump methods of the netlist classes.
  */
@@ -73,34 +75,55 @@ void NetNet::dump_net(ostream&o, unsigned ind) const
 	    pin_count() << "]";
       if (local_flag_)
 	    o << " (local)";
-      o << " (eref=" << get_eref() << ")";
-      if (scope_)
-	    o << " scope=" << scope_->name();
+      if (signed_)
+	    o << " signed";
+      switch (port_type_) {
+	  case NetNet::NOT_A_PORT:
+	    break;
+	  case NetNet::PIMPLICIT:
+	    o << " implicit-port?";
+	    break;
+	  case NetNet::PINPUT:
+	    o << " input";
+	    break;
+	  case NetNet::POUTPUT:
+	    o << " output";
+	    break;
+	  case NetNet::PINOUT:
+	    o << " inout";
+	    break;
+      }
+      o << " (eref=" << peek_eref() << ", lref=" << peek_lref() << ")";
+      if (scope())
+	    o << " scope=" << scope()->name();
       o << " #(" << rise_time() << "," << fall_time() << "," <<
 	    decay_time() << ") init=";
       for (unsigned idx = pin_count() ;  idx > 0 ;  idx -= 1)
-	    o << ivalue_[idx-1];
-      o << endl;
+	    o << pin(idx-1).get_init();
+
+      o << " (";
+      for (unsigned idx = pin_count() ;  idx > 0 ;  idx -= 1)
+	    o << pin(idx-1).nexus()->get_init();
+      o << ")" << endl;
 
       for (unsigned idx = 0 ;  idx < pin_count() ;  idx += 1) {
 	    if (! pin(idx).is_linked())
 		  continue;
 
-	    o << setw(ind+4) << "" << "[" << idx << "]:";
-
-	    unsigned cpin;
-	    const NetObj*cur;
-	    for (pin(idx).next_link(cur, cpin)
-		       ; (cur != this) || (cpin != idx)
-		       ; cur->pin(cpin).next_link(cur, cpin)) {
-
-		  o << " " << cur->name() << "[" << cpin << "]";
-	    }
-	    o << endl;
+	    const Nexus*nex = pin(idx).nexus();
+	    o << setw(ind+4) << "" << "[" << idx << "]: " << nex
+	      << " " << nex->name() << endl;
       }
       dump_obj_attr(o, ind+4);
 }
 
+void NetSubnet::dump_net(ostream&o, unsigned ind) const
+{
+      o << setw(ind) << "" << "** " << name() << " is a NetSubnet **"
+	<< endl;
+      NetNet::dump_net(o, ind);
+}
+
 void NetMemory::dump(ostream&o, unsigned ind) const
 {
       o << setw(ind) << ""  << name_ << "[" << width_ << "] " <<
@@ -144,28 +167,23 @@ void NetObj::dump_node_pins(ostream&o, unsigned ind) const
 	    }
 
 	    o << " (" << pin(idx).drive0() << "0 "
-	      << pin(idx).drive1() << "1):";
+	      << pin(idx).drive1() << "1): ";
 
-	    unsigned cpin;
-	    const NetObj*cur;
-	    for (pin(idx).next_link(cur, cpin)
-		       ; (cur != this) || (cpin != idx)
-		       ; cur->pin(cpin).next_link(cur, cpin)) {
-
-		  const NetNet*sig = dynamic_cast<const NetNet*>(cur);
-		  if (sig) o << " " << sig->name() << "[" << cpin << "]";
+	    if (pin(idx).is_linked()) {
+		  const Nexus*nex = pin(idx).nexus();
+		  o << nex << " " << nex->name();
 	    }
 	    o << endl;
+
       }
 }
 
 void NetObj::dump_obj_attr(ostream&o, unsigned ind) const
 {
-      for (map<string,string>::const_iterator idx = attributes_.begin()
-		 ; idx != attributes_.end()
-		 ; idx ++) {
-	    o << setw(ind) << "" << (*idx).first << " = \"" <<
-		  (*idx).second << "\"" << endl;
+      unsigned idx;
+      for (idx = 0 ;  idx < attr_cnt() ;  idx += 1) {
+	    o << setw(ind) << "" << attr_key(idx) << " = \"" <<
+		  attr_value(idx) << "\"" << endl;
       }
 }
 
@@ -220,34 +238,18 @@ void NetMult::dump_node(ostream&o, unsigned ind) const
 
 void NetMux::dump_node(ostream&o, unsigned ind) const
 {
-      o << setw(ind) << "" << "Multiplexer (NetMux): " << name() << endl;
+      o << setw(ind) << "" << "Multiplexer (NetMux): " << name()
+	<< " scope=" << scope()->name() << endl;
       dump_node_pins(o, ind+4);
       dump_obj_attr(o, ind+4);
 }
 
-void NetAssign::dump_node(ostream&o, unsigned ind) const
-{
-      o << setw(ind) << "" << "Procedural assign (NetAssign): " << name();
-      if (bmux())
-	    o << "[" << *bmux() << "]";
-      o << " = " << *rval() << endl;
-      dump_node_pins(o, ind+4);
-}
-
-void NetAssignNB::dump_node(ostream&o, unsigned ind) const
-{
-      if (bmux())
-	    o << setw(ind) << "" << "Procedural NB assign (NetAssignNB): "
-	      << name() << "[" << *bmux() << "] <= " << *rval() << endl;
-      else
-	    o << setw(ind) << "" << "Procedural NB assign (NetAssignNB): "
-	      << name() << " <= " << *rval() << endl;
-      dump_node_pins(o, ind+4);
-}
-
 void NetBUFZ::dump_node(ostream&o, unsigned ind) const
 {
-      o << setw(ind) << "" << "NetBUFZ: " << name() << endl;
+      o << setw(ind) << "" << "NetBUFZ: " << name()
+	<< " scope=" << (scope()? scope()->name() : "")
+	<< " delay=(" << rise_time() << "," << fall_time() << "," <<
+	    decay_time() << ")" << endl;
       dump_node_pins(o, ind+4);
 }
 
@@ -268,7 +270,10 @@ void NetConst::dump_node(ostream&o, unsigned ind) const
 
 void NetFF::dump_node(ostream&o, unsigned ind) const
 {
-      o << setw(ind) << "" << "LPM_FF: " << name() << endl;
+      o << setw(ind) << "" << "LPM_FF: " << name()
+	<< " scope=" << (scope()? scope()->name() : "")
+	<< " aset_value=" << aset_value_ << endl;
+
       dump_node_pins(o, ind+4);
       dump_obj_attr(o, ind+4);
 }
@@ -292,15 +297,39 @@ void NetLogic::dump_node(ostream&o, unsigned ind) const
 	  case NAND:
 	    o << "nand";
 	    break;
+	  case NMOS:
+	    o << "nmos";
+	    break;
 	  case NOR:
 	    o << "nor";
 	    break;
 	  case NOT:
 	    o << "not";
 	    break;
+	  case NOTIF0:
+	    o << "notif0";
+	    break;
+	  case NOTIF1:
+	    o << "notif1";
+	    break;
 	  case OR:
 	    o << "or";
 	    break;
+	  case PULLDOWN:
+	    o << "pulldown";
+	    break;
+	  case PULLUP:
+	    o << "pullup";
+	    break;
+	  case RNMOS:
+	    o << "rnmos";
+	    break;
+	  case RPMOS:
+	    o << "rpmos";
+	    break;
+	  case PMOS:
+	    o << "pmos";
+	    break;
 	  case XNOR:
 	    o << "xnor";
 	    break;
@@ -310,12 +339,20 @@ void NetLogic::dump_node(ostream&o, unsigned ind) const
       }
       o << " #(" << rise_time()
 	<< "," << fall_time() << "," << decay_time() << ") " << name()
+	<< " scope=" << (scope()? scope()->name() : "")
 	<< endl;
 
       dump_node_pins(o, ind+4);
       dump_obj_attr(o, ind+4);
 }
 
+void NetModulo::dump_node(ostream&o, unsigned ind) const
+{
+      o << setw(ind) << "" << "NET_MODULO (NetModulo): " << name() << endl;
+      dump_node_pins(o, ind+4);
+      dump_obj_attr(o, ind+4);
+}
+
 void NetRamDq::dump_node(ostream&o, unsigned ind) const
 {
       o << setw(ind) << "" << "LPM_RAM_DQ (" << mem_->name() << "): "
@@ -324,12 +361,21 @@ void NetRamDq::dump_node(ostream&o, unsigned ind) const
       dump_obj_attr(o, ind+4);
 }
 
+void NetUserFunc::dump_node(ostream&o, unsigned ind) const
+{
+      o << setw(ind) << "" << def_->name() << "(";
+      o << ")" << endl;
+      dump_node_pins(o, ind+4);
+      dump_obj_attr(o, ind+4);
+}
+
 void NetTaskDef::dump(ostream&o, unsigned ind) const
 {
       o << setw(ind) << "" << "task " << name_ << ";" << endl;
 
       for (unsigned idx = 0 ;  idx < ports_.count() ;  idx += 1) {
 	    o << setw(ind+4) << "";
+	    assert(ports_[idx]);
 	    switch (ports_[idx]->port_type()) {
 		case NetNet::PINPUT:
 		  o << "input ";
@@ -352,77 +398,12 @@ void NetTaskDef::dump(ostream&o, unsigned ind) const
       o << setw(ind) << "" << "endtask" << endl;
 }
 
-void NetUDP::dump_sequ_(ostream&o, unsigned ind) const
-{
-      string tmp = "";
-      for (unsigned idx = 0 ;  idx < ind ;  idx += 1)
-	    tmp += " ";
-
-      o << tmp << "Sequential UDP" << " #(" << rise_time() <<
-	    "," << fall_time() << "," << decay_time() << ") " << name() <<
-	    endl;
-
-      for (FSM_::const_iterator ent = fsm_.begin()
-		 ; ent != fsm_.end() ;  ent++) {
-	    o << setw(ind+6) << "" << (*ent).first << " -->";
-
-	    state_t_*st = (*ent).second;
-	    assert((*ent).first[0] == st->out);
-	    for (unsigned idx = 1 ;  idx < pin_count() ;  idx += 1) {
-		  string tmp = (*ent).first;
-		  if (st->pins[idx].zer) {
-			tmp[0] = st->pins[idx].zer->out;
-			tmp[idx] = '0';
-			o << " " << tmp;
-		  }
-
-		  if (st->pins[idx].one) {
-			tmp[0] = st->pins[idx].one->out;
-			tmp[idx] = '1';
-			o << " " << tmp;
-		  }
-
-		  if (st->pins[idx].xxx) {
-			tmp[0] = st->pins[idx].xxx->out;
-			tmp[idx] = 'x';
-			o << " " << tmp;
-		  }
-	    }
-
-	    o << endl;
-      }
-
-      o << setw(ind+6) << ""  << "initial value == " << init_ << endl;
-
-      dump_node_pins(o, ind+4);
-      dump_obj_attr(o, ind+4);
-}
-
-void NetUDP::dump_comb_(ostream&o, unsigned ind) const
-{
-      assert(0);
-}
-
 void NetUDP::dump_node(ostream&o, unsigned ind) const
 {
-      if (sequential_)
-	    dump_sequ_(o, ind);
-      else
-	    dump_comb_(o, ind);
-}
-
-void NetUDP_COMB::dump_node(ostream&o, unsigned ind) const
-{
-      o << setw(ind) << "" << "Combinational primitive: ";
+      o << setw(ind) << "" << "UDP (" << udp_name() << "): ";
       o << " #(" << rise_time() << "," << fall_time() << "," << decay_time() <<
 	    ") " << name() << endl;
 
-      for (map<string,char>::const_iterator ent = cm_.begin()
-		 ; ent != cm_.end() ;  ent++) {
-	    o << setw(ind+6) << "" << (*ent).first << " --> " <<
-		  (*ent).second << endl;
-      }
-
       dump_node_pins(o, ind+4);
       dump_obj_attr(o, ind+4);
 }
@@ -431,77 +412,94 @@ void NetProcTop::dump(ostream&o, unsigned ind) const
 {
       switch (type_) {
 	  case NetProcTop::KINITIAL:
-	    o << "initial  /* " << get_line() << " */" << endl;
+	    o << "initial  /* " << get_line() << " in "
+	      << scope_->name() << " */" << endl;
 	    break;
 	  case NetProcTop::KALWAYS:
-	    o << "always  /* " << get_line() << " */" << endl;
+	    o << "always  /* " << get_line() << " in "
+	      << scope_->name() << " */" << endl;
 	    break;
       }
 
+      for (unsigned idx = 0 ;  idx < attr_cnt() ;  idx += 1) {
+	    o << setw(ind+2) << "" << "(* " << attr_key(idx) << " = "
+	      << attr_value(idx) << " *)" << endl;
+      }
+
       statement_->dump(o, ind+2);
 }
 
+void NetAssign_::dump_lval(ostream&o) const
+{
+      if (sig_) {
+	    o << sig_->name();
+	    if (bmux_) {
+		  o << "[" << *bmux_ << "]";
+
+	    } else {
+		  o << "[" << (loff_+lwid_-1) << ":" << loff_ << "]";
+	    }
+      } else if (mem_) {
+	    // Is there an obvious way to flag memories in the dump
+	    // as different from the _real_ bit mux case?
+	    // o << "**memory**";
+	    o << mem_->name() << "[";
+	    if (bmux_) o << *bmux_;
+	      else     o << "**oops**";
+	    o << "]";
+      } else {
+	    o << "";
+      }
+}
+
+void NetAssignBase::dump_lval(ostream&o) const
+{
+      o << "{";
+      lval_->dump_lval(o);
+
+      for (NetAssign_*cur = lval_->more ;  cur ;  cur = cur->more) {
+	    o << ", ";
+	    cur->dump_lval(o);
+      }
+
+      o << "}";
+}
+
 /* Dump an assignment statement */
 void NetAssign::dump(ostream&o, unsigned ind) const
 {
       o << setw(ind) << "";
+      dump_lval(o);
 
-      if (bmux()) {
-	    o << name() << "[" << *bmux() << "] = ";
-	    if (rise_time())
-		  o << "#" << rise_time() << " ";
-	    o << *rval() << ";" << endl;
-
-      } else {
-	    o << name() << " = ";
-	    if (rise_time())
-		  o << "#" << rise_time() << " ";
-	    o << *rval() << ";" << endl;
-      }
+      o << " = ";
+#if 0
+      if (l_val(0)->rise_time())
+	    o << "#" << l_val(0)->rise_time() << " ";
+#endif
+      o << *rval() << ";" << endl;
 }
 
 void NetAssignNB::dump(ostream&o, unsigned ind) const
 {
       o << setw(ind) << "";
+      dump_lval(o);
 
-      if (bmux()) {
-	    o << name() << "[" << *bmux() << "] <= ";
-	    if (rise_time())
-		  o << "#" << rise_time() << " ";
-	    o << *rval() << ";" << endl;
+      o << " <= ";
+#if 0
+      if (l_val(0)->rise_time())
+	    o << "#" << l_val(0)->rise_time() << " ";
+#endif
+      o << *rval() << ";" << endl;
 
-      } else {
-	    o << name() << " <= ";
-	    if (rise_time())
-		  o << "#" << rise_time() << " ";
-	    o << *rval() << ";" << endl;
-      }
-}
-
-void NetAssignMem::dump(ostream&o, unsigned ind) const
-{
-      o << setw(ind) << "";
-      o << "/* " << get_line() << " */" << endl;
-      o << setw(ind) << "";
-      o << memory()->name() << "[" << *index() << "] = ";
-      rval()->dump(o);
-      o << ";" << endl;
-}
-
-void NetAssignMemNB::dump(ostream&o, unsigned ind) const
-{
-      o << setw(ind) << "";
-      o << "/* " << get_line() << " */" << endl;
-      o << setw(ind) << "";
-      o << memory()->name() << "[" << *index() << "] <= ";
-      rval()->dump(o);
-      o << ";" << endl;
 }
 
 /* Dump a block statement */
 void NetBlock::dump(ostream&o, unsigned ind) const
 {
-      o << setw(ind) << "" << type_ << endl;
+      o << setw(ind) << "" << type_;
+      if (subscope_)
+	    o << " : " << subscope_->name();
+      o << endl;
 
       if (last_) {
 	    const NetProc*cur = last_;
@@ -573,6 +571,12 @@ void NetDeassign::dump(ostream&o, unsigned ind) const
 	<< "/* " << get_line() << " */" << endl;
 }
 
+void NetDisable::dump(ostream&o, unsigned ind) const
+{
+      o << setw(ind) << "" << "disable " << target_->name() << "; "
+	<< "/* " << get_line() << " */" << endl;
+}
+
 void NetEvProbe::dump_node(ostream&o, unsigned ind) const
 {
       o << setw(ind) << "";
@@ -602,10 +606,10 @@ void NetEvTrig::dump(ostream&o, unsigned ind) const
 void NetEvWait::dump(ostream&o, unsigned ind) const
 {
       assert(nevents() > 0);
-      o << setw(ind) <<"" << "@(" << event(0)->name();
+      o << setw(ind) <<"" << "@(" << event(0)->full_name();
 
       for (unsigned idx = 1 ;  idx < nevents() ;  idx += 1)
-	    o << " or " << event(idx)->name();
+	    o << " or " << event(idx)->full_name();
 
       o << ")  // " << get_line() << endl;
 
@@ -638,7 +642,13 @@ void NetFuncDef::dump(ostream&o, unsigned ind) const
 
 void NetPDelay::dump(ostream&o, unsigned ind) const
 {
-      o << setw(ind) << "" << "#" << delay_;
+      if (expr_) {
+	    o << setw(ind) << "" << "#" << *expr_;
+
+      } else {
+	    o << setw(ind) << "" << "#" << delay_;
+      }
+
       if (statement_) {
 	    o << endl;
 	    statement_->dump(o, ind+2);
@@ -649,8 +659,12 @@ void NetPDelay::dump(ostream&o, unsigned ind) const
 
 void NetRelease::dump(ostream&o, unsigned ind) const
 {
-      o << setw(ind) << "" << "release " << lval_->name() << "; "
-	<< "/* " << get_line() << " */" << endl;
+      if (lval_)
+	    o << setw(ind) << "" << "release " << lval_->name() << "; "
+	      << "/* " << get_line() << " */" << endl;
+      else
+	    o << setw(ind) << "" << "release (null); "
+	      << "/* " << get_line() << " */" << endl;
 }
 
 void NetRepeat::dump(ostream&o, unsigned ind) const
@@ -673,7 +687,7 @@ void NetScope::dump(ostream&o) const
 	    o << " function";
 	    break;
 	  case MODULE:
-	    o << " module";
+	    o << " module <" << (module_name_? module_name_ : "") << ">";
 	    break;
 	  case TASK:
 	    o << " task";
@@ -681,25 +695,37 @@ void NetScope::dump(ostream&o) const
       }
       o << endl;
 
+      o << "    timescale = 10e" << time_unit() << " / 10e"
+	<< time_precision() << endl;
+
 	/* Dump the parameters for this scope. */
       {
-	    map<string,NetExpr*>::const_iterator pp;
+	    map<string,param_expr_t>::const_iterator pp;
 	    for (pp = parameters_.begin()
 		       ; pp != parameters_.end() ;  pp ++) {
-		  o << "    parameter " << (*pp).first << " = "  <<
-			*(*pp).second << ";" << endl;
+		  o << "    parameter ";
+
+		  if ((*pp).second.signed_flag)
+			o << "signed ";
+
+		  if ((*pp).second.msb)
+			o << "[" << *(*pp).second.msb
+			  << ":" << *(*pp).second.lsb << "] ";
+
+		  o << (*pp).first << " = "  <<
+			*(*pp).second.expr << ";" << endl;
 	    }
 
 	    for (pp = localparams_.begin()
 		       ; pp != localparams_.end() ;  pp ++) {
 		  o << "    localparam " << (*pp).first << " = "  <<
-			*(*pp).second << ";" << endl;
+			*(*pp).second.expr << ";" << endl;
 	    }
       }
 
 	/* Dump the saved defparam assignments here. */
       {
-	    map<string,NetExpr*>::const_iterator pp;
+	    map<hname_t,NetExpr*>::const_iterator pp;
 	    for (pp = defparams.begin()
 		       ; pp != defparams.end() ;  pp ++ ) {
 		  o << "    defparam " << (*pp).first << " = " <<
@@ -709,8 +735,8 @@ void NetScope::dump(ostream&o) const
 
 	/* Dump the events in this scope. */
       for (NetEvent*cur = events_ ;  cur ;  cur = cur->snext_) {
-	    o << "    event " << cur->name() << "; "
-	      << "// " << cur->get_line() << endl;
+	    o << "    event " << cur->name() << "; nprobe="
+	      << cur->nprobe() << " // " << cur->get_line() << endl;
       }
 
 	// Dump the signals,
@@ -731,6 +757,15 @@ void NetScope::dump(ostream&o) const
 	    } while (cur != memories_->snext_);
       }
 
+      switch (type_) {
+	  case FUNC:
+	    func_def()->dump(o, 4);
+	    break;
+	  case TASK:
+	    task_def()->dump(o, 4);
+	    break;
+      }
+
 	/* Dump any sub-scopes. */
       for (NetScope*cur = sub_ ;  cur ;  cur = cur->sib_)
 	    cur->dump(o);
@@ -776,7 +811,7 @@ void NetProc::dump(ostream&o, unsigned ind) const
 /* Dump an expression that noone wrote a dump method for. */
 void NetExpr::dump(ostream&o) const
 {
-      o << "(?)";
+      o << "(?" << typeid(*this).name() << "?)";
 }
 
 void NetEBinary::dump(ostream&o) const
@@ -832,8 +867,12 @@ void NetEBinary::dump(ostream&o) const
 
 void NetEConcat::dump(ostream&o) const
 {
-      if (repeat_ != 1)
-	    o << repeat_;
+      if (repeat_calculated_) {
+	    if (repeat_value_ != 1)
+		  o << repeat_value_;
+      } else if (repeat_) {
+	    o << "<" << *repeat_ << ">";
+      }
 
       if (parms_[0])
 	    o << "{" << *parms_[0];
@@ -857,11 +896,6 @@ void NetEConst::dump(ostream&o) const
 	    o << value_;
 }
 
-void NetEIdent::dump(ostream&o) const
-{
-      o << name_;
-}
-
 void NetEScope::dump(ostream&o) const
 {
       o << "<scope=" << scope_->name() << ">";
@@ -879,10 +913,12 @@ void NetESFunc::dump(ostream&o) const
 
 void NetESignal::dump(ostream&o) const
 {
-      o << name();
+      if (has_sign())
+	    o << "+";
+      o << name() << "[" << msi_<<":"<<lsi_ << "]";
 }
 
-void NetESubSignal::dump(ostream&o) const
+void NetEBitSel::dump(ostream&o) const
 {
       sig_->dump(o);
       o << "[";
@@ -899,7 +935,10 @@ void NetEMemory::dump(ostream&o) const
 
 void NetEParam::dump(ostream&o) const
 {
-      o << "<" << scope_->name() << "." << name_ << ">";
+      if (scope_ != 0)
+	    o << "<" << scope_->name() << "." << name_ << ">";
+      else
+	    o << "<" << name_ << ">";
 }
 
 void NetETernary::dump(ostream&o) const
@@ -911,11 +950,12 @@ void NetETernary::dump(ostream&o) const
 void NetEUFunc::dump(ostream&o) const
 {
       o << name() << "(";
-      assert(parms_.count() > 0);
-      parms_[0]->dump(o);
-      for (unsigned idx = 1 ;  idx < parms_.count() ;  idx += 1) {
-	    o << ", ";
-	    parms_[idx]->dump(o);
+      if (parms_.count() > 0) {
+	    parms_[0]->dump(o);
+	    for (unsigned idx = 1 ;  idx < parms_.count() ;  idx += 1) {
+		  o << ", ";
+		  parms_[idx]->dump(o);
+	    }
       }
       o << ")";
 }
@@ -937,26 +977,11 @@ void NetEUnary::dump(ostream&o) const
 
 void Design::dump(ostream&o) const
 {
+      o << "DESIGN TIME PRECISION: 10e" << get_precision() << endl;
       o << "SCOPES:" << endl;
-      root_scope_->dump(o);
-
-      o << "ELABORATED FUNCTION DEFINITIONS:" << endl;
-      {
-	    map<string,NetFuncDef*>::const_iterator pp;
-	    for (pp = funcs_.begin()
-		       ; pp != funcs_.end() ; pp ++) {
-		  (*pp).second->dump(o, 0);
-	    }
-      }
-
-      o << "ELABORATED TASK DEFINITIONS:" << endl;
-      {
-	    map<string,NetTaskDef*>::const_iterator pp;
-	    for (pp = tasks_.begin()
-		       ; pp != tasks_.end() ; pp ++) {
-		  (*pp).second->dump(o, 0);
-	    }
-      }
+      for (list<NetScope*>::const_iterator scope = root_scopes_.begin(); 
+	   scope != root_scopes_.end(); scope++)
+	    (*scope)->dump(o);
 
       o << "ELABORATED NODES:" << endl;
 
@@ -979,6 +1004,203 @@ void Design::dump(ostream&o) const
 
 /*
  * $Log: design_dump.cc,v $
+ * Revision 1.135  2002/10/23 01:47:17  steve
+ *  Fix synth2 handling of aset/aclr signals where
+ *  flip-flops are split by begin-end blocks.
+ *
+ * Revision 1.134  2002/10/19 22:59:49  steve
+ *  Redo the parameter vector support to allow
+ *  parameter names in range expressions.
+ *
+ * Revision 1.133  2002/08/19 00:06:11  steve
+ *  Allow release to handle removal of target net.
+ *
+ * Revision 1.132  2002/08/13 05:35:00  steve
+ *  Do not elide named blocks.
+ *
+ * Revision 1.131  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.130  2002/08/04 18:28:14  steve
+ *  Do not use hierarchical names of memories to
+ *  generate vvp labels. -tdll target does not
+ *  used hierarchical name string to look up the
+ *  memory objects in the design.
+ *
+ * Revision 1.129  2002/06/19 04:20:03  steve
+ *  Remove NetTmp and add NetSubnet class.
+ *
+ * Revision 1.128  2002/06/14 21:38:41  steve
+ *  Fix expression width for repeat concatenations.
+ *
+ * Revision 1.127  2002/06/08 23:42:46  steve
+ *  Add NetRamDq synthsesis from memory l-values.
+ *
+ * Revision 1.126  2002/06/05 03:44:25  steve
+ *  Add support for memory words in l-value of
+ *  non-blocking assignments, and remove the special
+ *  NetAssignMem_ and NetAssignMemNB classes.
+ *
+ * Revision 1.125  2002/06/04 05:38:44  steve
+ *  Add support for memory words in l-value of
+ *  blocking assignments, and remove the special
+ *  NetAssignMem class.
+ *
+ * Revision 1.124  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
+ * Revision 1.123  2002/05/05 21:11:49  steve
+ *  Put off evaluation of concatenation repeat expresions
+ *  until after parameters are defined. This allows parms
+ *  to be used in repeat expresions.
+ *
+ *  Add the builtin $signed system function.
+ *
+ * Revision 1.122  2002/03/09 02:10:22  steve
+ *  Add the NetUserFunc netlist node.
+ *
+ * Revision 1.121  2001/12/31 00:03:05  steve
+ *  Include s indicator in dump of signed numbers.
+ *
+ * Revision 1.120  2001/12/03 04:47:14  steve
+ *  Parser and pform use hierarchical names as hname_t
+ *  objects instead of encoded strings.
+ *
+ * Revision 1.119  2001/11/19 01:46:38  steve
+ *  Print typename is fallback expression node dump.
+ *
+ * Revision 1.118  2001/10/19 21:53:24  steve
+ *  Support multiple root modules (Philip Blundell)
+ *
+ * Revision 1.117  2001/08/25 23:50:02  steve
+ *  Change the NetAssign_ class to refer to the signal
+ *  instead of link into the netlist. This is faster
+ *  and uses less space. Make the NetAssignNB carry
+ *  the delays instead of the NetAssign_ lval objects.
+ *
+ *  Change the vvp code generator to support multiple
+ *  l-values, i.e. concatenations of part selects.
+ *
+ * Revision 1.116  2001/07/27 04:51:44  steve
+ *  Handle part select expressions as variants of
+ *  NetESignal/IVL_EX_SIGNAL objects, instead of
+ *  creating new and useless temporary signals.
+ *
+ * Revision 1.115  2001/07/27 02:41:55  steve
+ *  Fix binding of dangling function ports. do not elide them.
+ *
+ * Revision 1.114  2001/07/25 03:10:48  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
+ * Revision 1.113  2001/04/29 20:19:10  steve
+ *  Add pullup and pulldown devices.
+ *
+ * Revision 1.112  2001/04/22 23:09:46  steve
+ *  More UDP consolidation from Stephan Boettcher.
+ *
+ * Revision 1.111  2001/02/17 05:13:36  steve
+ *  Check that the port really exists here.
+ *
+ * Revision 1.110  2001/01/18 03:16:35  steve
+ *  NetMux needs a scope. (PR#115)
+ *
+ * Revision 1.109  2001/01/13 22:20:08  steve
+ *  Parse parameters within nested scopes.
+ *
+ * Revision 1.108  2000/12/16 01:45:47  steve
+ *  Detect recursive instantiations (PR#2)
+ *
+ * Revision 1.107  2000/12/11 00:31:43  steve
+ *  Add support for signed reg variables,
+ *  simulate in t-vvm signed comparisons.
+ *
+ * Revision 1.106  2000/12/10 06:41:59  steve
+ *  Support delays on continuous assignment from idents. (PR#40)
+ *
+ * Revision 1.105  2000/12/04 17:37:03  steve
+ *  Add Attrib class for holding NetObj attributes.
+ *
+ * Revision 1.104  2000/11/11 01:52:09  steve
+ *  change set for support of nmos, pmos, rnmos, rpmos, notif0, and notif1
+ *  change set to correct behavior of bufif0 and bufif1
+ *  (Tim Leight)
+ *
+ *  Also includes fix for PR#27
+ *
+ * Revision 1.103  2000/11/11 00:03:36  steve
+ *  Add support for the t-dll backend grabing flip-flops.
+ *
+ * Revision 1.102  2000/11/04 06:36:24  steve
+ *  Apply sequential UDP rework from Stephan Boettcher  (PR#39)
+ *
+ * Revision 1.101  2000/10/28 00:51:41  steve
+ *  Add scope to threads in vvm, pass that scope
+ *  to vpi sysTaskFunc objects, and add vpi calls
+ *  to access that information.
+ *
+ *  $display displays scope in %m (PR#1)
+ *
+ * Revision 1.100  2000/10/07 19:45:42  steve
+ *  Put logic devices into scopes.
+ *
+ * Revision 1.99  2000/10/06 23:46:50  steve
+ *  ivl_target updates, including more complete
+ *  handling of ivl_nexus_t objects. Much reduced
+ *  dependencies on pointers to netlist objects.
+ *
+ * Revision 1.98  2000/09/26 01:35:42  steve
+ *  Remove the obsolete NetEIdent class.
+ *
+ * Revision 1.97  2000/09/17 21:26:15  steve
+ *  Add support for modulus (Eric Aardoom)
+ *
+ * Revision 1.96  2000/09/10 02:18:16  steve
+ *  elaborate complex l-values
+ *
+ * Revision 1.95  2000/09/02 20:54:20  steve
+ *  Rearrange NetAssign to make NetAssign_ separate.
+ *
+ * Revision 1.94  2000/07/30 18:25:43  steve
+ *  Rearrange task and function elaboration so that the
+ *  NetTaskDef and NetFuncDef functions are created during
+ *  signal enaboration, and carry these objects in the
+ *  NetScope class instead of the extra, useless map in
+ *  the Design class.
+ *
+ * Revision 1.93  2000/07/29 03:55:38  steve
+ *  fix problem coalescing events w/ probes.
+ *
+ * Revision 1.92  2000/07/27 05:13:44  steve
+ *  Support elaboration of disable statements.
+ *
+ * Revision 1.91  2000/07/22 22:09:03  steve
+ *  Parse and elaborate timescale to scopes.
+ *
+ * Revision 1.90  2000/07/14 06:12:57  steve
+ *  Move inital value handling from NetNet to Nexus
+ *  objects. This allows better propogation of inital
+ *  values.
+ *
+ *  Clean up constant propagation  a bit to account
+ *  for regs that are not really values.
+ *
+ * Revision 1.89  2000/07/07 04:53:53  steve
+ *  Add support for non-constant delays in delay statements,
+ *  Support evaluating ! in constant expressions, and
+ *  move some code from netlist.cc to net_proc.cc.
+ *
+ * Revision 1.88  2000/06/25 19:59:42  steve
+ *  Redesign Links to include the Nexus class that
+ *  carries properties of the connected set of links.
+ *
+ * Revision 1.87  2000/06/24 22:55:19  steve
+ *  Get rid of useless next_link method.
+ *
  * Revision 1.86  2000/06/13 03:24:48  steve
  *  Index in memory assign should be a NetExpr.
  *
@@ -1021,43 +1243,5 @@ void Design::dump(ostream&o) const
  *  Get synthesis working with the NetEvWait class,
  *  and get started supporting multiple events in a
  *  wait in vvm.
- *
- * Revision 1.75  2000/04/12 04:23:57  steve
- *  Named events really should be expressed with PEIdent
- *  objects in the pform,
- *
- *  Handle named events within the mix of net events
- *  and edges. As a unified lot they get caught together.
- *  wait statements are broken into more complex statements
- *  that include a conditional.
- *
- *  Do not generate NetPEvent or NetNEvent objects in
- *  elaboration. NetEvent, NetEvWait and NetEvProbe
- *  take over those functions in the netlist.
- *
- * Revision 1.74  2000/04/10 05:26:05  steve
- *  All events now use the NetEvent class.
- *
- * Revision 1.73  2000/04/04 03:20:15  steve
- *  Simulate named event trigger and waits.
- *
- * Revision 1.72  2000/04/02 04:26:06  steve
- *  Remove the useless sref template.
- *
- * Revision 1.71  2000/04/01 21:40:22  steve
- *  Add support for integer division.
- *
- * Revision 1.70  2000/03/29 04:37:10  steve
- *  New and improved combinational primitives.
- *
- * Revision 1.69  2000/03/12 17:09:40  steve
- *  Support localparam.
- *
- * Revision 1.68  2000/03/08 04:36:53  steve
- *  Redesign the implementation of scopes and parameters.
- *  I now generate the scopes and notice the parameters
- *  in a separate pass over the pform. Once the scopes
- *  are generated, I can process overrides and evalutate
- *  paremeters before elaboration begins.
  */
 

dosify.c

@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2001 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: dosify.c,v 1.3 2002/08/12 01:34:58 steve Exp $"
+#endif
+
+/*
+ * This is a simple program to make a dosified copy of the
+ * original. That is, it converts unix style line ends to DOS
+ * style. This is useful for installing text files.
+ *
+ * The exact substitution is to replace \n with \r\n. If the line
+ * already ends with \r\n then it is not changed to \r\r\n.
+ */
+
+# include  <stdio.h>
+
+int main(int argc, char*argv[])
+{
+      FILE*ifile;
+      FILE*ofile;
+      int ch, pr;
+
+      if (argc != 3) {
+	    fprintf(stderr, "Usage: %s <input> <output>\n", argv[0]);
+	    return 1;
+      }
+
+      ifile = fopen(argv[1], "rb");
+      if (ifile == 0) {
+	    fprintf(stderr, "Unable to open %s for input.\n", argv[1]);
+	    return 2;
+      }
+
+      ofile = fopen(argv[2], "wb");
+      if (ofile == 0) {
+	    fprintf(stderr, "Unable to open %s for output.\n", argv[2]);
+	    return 2;
+      }
+
+      pr = 0;
+      while ((ch = fgetc(ifile)) != EOF) {
+
+	    if ((ch == '\n') && (pr != '\r'))
+		  fputc('\r', ofile);
+
+	    fputc(ch, ofile);
+	    pr = ch;
+      }
+
+      return 0;
+}
+
+/*
+ * $Log: dosify.c,v $
+ * Revision 1.3  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.2  2002/08/11 23:47:04  steve
+ *  Add missing Log and Ident strings.
+ *
+ * Revision 1.1  2001/08/03 17:06:47  steve
+ *  Add install of examples for Windows.
+ *
+ */
+

driver-vpi/.cvsignore

@@ -0,0 +1,2 @@
+Makefile
+iverilog-vpi.exe

driver-vpi/Makefile.in

@@ -0,0 +1,82 @@
+#
+#    This source code is free software; you can redistribute it
+#    and/or modify it in source code form under the terms of the GNU
+#    Library General Public License as published by the Free Software
+#    Foundation; either version 2 of the License, or (at your option)
+#    any later version.
+#
+#    This program is distributed in the hope that it will be useful,
+#    but WITHOUT ANY WARRANTY; without even the implied warranty of
+#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#    GNU Library General Public License for more details.
+#
+#    You should have received a copy of the GNU Library General Public
+#    License along with this program; if not, write to the Free
+#    Software Foundation, Inc.,
+#    59 Temple Place - Suite 330
+#    Boston, MA 02111-1307, USA
+#
+#ident "$Id: Makefile.in,v 1.5 2002/12/08 03:06:30 steve Exp $"
+#
+#
+SHELL = /bin/sh
+
+VERSION = 0.7
+
+prefix = @prefix@
+exec_prefix = @exec_prefix@
+srcdir = @srcdir@
+
+VPATH = $(srcdir)
+
+bindir = $(exec_prefix)/bin
+libdir = $(exec_prefix)/lib
+includedir = $(prefix)/include
+mandir = @mandir@
+
+dllib=@DLLIB@
+
+CC = @CC@
+CXX = @CXX@
+INSTALL = @INSTALL@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_DATA = @INSTALL_DATA@
+
+CPPFLAGS = @CPPFLAGS@ @DEFS@
+CFLAGS = @CFLAGS@ -I. -I$(srcdir)/.. -DVERSION='"$(VERSION)"'
+CXXFLAGS = @CXXFLAGS@ -I. -I$(srcdir)/..
+LDFLAGS = @LDFLAGS@
+
+all: iverilog-vpi@EXEEXT@
+
+clean:
+	rm -f *.o
+	rm -f iverilog-vpi@EXEEXT@
+
+distclean: clean
+	rm -f Makefile
+
+O = main.o res.o
+
+iverilog-vpi@EXEEXT@: $O
+	$(CC) $(LDFLAGS) $O -o iverilog-vpi@EXEEXT@ @EXTRALIBS@
+
+
+main.o: main.c
+	$(CC) $(CFLAGS) -c $(srcdir)/main.c
+
+# Windows specific...
+res.o: res.rc
+	windres -i res.rc -o res.o
+#
+
+install: all installdirs $(bindir)/iverilog-vpi@EXEEXT@
+
+$(bindir)/iverilog-vpi@EXEEXT@: ./iverilog-vpi@EXEEXT@
+	$(INSTALL_PROGRAM) ./iverilog-vpi@EXEEXT@ $(bindir)/iverilog-vpi@EXEEXT@
+
+installdirs: ../mkinstalldirs
+	$(srcdir)/../mkinstalldirs $(bindir)
+
+uninstall:
+	rm -f $(bindir)/iverilog-vpi@EXEEXT@

driver-vpi/main.c

@@ -0,0 +1,565 @@
+/*
+ * Copyright (c) 2002 Gus Baldauf ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+/*
+ *	iverilog-vpi.c
+ *
+ *	this program provides the functionality of iverilog-vpi.sh under Win32
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#include <windows.h>
+
+/* Macros used for compiling and linking */
+
+#define IVERILOG_VPI_CC        "gcc"				/* no .exe extension  */
+#define IVERILOG_VPI_CXX       "gcc"				/* no .exe extension  */
+#define IVERILOG_VPI_CFLAGS    "-O"					/* -I appended  later */
+#define IVERILOG_VPI_LD        "gcc"				/* no .exe extension  */
+#define IVERILOG_VPI_LDFLAGS   "-shared -Wl,--enable-auto-image-base"
+#define IVERILOG_VPI_LDLIBS    "-lveriuser -lvpi"	/* -L prepended later */
+
+/* pointers to global strings */
+
+static struct global_strings {
+	char *pCCSRC;		/* list of C source files */
+	char *pCXSRC;		/* list of C++ source files */
+	char *pOBJ;			/* list of object files */
+	char *pLIB;			/* list of library files */
+	char *pOUT;			/* output file name (.vpi extension), if 0 length then no source files specified */
+	char *pMINGW;		/* path to MinGW directory */
+	char *pIVL;			/* path to IVL directory */
+	char *pCFLAGS;		/* CFLAGS option */
+	char *pLDLIBS;		/* LDLIBS option */
+	char *pNewPath;		/* new PATH environment variable setting */
+} gstr;
+
+
+static void deInitDynString(char *str)
+{
+	free(str);
+}
+
+/* when finished, free allocated memory and return error code */
+
+static void myExit(int exitVal)
+{
+	deInitDynString(gstr.pCCSRC);
+	deInitDynString(gstr.pCXSRC);
+	deInitDynString(gstr.pOBJ);
+	deInitDynString(gstr.pLIB);
+	deInitDynString(gstr.pOUT);
+	deInitDynString(gstr.pMINGW);
+	deInitDynString(gstr.pIVL);
+	deInitDynString(gstr.pCFLAGS);
+	deInitDynString(gstr.pLDLIBS);
+	deInitDynString(gstr.pNewPath);
+
+	exit(exitVal);
+}
+
+/* display usage summary and exit */
+
+static void usage()
+{
+	fprintf(stderr,"usage: iverilog-vpi [--name=name] [-llibrary] [-mingw=dir] [-ivl=dir] sourcefile...\n");
+	fprintf(stderr,"   or  iverilog-vpi -mingw=dir\n");
+	fprintf(stderr,"   or  iverilog-vpi -ivl=dir\n");
+	myExit(1);
+}
+
+static void initDynString(char **str)
+{
+	*str = (char *) malloc(1);
+
+	if (!*str) {
+		fprintf(stderr,"error: out of memory\n");
+		myExit(4);
+	}
+
+	*str[0] = 0;
+}
+
+/* initialize dynamic memory buffers */
+
+static void init()
+{
+	initDynString(&gstr.pCCSRC);
+	initDynString(&gstr.pCXSRC);
+	initDynString(&gstr.pOBJ);
+	initDynString(&gstr.pLIB);
+	initDynString(&gstr.pOUT);
+	initDynString(&gstr.pMINGW);
+	initDynString(&gstr.pIVL);
+	initDynString(&gstr.pCFLAGS);
+	initDynString(&gstr.pLDLIBS);
+	initDynString(&gstr.pNewPath);
+}
+
+/* return true if "str" is terminated with with "end", case insensitive */
+
+static int endsIn (char *end, char *str)
+{
+	char *ext;
+
+	if (strlen(end) >= strlen(str))
+		return 0;
+
+	ext = str + (strlen(str) - strlen(end));
+
+	return stricmp(end,ext) ? 0 : 1;
+}
+
+/* return true if "str" begins with "prefix", case insensitive */
+
+static int startsWith (char *prefix, char *str)
+{
+	if (strlen(prefix) >= strlen(str))
+		return 0;
+
+	return strnicmp(prefix,str,strlen(prefix)) ? 0 : 1;
+}
+
+/* append "app" to "ptr", allocating memory as needed    */
+/*   if count is zero, then copy all characters of "app" */
+
+static void appendn (char **ptr, char *app, int count)
+{
+	*ptr = (char *) realloc(*ptr,strlen(*ptr)+(count?count:strlen(app))+1);
+
+	if (*ptr == NULL) {
+		fprintf(stderr,"error: out of memory\n");
+		myExit(4);
+	}
+
+	if (count)
+		strncat(*ptr,app,count);
+	else
+		strcat(*ptr,app);
+}
+
+/* append "app" to "ptr", allocating memory as needed    */
+
+static void append (char **ptr, char *app)
+{
+	appendn(ptr,app,0);
+}
+
+/* if the string does not end with a backslash, add one */
+
+static void appendBackSlash(char **str)
+{
+	if ((*str)[strlen(*str)-1] != '\\')
+		append(str,"\\");
+}
+
+/* copy count characters of "str" to "ptr", allocating memory as needed */
+/*   if count is zero, then copy all characters of "str"                */
+
+static void assignn (char **ptr, char *str, int count)
+{
+	*ptr = (char *) realloc(*ptr,(count?count:strlen(str))+1);
+
+	if (*ptr == NULL) {
+		fprintf(stderr,"error: out of memory\n");
+		myExit(4);
+	}
+
+	if (count) {
+		strncpy(*ptr,str,count);
+		(*ptr)[count] = 0;
+	}
+	else
+		strcpy(*ptr,str);
+}
+
+/* copy count characters of "str" to "ptr", allocating memory as needed */
+
+static void assign (char **ptr, char *str)
+{
+	assignn(ptr,str,0);
+}
+
+/* get a copy of a Icarus Verilog registry string key */
+
+static int GetRegistryKey(char *key, char **value)
+{
+	long lrv;
+	HKEY hkKey;
+	char *regKeyBuffer;
+	DWORD regKeyType, regKeySize;
+
+	lrv = RegOpenKeyEx(HKEY_LOCAL_MACHINE,"Software\\Icarus Verilog",0,KEY_QUERY_VALUE,&hkKey);
+	if (lrv != ERROR_SUCCESS)
+		return 0;
+
+	lrv = RegQueryValueEx(hkKey,key,NULL,&regKeyType,NULL,&regKeySize);
+	if ((lrv != ERROR_SUCCESS) || (regKeyType != REG_SZ) || (!regKeySize)) {
+		lrv = RegCloseKey(hkKey);
+		return 0;
+	}
+
+	regKeyBuffer = (char *) malloc(regKeySize+1);
+	if (!regKeyBuffer) {
+		lrv = RegCloseKey(hkKey);
+		fprintf(stderr,"error: out of memory\n");
+		myExit(4);
+	}
+	regKeyBuffer[regKeySize] = 0;		/* makes sure there is a trailing NULL */
+
+	lrv = RegQueryValueEx(hkKey,key,NULL,&regKeyType,regKeyBuffer,&regKeySize);
+	if ((lrv != ERROR_SUCCESS) || (regKeyType != REG_SZ) || (!regKeySize)) {
+		lrv = RegCloseKey(hkKey);
+		free(regKeyBuffer);
+		return 0;
+	}
+
+	RegCloseKey(hkKey);
+
+	assign(value,regKeyBuffer);
+	free(regKeyBuffer);
+
+	return 1;
+}
+
+/* store a copy of a Icarus Verilog registry string key */
+
+static void SetRegistryKey(char *key, char *value)
+{
+	HKEY hkKey;
+	DWORD res;
+
+	if (RegCreateKeyEx(
+		HKEY_LOCAL_MACHINE,
+		"Software\\Icarus Verilog",
+		0,
+		"",
+		REG_OPTION_NON_VOLATILE,
+		KEY_ALL_ACCESS,NULL,
+		&hkKey,
+		&res) != ERROR_SUCCESS)
+			return;
+
+	RegSetValueEx(hkKey,key,0,REG_SZ,value,strlen(value)+1);
+	RegCloseKey(hkKey);
+
+	printf("info:  storing %s in Windows' registry entry\n",value);
+	printf("       HKEY_LOCAL_MACHINE\\Software\\Icarus Verilog\\%s\n",key);
+}
+
+/* parse the command line, assign results to global variable strings */
+
+static int parse(int argc, char *argv[])
+{
+	int idx, srcFileCnt=0;
+
+	char dot_c_ext[]    = ".c";
+	char dot_cc_ext[]   = ".cc";
+	char dot_o_ext[]    = ".o";
+	char name_option[]  = "--name=";
+	char lib_option[]   = "-l";
+	char mingw_option[] = "-mingw=";
+	char ivl_option[]   = "-ivl=";
+
+	if (argc == 1)
+		return 0;
+
+	for (idx=1; idx<argc; ++idx) {
+		if (endsIn(dot_c_ext,argv[idx])) {				/* check for C source files */
+			++srcFileCnt;
+			append(&gstr.pCCSRC,argv[idx]);
+			append(&gstr.pCCSRC," ");
+			if (!*gstr.pOUT)
+			   assignn(&gstr.pOUT,argv[idx],strlen(argv[idx])-strlen(dot_c_ext));
+		}
+		else if (endsIn(dot_cc_ext,argv[idx])) {		/* check for C++ source files */
+			++srcFileCnt;
+			append(&gstr.pCXSRC,argv[idx]);
+			append(&gstr.pCXSRC," ");
+			if (!*gstr.pOUT)
+			   assignn(&gstr.pOUT,argv[idx],strlen(argv[idx])-strlen(dot_cc_ext));
+		}
+		else if (endsIn(dot_o_ext,argv[idx])) {			/* check for compiled object files */
+			++srcFileCnt;
+			append(&gstr.pOBJ,argv[idx]);
+			append(&gstr.pOBJ," ");
+			if (!*gstr.pOUT)
+			   assignn(&gstr.pOUT,argv[idx],strlen(argv[idx])-strlen(dot_o_ext));
+		}
+		else if (startsWith(name_option,argv[idx])) {	/* check for --name option */
+			assignn(&gstr.pOUT,argv[idx]+sizeof(name_option)-1,strlen(argv[idx])-(sizeof(name_option)-1));
+		}
+		else if (startsWith(lib_option,argv[idx])) {	/* check for -l option */
+			append(&gstr.pLIB,argv[idx]);
+			append(&gstr.pLIB," ");
+		}
+		else if (startsWith(mingw_option,argv[idx]))	/* check for -mingw option */
+			assignn(&gstr.pMINGW,argv[idx]+sizeof(mingw_option)-1,strlen(argv[idx])-(sizeof(mingw_option)-1));
+		else if (startsWith(ivl_option,argv[idx]))		/* check for -ivl   option */
+			assignn(&gstr.pIVL,argv[idx]+sizeof(ivl_option)-1,strlen(argv[idx])-(sizeof(ivl_option)-1));
+		else
+			return 0;	/* different from iverilog-vpi.sh, we don't ignore accept arguments */
+	}
+
+	if (0 == srcFileCnt)
+		assign(&gstr.pOUT,"");				/* in case they used --name with no source files */
+
+	if (!*gstr.pOUT) {						/* normally it's an error if there are no *.c,*.cc,*.o files */
+		if (!*gstr.pMINGW && !*gstr.pIVL)	/* unless they are just setting the IVL or MinGW registry entries */
+			usage();
+	}
+	else {
+		append(&gstr.pOUT,".vpi");			/* the result file should have a .vpi extension */
+		append(&gstr.pOUT," ");
+	}
+
+	return 1;
+}
+
+/* do minimal check that the MinGW root directory looks valid */
+
+static void checkMingwDir(char *root)
+{
+	int irv;
+	struct _stat stat_buf;
+
+	char *path;
+	initDynString(&path);
+	assign(&path,gstr.pMINGW);
+	appendBackSlash(&path);
+	append(&path,"bin\\" IVERILOG_VPI_CC ".exe");
+
+	irv = _stat(path,&stat_buf);
+	deInitDynString(path);
+
+	if (irv) {
+		fprintf(stderr,"error: %s does not appear to be the valid root directory\n",root);
+		fprintf(stderr,"       of MinGW.  Use the -mingw option of iverilog-vpi.exe to\n");
+		fprintf(stderr,"       point to the MinGW root directory.  For a Windows command\n");
+		fprintf(stderr,"       shell the option would be something like -mingw=c:\\mingw\n");
+		fprintf(stderr,"       For a Cygwin shell the option would be something like\n");
+		fprintf(stderr,"       -mingw=c:\\\\mingw\n");
+		myExit(5);
+	}
+}
+
+/* do minimal check that the Icarus Verilog root directory looks valid */
+
+static void checkIvlDir(char *root)
+{
+	int irv;
+	struct _stat stat_buf;
+
+	char *path;
+	initDynString(&path);
+	assign(&path,gstr.pIVL);
+	appendBackSlash(&path);
+	append(&path,"bin\\vvp.exe");
+
+	irv = _stat(path,&stat_buf);
+	deInitDynString(path);
+
+	if (irv) {
+		fprintf(stderr,"error: %s does not appear to be the valid root directory of\n",root);
+		fprintf(stderr,"       Icarus Verilog.  Use the -ivl option of iverilog-vpi.exe to\n");
+		fprintf(stderr,"       point to the Icarus Verilog root directory.  For a Windows\n");
+		fprintf(stderr,"       command shell the option would be something like -ivl=c:\\iverilog\n");
+		fprintf(stderr,"       For a Cygwin shell the option would be something like\n");
+		fprintf(stderr,"       -ivl=c:\\\\iverilog\n");
+		myExit(6);
+	}
+}
+
+/* see if we can find mingw root */
+
+#define IVL_REGKEY_MINGW "MingwDir"
+
+static void setup_mingw_environment()
+{
+	char *pOldPATH = getenv("PATH");		/* get current path */
+	
+	if (*gstr.pMINGW) {
+		checkMingwDir(gstr.pMINGW);
+		SetRegistryKey(IVL_REGKEY_MINGW,gstr.pMINGW);
+	}
+	else
+		if (!GetRegistryKey(IVL_REGKEY_MINGW,&gstr.pMINGW)) {
+			fprintf(stderr,"error: can not locate the MinGW root directory, use the -mingw option of\n");
+			fprintf(stderr,"       iverilog-vpi.exe to point to the MinGW root directory.  For\n");
+			fprintf(stderr,"       a Windows command shell the option would be something like\n");
+			fprintf(stderr,"       -mingw=c:\\mingw  For a Cygwin shell the option would be\n");
+			fprintf(stderr,"       something like -mingw=c:\\\\mingw\n");
+			myExit(5);
+		}
+
+	assign(&gstr.pNewPath,"PATH=");			/* create new path */
+	append(&gstr.pNewPath,gstr.pMINGW);
+	appendBackSlash(&gstr.pNewPath);
+	append(&gstr.pNewPath,"bin;");
+	append(&gstr.pNewPath,pOldPATH);
+
+	_putenv(gstr.pNewPath);					/* place new path in environment variable */
+}
+
+/* see if we can find iverilog root */
+
+#define IVL_REGKEY_IVL   "InstallDir"
+
+static void setup_ivl_environment()
+{
+	if (*gstr.pIVL) {
+		checkIvlDir(gstr.pIVL);
+		SetRegistryKey(IVL_REGKEY_IVL,gstr.pIVL);
+	}
+	else
+		if (!GetRegistryKey(IVL_REGKEY_IVL,&gstr.pIVL)) {
+			fprintf(stderr,"error: can not locate the Icarus Verilog root directory, use the -ivl option\n");
+			fprintf(stderr,"       of iverilog-vpi.exe to point to the Icarus Verilog root directory.\n");
+			fprintf(stderr,"       For a Windows command shell the option would be something like\n");
+			fprintf(stderr,"       -ivl=c:\\iverilog  For a Cygwin shell the option would be something\n");
+			fprintf(stderr,"       like -ivl=c:\\\\iverilog\n");
+			myExit(6);
+		}
+
+	/* build up the CFLAGS option string */
+
+	assign(&gstr.pCFLAGS,IVERILOG_VPI_CFLAGS);
+	append(&gstr.pCFLAGS," -I");
+	append(&gstr.pCFLAGS,gstr.pIVL);
+	appendBackSlash(&gstr.pCFLAGS);
+	append(&gstr.pCFLAGS,"include");
+
+	/* build up the LDFLAGS option string */
+
+	assign(&gstr.pLDLIBS,"-L");
+	append(&gstr.pLDLIBS,gstr.pIVL);
+	appendBackSlash(&gstr.pLDLIBS);
+	append(&gstr.pLDLIBS,"lib ");
+	append(&gstr.pLDLIBS,IVERILOG_VPI_LDLIBS);
+}
+
+/* compile source modules */
+
+static void compile(char *pSource, char **pObject, char *ext, int *compile_errors, char *compiler)
+{
+	char *ptr1 = pSource;
+	char *ptr2 = strchr(pSource,' ');
+	char *buf=0,*src=0,*obj=0;
+
+	while (ptr2) {
+		int len = ptr2 - ptr1;
+		assignn(&src,ptr1,len);
+
+		assignn(&obj,ptr1,len-strlen(ext));		/* strip off the extension */
+		append (&obj,".o");
+
+		assign (&buf,compiler);
+		append (&buf," -c -o ");
+		append (&buf,obj);
+		append (&buf," ");
+		append (&buf,gstr.pCFLAGS);
+		append (&buf," ");
+		append (&buf,src);
+
+		append (pObject,obj);
+		append (pObject," ");
+
+		printf("%s\n",buf);
+
+		if (system(buf))
+			++*compile_errors;
+
+		ptr1 = ptr2 + 1;					/* advance to next token */
+		ptr2 = strchr(ptr1,' ');
+	}
+
+	free(buf);
+	free(src);
+	free(obj);
+}
+
+/* using the global strings, compile and link */
+
+static void compile_and_link()
+{
+	char *buf=0;
+	int iRet, compile_errors = 0;
+
+	/* print out the mingw and ivl directories to help the user debug problems */
+
+	printf("info:  %s will be used as the MinGW root directory.\n",gstr.pMINGW);
+	checkMingwDir(gstr.pMINGW);
+
+	printf("info:  %s will be used as the Icarus Verilog root directory.\n",gstr.pIVL);
+	checkIvlDir(gstr.pIVL);
+
+	/* compile */
+
+	compile(gstr.pCCSRC,&gstr.pOBJ,".c" ,&compile_errors,IVERILOG_VPI_CC );		/* compile the C   source files */
+	compile(gstr.pCXSRC,&gstr.pOBJ,".cc",&compile_errors,IVERILOG_VPI_CXX);		/* compile the C++ source files */
+
+	if (compile_errors) {
+		fprintf(stderr,"iverilog-vpi: Some %d files failed to compile.\n",compile_errors);
+		myExit(2);
+	}
+
+	/* link */
+
+	assign(&buf,IVERILOG_VPI_LD);
+	append(&buf," -o ");
+	append(&buf,gstr.pOUT);				/* has a trailing space */
+	append(&buf,IVERILOG_VPI_LDFLAGS);
+	append(&buf," ");
+	append(&buf,gstr.pOBJ)				/* has a trailing space */;
+	append(&buf,gstr.pLIB);				/* has a trailing space */
+	append(&buf,gstr.pLDLIBS);
+
+	printf("%s\n",buf);
+
+	iRet = system(buf);
+
+	free(buf);
+
+	if (iRet)
+		myExit(3);
+}
+
+/* program execution starts here */
+
+int main(int argc, char *argv[])
+{
+	init();
+
+	if (!parse(argc,argv))
+		usage();
+
+	setup_mingw_environment();
+	setup_ivl_environment();
+
+	if (*gstr.pOUT)				/* are there any *.c,*.cc,*.o files specified */
+		compile_and_link();
+
+	myExit(0);
+}

driver-vpi/res.rc

@@ -0,0 +1,38 @@
+
+// LANGUAGE ENGLISH
+LANGUAGE 9, 4
+
+
+/////////////////////////////////////////////////////////////////////////////
+//
+// Version
+//
+
+1 VERSIONINFO
+ FILEVERSION 2002,11,13,0
+ PRODUCTVERSION 0,7,0,0
+ FILEFLAGSMASK 0x3fL
+ FILEFLAGS 0x2L
+ FILEOS 0x40004L
+ FILETYPE 0x2L
+ FILESUBTYPE 0x0L
+BEGIN
+    BLOCK "StringFileInfo"
+    BEGIN
+        BLOCK "040904b0"
+        BEGIN
+            VALUE "CompanyName", "Icarus Verilog\0"
+            VALUE "FileDescription", "Icarus Veriog VPI Tool\0"
+            VALUE "FileVersion", "2002, 11, 13, 0\0"
+            VALUE "InternalName", "iverilog-vpi\0"
+            VALUE "LegalCopyright", "Copyright 2002 Gus Baldauf\0"
+            VALUE "OriginalFilename", "iverilog-vpi.exe\0"
+            VALUE "ProductName", "Icarus Verilog\0"
+            VALUE "ProductVersion", "0, 7, 0, 0\0"
+        END
+    END
+    BLOCK "VarFileInfo"
+    BEGIN
+        VALUE "Translation", 0x409, 1200
+    END
+END

driver/.cvsignore

@@ -0,0 +1,15 @@
+a.out
+Makefile
+parse.c
+parse.h
+parse.output
+lexor.c
+cfparse.c
+cfparse.h
+cfparse.output
+cflexor.c
+foo.*
+iverilog
+iverilog.ps
+iverilog.pdf
+tmp.pdf

driver/Makefile.in

@@ -0,0 +1,114 @@
+#
+#    This source code is free software; you can redistribute it
+#    and/or modify it in source code form under the terms of the GNU
+#    Library General Public License as published by the Free Software
+#    Foundation; either version 2 of the License, or (at your option)
+#    any later version.
+#
+#    This program is distributed in the hope that it will be useful,
+#    but WITHOUT ANY WARRANTY; without even the implied warranty of
+#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#    GNU Library General Public License for more details.
+#
+#    You should have received a copy of the GNU Library General Public
+#    License along with this program; if not, write to the Free
+#    Software Foundation, Inc.,
+#    59 Temple Place - Suite 330
+#    Boston, MA 02111-1307, USA
+#
+#ident "$Id: Makefile.in,v 1.16 2002/12/08 03:06:30 steve Exp $"
+#
+#
+SHELL = /bin/sh
+
+VERSION = 0.7
+
+prefix = @prefix@
+exec_prefix = @exec_prefix@
+srcdir = @srcdir@
+
+VPATH = $(srcdir)
+
+bindir = $(exec_prefix)/bin
+libdir = $(exec_prefix)/lib
+includedir = $(prefix)/include
+mandir = @mandir@
+
+dllib=@DLLIB@
+
+CC = @CC@
+CXX = @CXX@
+INSTALL = @INSTALL@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_DATA = @INSTALL_DATA@
+
+CPPFLAGS = @CPPFLAGS@ @DEFS@
+CFLAGS = @CFLAGS@ -I. -I$(srcdir)/.. -DVERSION='"$(VERSION)"'
+CXXFLAGS = @CXXFLAGS@ -I. -I$(srcdir)/..
+LDFLAGS = @LDFLAGS@
+
+all: iverilog@EXEEXT@
+
+clean:
+	rm -f *.o lexor.c parse.c parse.h parse.output
+	rm -f cflexor.c cfparse.c cfparse.h cfparse.output
+
+O = main.o build_string.o lexor.o parse.o substit.o cflexor.o cfparse.o
+
+iverilog@EXEEXT@: $O
+	$(CC) $(LDFLAGS) $O -o iverilog@EXEEXT@ @EXTRALIBS@
+
+lexor.c: lexor.lex
+	flex -s -olexor.c $(srcdir)/lexor.lex
+
+parse.h parse.c: parse.y
+	bison --verbose -t -d -o parse.c $(srcdir)/parse.y
+
+cflexor.c: cflexor.lex
+	flex -s -Pcf -ocflexor.c $(srcdir)/cflexor.lex
+
+cfparse.h cfparse.c: cfparse.y
+	bison --verbose -t -d -o cfparse.c --name-prefix=cf $(srcdir)/cfparse.y
+
+
+main.o: main.c globals.h
+	$(CC) $(CFLAGS) -c -DCXX='"@CXX@"' -DIVL_ROOT='"@libdir@/ivl"'  -DIVL_INC='"@includedir@"' -DIVL_LIB='"@libdir@"' -DDLLIB='"@DLLIB@"' $(srcdir)/main.c
+
+build_string.o: build_string.c globals.h
+lexor.o: lexor.c parse.h globals.h
+parse.o: parse.c globals.h
+cflexor.o: cflexor.c cfparse.h cfparse_misc.h globals.h
+cfparse.o: cfparse.c globals.h cfparse_misc.h
+
+iverilog.ps: $(srcdir)/iverilog.man
+	man -t $(srcdir)/iverilog.man > iverilog.ps
+
+iverilog.pdf: iverilog.ps
+	ps2pdf iverilog.ps iverilog.pdf
+
+ifeq (@WIN32@,yes)
+INSTALL_DOC = $(prefix)/iverilog.pdf
+INSTALL_DOCDIR =
+all: iverilog.pdf
+else
+INSTALL_DOC = $(mandir)/man1/iverilog.1
+INSTALL_DOCDIR = $(mandir)/man1
+endif
+
+install: all installdirs $(bindir)/iverilog@EXEEXT@ $(INSTALL_DOC)
+
+$(bindir)/iverilog@EXEEXT@: ./iverilog@EXEEXT@
+	$(INSTALL_PROGRAM) ./iverilog@EXEEXT@ $(bindir)/iverilog@EXEEXT@
+
+$(mandir)/man1/iverilog.1: $(srcdir)/iverilog.man
+	$(INSTALL_DATA) $(srcdir)/iverilog.man $(mandir)/man1/iverilog.1
+
+$(prefix)/iverilog.pdf: iverilog.pdf
+	$(INSTALL_DATA) iverilog.pdf $(prefix)/iverilog.pdf
+
+installdirs: ../mkinstalldirs
+	$(srcdir)/../mkinstalldirs $(bindir) $(INSTALL_DOCDIR)
+
+uninstall:
+	rm -f $(bindir)/iverilog@EXEEXT@
+	rm -f $(mandir)/man1/iverilog.1

driver/build_string.c

@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2000 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: build_string.c,v 1.11 2002/08/12 01:35:01 steve Exp $"
+#endif
+
+# include "config.h"
+
+# include  "globals.h"
+# include  <string.h>
+# include  <assert.h>
+
+int build_string(char*output, size_t olen, const char*pattern)
+{
+      char tmp_buf[1024];
+
+      char*output_save = output;
+      while (*pattern) {
+
+	    if (*pattern == '%') {
+		  pattern += 1;
+		  switch (*pattern) {
+		      case 0:
+			break;
+
+		      case '%':
+			*output++ = '%';
+			break;
+
+		      case '[': {
+			    const char*tail;
+			    pattern += 1;
+			    assert(*pattern);
+			    tail = strchr(pattern+1, ']');
+			    assert(tail);
+			    strncpy(tmp_buf, pattern+1, tail-pattern-1);
+			    tmp_buf[tail-pattern-1] = 0;
+
+			    if (((*pattern == 's') && start)
+				|| ((*pattern == 'v') && verbose_flag)
+				|| ((*pattern == 'M') && depfile)
+				|| ((*pattern == 'N') && npath)
+				|| ((*pattern == 'T') && mtm)) {
+				  int rc = build_string(output, olen,
+							tmp_buf);
+				  output += rc;
+				  olen -= rc;
+			    }
+			    pattern = tail;
+			    break;
+		      }
+
+		      case 'B':
+			strcpy(output, base);
+			output += strlen(base);
+			olen -= strlen(base);
+			break;
+
+		      case 'C':
+			strcpy(output, iconfig_path);
+			output += strlen(iconfig_path);
+			olen -= strlen(iconfig_path);
+			break;
+
+		      case 'g':
+			strcpy(output, generation);
+			output += strlen(generation);
+			olen -= strlen(generation);
+			break;
+
+		      case 'f':
+			if (f_list) {
+			      strcpy(output, f_list);
+			      output += strlen(f_list);
+			      olen -= strlen(f_list);
+			}
+			break;
+
+		      case 'm':
+			if (mod_list) {
+			      strcpy(output, mod_list);
+			      output += strlen(mod_list);
+			      olen -= strlen(mod_list);
+			}
+			break;
+
+		      case 'M':
+			if (depfile) {
+			      strcpy(output, depfile);
+			      output += strlen(depfile);
+			      olen -= strlen(depfile);
+			}
+			break;
+
+		      case 'N':
+			if (npath) {
+			      strcpy(output, npath);
+			      output += strlen(npath);
+			      olen -= strlen(npath);
+			}
+			break;
+
+		      case 'o':
+			strcpy(output, opath);
+			output += strlen(opath);
+			olen -= strlen(opath);
+			break;
+
+		      case 's':
+			if (start) {
+			      strcpy(output, start);
+			      output += strlen(start);
+			      olen -= strlen(start);
+			}
+			break;
+
+		      case 'T':
+			if (mtm) {
+			      strcpy(output, mtm);
+			      output += strlen(mtm);
+			      olen -= strlen(mtm);
+			}
+			break;
+
+		      case 't':
+			strcpy(output, targ);
+			output += strlen(targ);
+			olen -= strlen(targ);
+			break;
+
+		      case 'W':
+			strcpy(output, warning_flags);
+			output += strlen(warning_flags);
+			olen -= strlen(warning_flags);
+			break;
+
+		  }
+		  pattern += 1;
+
+	    } else {
+		  *output++ = *pattern++;
+		  olen -= 1;
+	    }
+      }
+
+      *output = 0;
+      return output-output_save;
+}
+
+/*
+ * $Log: build_string.c,v $
+ * Revision 1.11  2002/08/12 01:35:01  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.10  2002/05/28 02:25:03  steve
+ *  Pass library paths through -Cfile instead of command line.
+ *
+ * Revision 1.9  2002/05/28 00:50:39  steve
+ *  Add the ivl -C flag for bulk configuration
+ *  from the driver, and use that to run library
+ *  modules through the preprocessor.
+ *
+ * Revision 1.8  2002/05/24 01:13:00  steve
+ *  Support language generation flag -g.
+ *
+ * Revision 1.7  2002/04/04 05:26:13  steve
+ *  Add dependency generation.
+ *
+ * Revision 1.6  2001/11/16 05:07:19  steve
+ *  Add support for +libext+ in command files.
+ *
+ * Revision 1.5  2001/10/20 23:02:40  steve
+ *  Add automatic module libraries.
+ *
+ * Revision 1.4  2001/07/25 03:10:50  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
+ * Revision 1.3  2001/07/03 04:09:25  steve
+ *  Generate verbuse status messages (Stephan Boettcher)
+ *
+ * Revision 1.2  2000/10/28 03:45:47  steve
+ *  Use the conf file to generate the vvm ivl string.
+ *
+ * Revision 1.1  2000/10/08 22:36:56  steve
+ *  iverilog with an iverilog.conf configuration file.
+ *
+ */
+

driver/cflexor.lex

@@ -0,0 +1,137 @@
+
+%{
+/*
+ * Copyright (c) 2001 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#if !defined(WINNT) && !defined(macintosh)
+#ident "$Id: cflexor.lex,v 1.6 2002/05/28 20:40:37 steve Exp $"
+#endif
+
+# include  "cfparse.h"
+# include  "cfparse_misc.h"
+# include  "globals.h"
+# include  <string.h>
+
+/*
+ * Lexical location information is passed in the yylloc variable to th
+ * parser. The file names, strings, are kept in a list so that I can
+ * re-use them. The set_file_name function will return a pointer to
+ * the name as it exists in the list (and delete the passed string.)
+ * If the name is new, it will be added to the list.
+ */
+YYLTYPE yylloc;
+
+static int comment_enter;
+
+%}
+
+%x CCOMMENT
+%x LCOMMENT
+%x PLUS_ARGS
+
+%%
+
+  /* Accept C++ style comments. */
+"//".* { comment_enter = YY_START; BEGIN(LCOMMENT); }
+<LCOMMENT>.    { yymore(); }
+<LCOMMENT>\n   { yylloc.first_line += 1; BEGIN(comment_enter); }
+
+  /* Accept C style comments. */
+"/*" { comment_enter = YY_START; BEGIN(CCOMMENT); }
+<CCOMMENT>.    { yymore(); }
+<CCOMMENT>\n   { yylloc.first_line += 1; yymore(); }
+<CCOMMENT>"*/" { BEGIN(comment_enter); }
+
+  /* Accept shell type comments. */
+^"#".* { ; }
+
+  /* Skip white space. */
+[ \t\f\r] { ; }
+  /* Skip line ends, but also count the line. */
+\n { yylloc.first_line += 1; }
+
+
+"+define+" { BEGIN(PLUS_ARGS); return TOK_DEFINE; }
+
+"+incdir+" { BEGIN(PLUS_ARGS); return TOK_INCDIR; }
+
+"+libdir+" { BEGIN(PLUS_ARGS); return TOK_LIBDIR; }
+
+"+libdir-nocase+" { BEGIN(PLUS_ARGS); return TOK_LIBDIR_NOCASE; }
+
+"+libext+" { BEGIN(PLUS_ARGS); return TOK_LIBEXT; }
+
+
+  /* If it is not any known plus-flag, return the generic form. */
+"+"[^\n \t\b\f\r+]* {
+      cflval.text = strdup(yytext);
+      BEGIN(PLUS_ARGS);
+      return TOK_PLUSWORD; }
+
+  /* Once in PLUS_ARGS mode, words are delimited by +
+     characters. White space and line end terminate PLUS_ARGS mode,
+     but + terminates only the word. */
+<PLUS_ARGS>[^\n \t\b\f\r+]* {
+      cflval.text = strdup(yytext);
+      return TOK_PLUSARG; }
+
+  /* Within plusargs, this is a delimiter. */
+<PLUS_ARGS>"+" { }
+
+  /* White space end plus_args mode. */
+<PLUS_ARGS>[ \t\b\f\r] { BEGIN(0); }
+
+<PLUS_ARGS>\n {
+      yylloc.first_line += 1;
+      BEGIN(0); }
+
+  /* Notice the -a flag. */
+"-a" { return TOK_Da; }
+
+  /* Notice the -v flag. */
+"-v" { return TOK_Dv; }
+
+  /* Notice the -y flag. */
+"-y" { return TOK_Dy; }
+
+  /* This rule matches paths and strings that may be file names. This
+     is a little bit tricky, as we don't want to mistake a comment for
+     a string word. */
+"/"[^\*\/].* { cflval.text = strdup(yytext);
+               return TOK_STRING; } 
+
+[^/\n \t\b\r+-].* { cflval.text = strdup(yytext);
+                   return TOK_STRING; } 
+
+  /* Fallback match. */
+. { return yytext[0]; }
+
+%%
+
+int yywrap()
+{
+      return 1;
+}
+
+void cfreset(FILE*fd, const char*path)
+{
+      yyin = fd;
+      yyrestart(fd);
+      yylloc.first_line = 1;
+      yylloc.text = (char*)path;
+}

driver/cfparse.y

@@ -0,0 +1,210 @@
+%{
+/*
+ * Copyright (c) 20001 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#if !defined(WINNT) && !defined(macintosh)
+#ident "$Id: cfparse.y,v 1.8 2002/06/23 20:10:51 steve Exp $"
+#endif
+
+
+# include  "globals.h"
+# include  "cfparse_misc.h"
+# include  <ctype.h>
+
+/*
+ * This flag is set to 0, 1 or 2 if file names are to be translated to
+ * uppercase(1) or lowercase(2).
+ */
+static int setcase_filename_flag = 0;
+static void translate_file_name(char*text)
+{
+      switch (setcase_filename_flag) {
+	  case 0:
+	    break;
+	  case 1:
+	    while (*text) {
+		  *text = toupper(*text);
+		  text += 1;
+	    }
+	    break;
+	  case 2:
+	    while (*text) {
+		  *text = tolower(*text);
+		  text += 1;
+	    }
+	    break;
+      }
+}
+
+%}
+
+%union {
+      char*text;
+};
+
+%token TOK_Da TOK_Dv TOK_Dy
+%token TOK_DEFINE TOK_INCDIR TOK_LIBDIR TOK_LIBDIR_NOCASE TOK_LIBEXT
+%token <text> TOK_PLUSARG TOK_PLUSWORD TOK_STRING
+
+%%
+
+start
+	:
+	| item_list
+	;
+
+item_list
+	: item_list item
+	| item
+	;
+
+item
+  /* Absent any other matching, a token string is taken to be the name
+     of a source file. Add the file to the file list. */
+
+	: TOK_STRING
+		{ char*tmp = substitutions($1);
+		  translate_file_name(tmp);
+		  process_file_name(tmp);
+		  free($1);
+		  free(tmp);
+		}
+
+  /* The -a flag is completely ignored. */
+
+        | TOK_Da { }
+
+  /* The -v <libfile> flag is ignored, and the <libfile> is processed
+     as an ordinary source file. */
+
+        | TOK_Dv TOK_STRING
+		{ char*tmp = substitutions($2);
+		  translate_file_name(tmp);
+		  process_file_name(tmp);
+		  fprintf(stderr, "%s:%u: Ignoring -v in front of %s\n",
+			  @1.text, @1.first_line, $2);
+		  free($2);
+		  free(tmp);
+		}
+
+  /* This rule matches "-y <path>" sequences. This does the same thing
+     as -y on the command line, so add the path to the library
+     directory list. */
+
+        | TOK_Dy TOK_STRING
+		{ char*tmp = substitutions($2);
+		  process_library_switch(tmp);
+		  free($2);
+		  free(tmp);
+		}
+
+        | TOK_LIBDIR TOK_PLUSARG
+		{ char*tmp = substitutions($2);
+		  process_library_switch(tmp);
+		  free($2);
+		  free(tmp);
+		}
+
+        | TOK_LIBDIR_NOCASE TOK_PLUSARG
+		{ char*tmp = substitutions($2);
+		  process_library_nocase_switch(tmp);
+		  free($2);
+		  free(tmp);
+		}
+
+	| TOK_DEFINE TOK_PLUSARG
+		{ process_define($2);
+		  free($2);
+		}
+
+  /* The +incdir token introduces a list of +<path> arguments that are
+     the include directories to search. */
+
+	| TOK_INCDIR inc_args
+
+  /* The +libext token introduces a list of +<ext> arguments that
+     become individual -Y flags to ivl. */
+
+	| TOK_LIBEXT libext_args
+
+  /* The +<word> tokens that are not otherwise matched, are
+     ignored. The skip_args rule arranges for all the argument words
+     to be consumed. */
+
+	| TOK_PLUSWORD skip_args
+		{ fprintf(stderr, "%s:%u: Ignoring %s\n",
+			  @1.text, @1.first_line, $1);
+		  free($1);
+		}
+	| TOK_PLUSWORD
+		{ if (strcmp($1, "+toupper-filenames") == 0) {
+		        setcase_filename_flag = 1;
+		  } else if (strcmp($1, "+tolower-filenames") == 0) {
+			setcase_filename_flag = 2;
+		  } else {
+			fprintf(stderr, "%s:%u: Ignoring %s\n",
+				@1.text, @1.first_line, $1);
+		  }
+		  free($1);
+		}
+	;
+
+  /* inc_args are +incdir+ arguments in order. */
+inc_args
+	: inc_args inc_arg
+	| inc_arg
+	;
+
+inc_arg : TOK_PLUSARG
+		{ char*tmp = substitutions($1);
+		  process_include_dir(tmp);
+		  free($1);
+		  free(tmp);
+		}
+	;
+
+  /* inc_args are +incdir+ arguments in order. */
+libext_args
+	: libext_args libext_arg
+	| libext_arg
+	;
+
+libext_arg : TOK_PLUSARG
+		{ process_library2_switch($1);
+		  free($1);
+		}
+	;
+
+  /* skip_args are arguments to a +word flag that is not otherwise
+     parsed. This rule matches them and releases the strings, so that
+     they can be safely ignored. */
+skip_args
+	: skip_args skip_arg
+	| skip_arg
+	;
+
+skip_arg : TOK_PLUSARG
+		{ free($1);
+		}
+	;
+
+%%
+
+int yyerror(const char*msg)
+{
+}

driver/cfparse_misc.h

@@ -0,0 +1,57 @@
+#ifndef __cfparse_misc_H
+#define __cfparse_misc_H
+/*
+ * Copyright (c) 2001 Picture Elements, Inc.
+ *    Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: cfparse_misc.h,v 1.4 2002/08/12 01:35:01 steve Exp $"
+#endif
+
+/*
+ * The vlltype supports the passing of detailed source file location
+ * information between the lexical analyzer and the parser. Defining
+ * YYLTYPE compels the lexor to use this type and not something other.
+ */
+struct cfltype {
+      unsigned first_line;
+      unsigned first_column;
+      unsigned last_line;
+      unsigned last_column;
+      const char*text;
+};
+# define YYLTYPE struct cfltype
+extern YYLTYPE yylloc;
+
+/*
+ * $Log: cfparse_misc.h,v $
+ * Revision 1.4  2002/08/12 01:35:01  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.3  2002/01/02 02:39:34  steve
+ *  Use my own cfltype to defend against bison 1.30.
+ *
+ * Revision 1.2  2001/11/12 18:47:32  steve
+ *  Support +incdir in command files, and ignore other
+ *  +args flags. Also ignore -a and -v flags.
+ *
+ * Revision 1.1  2001/11/12 01:26:36  steve
+ *  More sophisticated command file parser.
+ *
+ */
+#endif

driver/globals.h

@@ -0,0 +1,149 @@
+#ifndef __globals_H
+#define __globals_H
+/*
+ * Copyright (c) 2000 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: globals.h,v 1.16 2002/08/12 01:35:01 steve Exp $"
+#endif
+
+# include  <stddef.h>
+
+  /* This is the base (i.e. -B<value>) of the Icarus Verilog files. */
+extern const char*base;
+
+  /* This is the path to the iconfig file sent to ivl. */
+extern char* iconfig_path;
+
+  /* This is a list of all the -f<key>=<value> options from the
+     command line, concatenated together. */
+extern char*f_list;
+
+extern char*mod_list;
+
+  /* This is the optional -Tmin|typ|max setting. */
+extern const char*mtm;
+
+  /* Ths is the optional -M<dependfile> value, if one was supplied. */
+extern const char*depfile;
+
+  /* Ths is the optional -N<path> value, if one was supplied. */
+extern const char*npath;
+
+  /* This is the name of the output file that the user selected. */
+extern const char*opath;
+
+  /* This pointer is set if there were -s<value> parameters. */
+extern char*start;
+
+  /* This flag is true if the -S flag was used on the command line. */
+extern int synth_flag;
+
+  /* This is the name of the selected target. */
+extern const char*targ;
+
+  /* This is the language generation flag. */
+extern const char*generation;
+
+  /* Perform variable substitutions on the string. */
+extern char* substitutions(const char*str);
+
+  /* Add the name to the list of source files. */
+extern void process_file_name(const char*name);
+
+  /* Add the name to the list of library directories. */
+extern void process_library_switch(const char*name);
+extern void process_library_nocase_switch(const char*name);
+extern void process_library2_switch(const char*name);
+
+  /* Add a new include file search directory */
+extern void process_include_dir(const char*name);
+
+  /* Add a new -D define. */
+extern void process_define(const char*name);
+
+  /* -v */
+extern int verbose_flag;
+
+extern char warning_flags[];
+
+  /* -y and -Y flags from the command line. */
+extern char* library_flags;
+extern char* library_flags2;
+
+extern const char*lookup_pattern(const char*key);
+
+extern int build_string(char*out, size_t olen, const char*pattern);
+
+/*
+ * $Log: globals.h,v $
+ * Revision 1.16  2002/08/12 01:35:01  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.15  2002/06/23 20:10:51  steve
+ *  Variable substitution in command files.
+ *
+ * Revision 1.14  2002/05/28 20:40:37  steve
+ *  ivl indexes the search path for libraries, and
+ *  supports case insensitive module-to-file lookup.
+ *
+ * Revision 1.13  2002/05/28 00:50:40  steve
+ *  Add the ivl -C flag for bulk configuration
+ *  from the driver, and use that to run library
+ *  modules through the preprocessor.
+ *
+ * Revision 1.12  2002/05/24 01:13:00  steve
+ *  Support language generation flag -g.
+ *
+ * Revision 1.11  2002/04/04 05:26:13  steve
+ *  Add dependency generation.
+ *
+ * Revision 1.10  2001/11/16 05:07:19  steve
+ *  Add support for +libext+ in command files.
+ *
+ * Revision 1.9  2001/11/13 03:30:26  steve
+ *  The +incdir+ plusarg can take multiple directores,
+ *  and add initial support for +define+ in the command file.
+ *
+ * Revision 1.8  2001/11/12 18:47:32  steve
+ *  Support +incdir in command files, and ignore other
+ *  +args flags. Also ignore -a and -v flags.
+ *
+ * Revision 1.7  2001/11/12 01:26:36  steve
+ *  More sophisticated command file parser.
+ *
+ * Revision 1.6  2001/10/23 00:37:30  steve
+ *  The -s flag can now be repeated on the iverilog command.
+ *
+ * Revision 1.5  2001/10/20 23:02:40  steve
+ *  Add automatic module libraries.
+ *
+ * Revision 1.4  2001/07/03 04:09:25  steve
+ *  Generate verbuse status messages (Stephan Boettcher)
+ *
+ * Revision 1.3  2000/11/09 21:58:00  steve
+ *  Remember to include the -S condition.
+ *
+ * Revision 1.2  2000/10/28 03:45:47  steve
+ *  Use the conf file to generate the vvm ivl string.
+ *
+ * Revision 1.1  2000/10/08 22:36:56  steve
+ *  iverilog with an iverilog.conf configuration file.
+ *
+ */
+#endif

driver/iverilog.man

@@ -0,0 +1,322 @@
+.TH iverilog 1 "$Date: 2002/06/23 20:10:51 $" Version "$Date: 2002/06/23 20:10:51 $"
+.SH NAME
+iverilog - Icarus Verilog compiler
+
+.SH SYNOPSIS
+.B iverilog
+[-ESVv] [-Cpath] [-ccmdfile] [-g1|-g2|-g3.0] [-Dmacro[=defn]] [-pflag=value]
+[-Iincludedir] [-mmodule] [-Mfile] [-Nfile] [-ooutputfilename]
+[-stopmodule] [-ttype] [-Tmin/typ/max] [-Wclass] [-ypath] sourcefile
+
+.SH DESCRIPTION
+.PP
+\fIiverilog\fP is a compiler that translates Verilog source code into
+executable programs for simulation, or other netlist formats for
+further processing. The currently supported targets are \fIvvp\fP for
+simulation, and \fIxnf\fP and \fIfpga\fP for synthesis. Other target
+types are added as code generators are implemented.
+
+.SH OPTIONS
+.l
+\fIiverilog\fP accepts the following options:
+.TP 8
+.B -B\fIbase\fP
+The \fIiverilog\fP program uses external programs to preprocess and
+compile the Verilog source. Normally, the path used to locate these
+tools is built into the \fIiverilog\fP program. However, the \fB-B\fP
+switch allows the user to select a different set of programs. The path
+given is used to locate \fIivlpp\fP, \fIivl\fP and the VPI modules.
+.TP 8
+.B -c\fIfile\fP
+This flag specifies an input file that contains a list of Verilog
+source files. This is similar to the \fIcommand file\fP of other
+Verilog simulators, in that it is a file that contains the file names
+instead of taking them on the command line. See \fBCommand Files\fP below.
+.TP 8
+.B -C\fIpath\fP
+This flag selects the driver configuration file to use. Normally, the
+iverilog program will read its configuration file from
+/usr/lib/ivl/iverilog.conf (or the install path configured at compile
+time) but the user can specify the path to a different configuration
+file. This is useful when testing new configuration files. See the
+installed configuration file for a summary of the file format.
+.TP 8
+.B -D\fImacro\fP
+Defines macro \fImacro\fP with the string `1' as its definition. This
+form is normally only used to trigger ifdef conditionals in the
+Verilog source.
+.TP 8
+.B -D\fImacro=defn\fP
+Defines macro \fImacro\fP as \fIdefn\fP.
+.TP 8
+.B -E
+Preprocess the Verilog source, but do not compile it. The output file
+is the Verilog input, but with file inclusions and macro references
+expanded and removed. This is useful, for example, to preprocess
+Verilog source for use by other compilers.
+.TP 8
+.B -g1\fI|\fP-g2\fI|\fP-g3.0
+Select the Verilog language \fIgeneration\fP to support in the
+compiler. This selects between \fIIEEE1364-1995\fP(1),
+\fIIEEE1364-2001\fP(2), or \fISystemVerilog 3.0\fP(3.0). Normally,
+Icarus Verilog defaults to the latest known generation of the
+language. This flag is most useful to restrict the language to a set
+supported by tools of specific generations, for compatibility with
+other tools.
+.TP 8
+.B -I\fIincludedir\fP 
+Append directory \fIincludedir\fP to list of directories searched
+for Verilog include files. The \fB-I\fP switch may be used many times
+to specify several directories to search, the directories are searched
+in the order they appear on the command line.
+.TP 8
+.B -M\fIpath\fP
+Write into the file specified by path a list of files that contribute
+to the compilation of the design. This includes files that are
+included by include directives and files that are automatically loaded
+by library support. The output is one file name per line, with no
+leading or trailing space.
+.TP 8
+.B -m\fImodule\fP
+Add this module to the list of VPI modules to be loaded by the
+simulation. Many modules can be specified, and all will be loaded, in
+the order specified. The system module is implicit and always included.
+.TP 8
+.B -N\fIpath\fP
+This is used for debugging the compiler proper. Dump the final netlist
+form of the design to the specified file. It otherwise does not affect
+operation of the compiler. The dump happens after the design is
+elaborated and optimized.
+.TP 8
+.B -o \fIfilename\fP
+Place output in the file \fIfilename\fP. If no output file name is
+specified, \fIiverilog\fP uses the default name \fBa.out\fP.
+.TP 8
+.B -p\fIflag=value\fP
+Assign a value to a target specific flag. The \fB-p\fP switch may be
+used as often as necessary to specify all the desired flags. The flags
+that are used depend on the target that is selected, and are described
+in target specific documentation. Flags that are not used are ignored.
+.TP 8
+.B -S
+Synthesize. Normally, if the target can accept behavioral
+descriptions the compiler will leave processes in behavioral
+form. The \fB-S\fP switch causes the compiler to perform synthesis
+even if it is not necessary for the target. If the target type is a
+netlist format, the \fB-S\fP switch is unnecessary and has no effect.
+.TP 8
+.B -s \fItopmodule\fP
+Specify the top level module to elaborate. Icarus Verilog will by default
+choose modules that are not instantiated in any other modules, but
+sometimes that is not sufficient, or instantiates too many modules. If
+the user specifies one or more root modules with \fB-s\fP flags, then
+they will be used as root modules instead.
+.TP 8
+.B -T\fImin|typ|max\fP
+Use this switch to select min, typ or max times from min:typ:max
+expressions. Normally, the compiler will simply use the typ value from
+these expressions (with a warning) but this switch will tell the
+compiler explicitly which value to use. This will suppress the
+warning that the compiler is making a choice.
+.TP 8
+.B -t\fItarget\fP
+Use this switch to specify the target output format. See the
+\fBTARGETS\fP section below for a list of valid output formats.
+.TP 8
+.B -v
+Turn on verbose messages. This will print the command lines that are
+executed to perform the actual compilation, along with version
+information from the various components, as well as the version of the
+product as a whole.
+.TP 8
+.B -V
+Print the version of the compiler, and exit.
+.TP 8
+.B -W\fIclass\fP
+Turn on different classes of warnings. See the \fBWARNING TYPES\fP
+section below for descriptions of the different warning groups. If
+multiple \fB-W\fP switches are used, the warning set is the union of
+all the requested classes.
+.TP 8
+.B -y\fIlibdir\fP
+Append the directory to the library module search path. When the
+compiler finds an undefined module, it looks in these directories for
+files with the right name.
+
+.SH MODULE LIBRARIES
+
+The Icarus Verilog compiler supports module libraries as directories
+that contain Verilog source files.  During elaboration, the compiler
+notices the instantiation of undefined module types. If the user
+specifies library search directories, the compiler will search the
+directory for files with the name of the missing module type. If it
+finds such a file, it loads it as a Verilog source file, they tries
+again to elaborate the module.
+
+Library module files should contain only a single module, but this is
+not a requirement. Library modules may reference other modules in the
+library or in the main design.
+
+.SH TARGETS
+
+The Icarus Verilog compiler supports a variety of targets, for
+different purposes, and the \fB-t\fP switch is used to select the
+desired target.
+
+.TP 8
+.B null
+The null target causes no code to be generated. It is useful for
+checking the syntax of the Verilog source.
+.TP 8
+.B vvp
+This is the default. The vvp target generates code for the vvp
+runtime. The output is a complete program that simulates the design
+but must be run by the \fBvvp\fP command.
+.TP 8
+.B xnf
+This is the Xilinx Netlist Format used by many tools for placing
+devices in FPGAs or other programmable devices. The Icarus Verilog XNF
+code generator can generate complete designs or XNF macros that can be
+imported into larger designs by other tools. (This target is obsolete,
+use the \fBfpga\fP target instead.)
+.TP 8
+.B fpga
+This is a synthesis target that supports a variety of fpga devices,
+mostly by EDIF format output.
+
+.SH "WARNING TYPES"
+These are the types of warnings that can be selected by the \fB-W\fP
+switch. All the warning types (other then \fBall\fP) can also be
+prefixed with \fBno-\fP to turn off that warning. This is most useful
+after a \fB-Wall\fP argument to suppress isolated warning types.
+
+.TP 8
+.B all
+This enables all supported warning categories.
+
+.TP 8
+.B implicit
+This enables warnings for creation of implicit declarations. For
+example, if a scalar wire X is used but not declared in the Verilog
+source, this will print a warning at its first use.
+
+.TP 8
+.B timescale
+This enables warnings for inconsistent use of the timescale
+directive. It detects if some modules have no timescale, or if modules
+inherit timescale from another file. Both probably mean that
+timescales are inconsistent, and simulation timing can be confusing
+and dependent on compilation order.
+
+.SH "COMMAND FILES"
+The command file allows the user to place source file names and
+certain command line switches into a text file instead of on a long
+command line. Command files can include C or C++ style comments, as
+well as # comments, if the # starts the line.
+
+.TP 8
+.I "file name"
+A simple file name or file path is taken to be the name of a Verilog
+source file. The path starts with the first non-white-space
+character. Variables are substitued in file names.
+
+.TP 8
+.B -y\ \fIlibdir\fP
+A \fB-y\fP token prefixes a library directory in the command file,
+exactly like it does on the command line. The parameter to the \fB-y\fP
+flag may be on the same line or the next non-comment line.
+
+Variables in the \fIlibdir\fP are substituted.
+
+.TP 8
+.B +incdir+\fIincludedir\fP
+The \fB+incdir+\fP token in command files gives directories to search
+for include files in much the same way that \fB-I\fP flags work on the
+command line. The difference is that multiple \fI+includedir\fP
+directories are valid parameters to a single \fB+incdir+\fP token,
+although you may also have multiple \fB+incdir+\fP lines.
+
+Variables in the \fIincludedir\fP are substituted.
+
+.TP 8
+.B +libext+\fIext\fP
+The \fB+libext\fP token in command files fives file extensions to try
+when looking for a library file. This is useful in conjunction with
+\fB-y\fP flags to list suffixes to try in each directory before moving
+on to the next library directory.
+
+.TP 8
+.B +libdir+\fIdir\fP
+This is another way to specify library directories. See the -y flag.
+
+.TP 8
+.B +libdir-nocase+\fIdir\fP
+This is like the \fB+libdir\fP statement, but file names inside the
+directories declared here are case insensitive. The missing module
+name in a lookup need not match the file name case, as long as the
+letters are correct. For example, "foo" matches "Foo.v" but not
+"bar.v".
+
+.TP 8
+.B +define+\fINAME\fP=\fIvalue\fP
+The \fB+define+\fP token is the same as the \fB-D\fP option on the
+command line. The value part of the token is optional.
+
+.TP 8
+.B +toupper-filename\fP
+This token causes file names after this in the command file to be
+translated to uppercase. This helps with situations where a directory
+has passed through a DOS machine, and in the process the file names
+become munged.
+
+.TP 8
+.B +tolower-filename\fP
+This is similar to the \fB+toupper-filename\fP hack described above.
+
+.SH "VARIABLES IN COMMAND FILES"
+
+In certain cases, iverilog supports variables in command files. These
+are strings of the form "$(\fIvarname\fP)", where \fIvarname\fP is the
+name of the environment variable to read. The entire string is
+replaced with the contents of that variable. Variables are only
+substitued in contexts that explicitly support them, including file
+and directory strings.
+
+Variable values come from the operating system environment, and not
+from preprocessor defines elsewhere in the file or the command line.
+
+.SH EXAMPLES 
+These examples assume that you have a Verilog source file called hello.v in
+the current directory
+
+To compile hello.v to an executable file called a.out:
+
+	iverilog hello.v
+
+To compile hello.v to an executable file called hello:
+
+	iverilog -o hello hello.v
+
+To compile and run explicitly using the vvp runtime:
+
+	iverilog -ohello.vvp -tvvp hello.v
+
+To compile hello.v to a file in XNF-format called hello.xnf
+
+	iverilog -txnf -ohello.xnf hello.v
+
+
+.SH "AUTHOR"
+.nf
+Steve Williams ([email protected])
+
+.SH SEE ALSO
+vvp(1),
+.BR "<http://www.icarus.com/eda/verilog/>"
+
+.SH COPYRIGHT
+.nf
+Copyright \(co  2002 Stephen Williams
+
+This document can be freely redistributed according to the terms of the 
+GNU General Public License version 2.0

driver/lexor.lex

@@ -0,0 +1,80 @@
+
+%{
+/*
+ * Copyright (c) 2000 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#if !defined(WINNT) && !defined(macintosh)
+#ident "$Id: lexor.lex,v 1.5 2001/07/25 03:10:50 steve Exp $"
+#endif
+
+# include "config.h"
+
+# include  <string.h>
+# include  "parse.h"
+
+%}
+
+%x CTOKENS
+%x PATTERN
+
+%%
+
+"#".* { /* eat comments */; }
+
+"\n" { /* eat line-ends */; }
+"\r" { /* eat line-ends */; }
+
+"[" { BEGIN(CTOKENS); return '['; }
+
+<CTOKENS>"]" { BEGIN(0); return ']'; }
+
+<CTOKENS>[ \t\b]+ { /* skip white space */; }
+
+<CTOKENS>"-S" { return CT_S; }
+
+<CTOKENS>"-t"[a-zA-Z0-9\-_]+ {
+      yylval.text = strdup(yytext+2);
+      return CT_t; }
+
+"<"[^>]*">" {
+      BEGIN(PATTERN);
+      yylval.text = strdup(yytext);
+      return PATTERN_NAME; }
+
+<PATTERN>.* {
+      BEGIN(0);
+	/* Trim off a trailing \r. This is an issue in the DOS world. */
+      if (yytext[strlen(yytext)-1] == '\r')
+	    yytext[strlen(yytext)-1] = 0;
+
+      yylval.text = strdup(yytext);
+      return PATTERN_TEXT; }
+
+. { fprintf(stderr, "driver lexor: Unmatched character: %c\n", yytext[0]); }
+
+%%
+
+void reset_lexor(FILE*fd)
+{
+      yyrestart(fd);
+}
+
+int yywrap()
+{
+      return 1;
+}

driver/main.c

@@ -0,0 +1,826 @@
+/*
+ * Copyright (c) 2000-2001 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ident "$Id: main.c,v 1.49 2002/12/04 03:26:59 steve Exp $"
+
+# include "config.h"
+
+
+const char HELP[] =
+"Usage: iverilog [-ESvV] [-B base] [-C path] [-c cmdfile] [-g1|-g2|-g3.0]\n"
+"                [-D macro[=defn]] [-I includedir] [-M depfile] [-m module]\n"
+"                [-N file] [-o filename] [-p flag=value]\n"
+"                [-s topmodule] [-t target] [-T min|typ|max]\n"
+"                [-W class] [-y dir] [-Y suf] source_file(s)\n"
+"See man page for details.";
+
+#define MAXSIZE 4096
+
+#include <stdio.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <string.h>
+#include <assert.h>
+
+#include <sys/types.h>
+#ifdef HAVE_SYS_WAIT_H
+#include <sys/wait.h>
+#endif
+
+#ifdef __MINGW32__
+#include <windows.h>
+#include <libiberty.h>
+#endif
+
+#if HAVE_GETOPT_H
+#include <getopt.h>
+#endif
+
+#if defined(__MINGW32__) && !defined(HAVE_GETOPT_H)
+extern int getopt(int argc, char*argv[], const char*fmt);
+extern int optind;
+extern const char*optarg;
+#endif
+
+#if !defined(WIFEXITED)
+# define WIFEXITED(rc) ((rc&0x7f) == 0)
+#endif
+
+#if !defined(WEXITSTATUS)
+# define WEXITSTATUS(rc) (rc>>8)
+#endif
+
+#ifndef IVL_ROOT
+# define IVL_ROOT "."
+#endif
+
+# include  "globals.h"
+
+#ifdef __MINGW32__
+const char sep = '\\';
+#else
+const char sep = '/';
+#endif
+
+extern void cfreset(FILE*fd, const char*path);
+
+const char*base = 0;
+const char*mtm  = 0;
+const char*opath = "a.out";
+const char*npath = 0;
+const char*targ  = "vvp";
+const char*depfile = 0;
+
+const char*generation = "-g3.0";
+
+char warning_flags[16] = "";
+
+char*inc_list = 0;
+char*def_list = 0;
+char*mod_list = 0;
+char*command_filename = 0;
+char*start = 0;
+
+char*f_list = 0;
+
+/* These are used to collect the list of file names that will be
+   passed to ivlpp. Keep the list in a file because it can be a long
+   list. */
+char*source_path = 0;
+FILE*source_file = 0;
+unsigned source_count = 0;
+
+char*iconfig_path = 0;
+FILE*iconfig_file = 0;
+
+int synth_flag = 0;
+int verbose_flag = 0;
+int command_file = 0;
+
+FILE *fp;
+
+char line[MAXSIZE];
+char tmp[MAXSIZE];
+
+static char ivl_root[MAXSIZE];
+
+#ifdef __MINGW32__
+# include  <io.h>
+# include  <fcntl.h>
+static FILE*fopen_safe(const char*path)
+{
+      FILE*file = 0;
+      int fd;
+
+      fd = _open(path, _O_WRONLY|_O_CREAT|_O_EXCL, 0700);
+      if (fd != -1)
+	    file = _fdopen(fd, "w");
+
+       return file;
+}
+#else
+# include  <fcntl.h>
+static FILE*fopen_safe(const char*path)
+{
+      FILE*file = 0;
+      int fd;
+
+      fd = open(path, O_WRONLY|O_CREAT|O_EXCL, 0700);
+      if (fd != -1)
+	    file = fdopen(fd, "w");
+
+       return file;
+}
+#endif
+
+static const char*my_tempfile(const char*str, FILE**fout)
+{
+      FILE*file;
+      int retry;
+
+      static char pathbuf[8192];
+
+      const char*tmpdir = getenv("TMP");
+      if (tmpdir == 0)
+	    tmpdir = getenv("TMPDIR");
+      if (tmpdir == 0)
+	    tmpdir = getenv("TEMP");
+#ifdef __MINGW32__
+      if (tmpdir == 0)
+	    tmpdir = "C:\\TEMP";
+#else
+      if (tmpdir == 0)
+	    tmpdir = "/tmp";
+#endif
+
+      assert(tmpdir);
+      assert((strlen(tmpdir) + strlen(str)) < sizeof pathbuf - 10);
+
+      srand(getpid());
+      retry = 100;
+      file = NULL;
+      while ((retry > 0) && (file == NULL)) {
+	    unsigned code = rand();
+	    sprintf(pathbuf, "%s%c%s%04x", tmpdir, sep, str, code);
+	    file = fopen_safe(pathbuf);
+	    retry -= 1;
+      }
+
+      *fout = file;
+      return pathbuf;
+}
+
+/*
+ * This is the default target type. It looks up the bits that are
+ * needed to run the command from the configuration file (which is
+ * already parsed for us) so we can handle must of the generic cases.
+ */
+static int t_default(char*cmd, unsigned ncmd)
+{
+      int rc;
+      const char*pattern;
+
+      pattern = lookup_pattern("<ivl>");
+      if (pattern == 0) {
+	    fprintf(stderr, "No such target: %s\n", targ);
+	    return -1;
+      }
+
+      tmp[0] = ' ';
+      tmp[1] = '|';
+      tmp[2] = ' ';
+      rc = build_string(tmp+3, sizeof tmp - 3, pattern);
+      cmd = realloc(cmd, ncmd+3+rc+1);
+#ifdef __MINGW32__
+      {
+	char *t;
+	for (t = tmp; *t; t++)
+	  {
+	    if (*t == '/') *t = '\\';
+	  }
+      }
+#endif
+
+      strcpy(cmd+ncmd, tmp);
+
+
+      if (verbose_flag)
+	    printf("translate: %s\n", cmd);
+
+
+      rc = system(cmd);
+      remove(source_path);
+      remove(iconfig_path);
+      if (rc != 0) {
+	    if (rc == 127) {
+		  fprintf(stderr, "Failed to execute: %s\n", cmd);
+		  return 1;
+	    }
+
+	    if (WIFEXITED(rc))
+		  return WEXITSTATUS(rc);
+
+	    fprintf(stderr, "Command signaled: %s\n", cmd);
+	    return -1;
+      }
+
+      return 0;
+}
+
+
+static void process_warning_switch(const char*name)
+{
+      if (warning_flags[0] == 0)
+	    strcpy(warning_flags, "-W");
+
+      if (strcmp(name,"all") == 0) {
+	    strcat(warning_flags, "it");
+
+      } else if (strcmp(name,"implicit") == 0) {
+	    if (! strchr(warning_flags+2, 'i'))
+		  strcat(warning_flags, "i");
+      } else if (strcmp(name,"timescale") == 0) {
+	    if (! strchr(warning_flags+2, 't'))
+		  strcat(warning_flags, "t");
+      } else if (strcmp(name,"no-implicit") == 0) {
+	    char*cp = strchr(warning_flags+2, 'i');
+	    if (cp) while (*cp) {
+		  cp[0] = cp[1];
+		  cp += 1;
+	    }
+      } else if (strcmp(name,"no-timescale") == 0) {
+	    char*cp = strchr(warning_flags+2, 't');
+	    if (cp) while (*cp) {
+		  cp[0] = cp[1];
+		  cp += 1;
+	    }
+      }
+}
+
+void process_library_switch(const char *name)
+{
+      fprintf(iconfig_file, "-y:%s\n", name);
+}
+
+void process_library_nocase_switch(const char *name)
+{
+      fprintf(iconfig_file, "-yl:%s\n", name);
+}
+
+void process_library2_switch(const char *name)
+{
+      fprintf(iconfig_file, "-Y:%s\n", name);
+}
+
+void process_include_dir(const char *name)
+{
+      if (inc_list == 0) {
+	    inc_list = malloc(strlen(" -I")+strlen(name)+1);
+	    strcpy(inc_list, " -I");
+	    strcat(inc_list, name);
+      } else {
+	    inc_list = realloc(inc_list, strlen(inc_list)
+			       + strlen(" -I")
+			       + strlen(name) + 1);
+	    strcat(inc_list, " -I");
+	    strcat(inc_list, name);
+      }
+}
+
+void process_define(const char*name)
+{
+      if (def_list == 0) {
+	    def_list = malloc(strlen(" -D")+strlen(name)+1);
+	    strcpy(def_list, " -D");
+	    strcat(def_list, name);
+      } else {
+	    def_list = realloc(def_list, strlen(def_list)
+			       + strlen(" -D")
+			       + strlen(name) + 1);
+	    strcat(def_list, " -D");
+	    strcat(def_list, name);
+      }
+}
+
+void process_file_name(const char*name)
+{
+      fprintf(source_file, "%s\n", name);
+      source_count += 1;
+}
+
+int process_generation(const char*name)
+{
+      if (strcmp(name,"1") == 0)
+	    generation = "-g1";
+
+      else if (strcmp(name,"2") == 0)
+	    generation = "-g2";
+
+      else if (strcmp(name,"3.0") == 0)
+	    generation = "-g3.0";
+
+      else {
+	    fprintf(stderr, "Unknown/Unsupported Language generation "
+		    "%s\n", name);
+	    fprintf(stderr, "Supported generations are:\n");
+	    fprintf(stderr, "    1   -- IEEE1364-1995 (Verilog 1)\n"
+		            "    2   -- IEEE1364-2001 (Verilog 2001)\n"
+		            "    3.0 -- SystemVerilog 3.0\n");
+	    return 1;
+      }
+
+      return 0;
+}
+
+int main(int argc, char **argv)
+{
+      const char*config_path = 0;
+      char*cmd;
+      unsigned ncmd;
+      int e_flag = 0;
+      int version_flag = 0;
+      int opt, idx, rc;
+      char*cp;
+
+#ifdef __MINGW32__
+      { char * s;
+	char basepath[1024];
+	GetModuleFileName(NULL,basepath,1024);
+
+	  /* Calculate the ivl_root from the path to the command. This
+	     is necessary because of the installation process in
+	     Windows. Mostly, it is those darn drive letters, but oh
+	     well. We know the command path is formed like this:
+
+	         D:\iverilog\bin\iverilog.exe
+
+	     The IVL_ROOT in a Windows installation is the path:
+
+	         D:\iverilog\lib\ivl
+
+	     so we chop the file name and the last directory by
+	     turning the last two \ characters to null. Then we append
+	     the lib\ivl to finish. */
+
+        strncpy(ivl_root, basepath, MAXSIZE);
+	s = strrchr(ivl_root, sep);
+	if (s) *s = 0;
+	s = strrchr(ivl_root, sep);
+	if (s) *s = 0;
+	strcat(ivl_root, "\\lib\\ivl");
+
+	base = ivl_root;
+      }
+
+#else
+        /* In a UNIX environment, the IVL_ROOT from the Makefile is
+	   dependable. It points to the $prefix/lib/ivl directory,
+	   where the sub-parts are installed. */
+      strcpy(ivl_root, IVL_ROOT);
+      base = ivl_root;
+#endif
+
+	/* Create a temporary file for communicating input parameters
+	   to the preprocessor. */
+      source_path = strdup(my_tempfile("ivrlg", &source_file));
+      if (NULL == source_file) {
+	    fprintf(stderr, "%s: Error opening temporary file %s\n",
+		    argv[0], source_path);
+	    fprintf(stderr, "%s: Please check TMP or TMPDIR.\n", argv[0]);
+	    return 1;
+      }
+
+	/* Create another temporary file for passing configuration
+	   information to ivl. */
+      iconfig_path = strdup(my_tempfile("ivrlh", &iconfig_file));
+      if (NULL == iconfig_file) {
+	    fprintf(stderr, "%s: Error opening temporary file %s\n",
+		    argv[0], iconfig_path);
+	    fprintf(stderr, "%s: Please check TMP or TMPDIR.\n", argv[0]);
+	    fclose(source_file);
+	    remove(source_path);
+	    return 1;
+      }
+
+      while ((opt = getopt(argc, argv, "B:C:c:D:Ef:g:hI:M:m:N::o:p:Ss:T:t:vVW:y:Y:")) != EOF) {
+
+	    switch (opt) {
+		case 'B':
+		  base = optarg;
+		  break;
+		case 'C':
+		  config_path = optarg;
+		  break;
+ 		case 'c':
+		  command_filename = malloc(strlen(optarg)+1);
+ 		  strcpy(command_filename, optarg);
+ 		  break;
+		case 'D':
+		  process_define(optarg);
+		  break;
+		case 'E':
+		  e_flag = 1;
+		  break;
+		case 'f':
+		  fprintf(stderr, "warning: The -f flag is moved to -p\n");
+		case 'p':
+		  if (f_list == 0) {
+			f_list = malloc(strlen(" -p")+strlen(optarg)+1);
+			strcpy(f_list, " -p");
+			strcat(f_list, optarg);
+		  } else {
+			f_list = realloc(f_list, strlen(f_list) +
+					 strlen(" -p") +
+					 strlen(optarg) + 1);
+			strcat(f_list, " -p");
+			strcat(f_list, optarg);
+		  }
+		  break;
+
+		case 'g':
+		  rc = process_generation(optarg);
+		  if (rc != 0)
+			return -1;
+		  break;
+ 		case 'h':
+ 		  fprintf(stderr, "%s\n", HELP);
+ 		  return 1;
+
+		case 'I':
+		  process_include_dir(optarg);
+		  break;
+
+		case 'M':
+		  depfile = optarg;
+		  break;
+
+		case 'm':
+		  if (mod_list == 0) {
+			mod_list = malloc(strlen(" -m")+strlen(optarg)+1);
+			strcpy(mod_list, " -m");
+			strcat(mod_list, optarg);
+		  } else {
+			mod_list = realloc(mod_list, strlen(mod_list)
+					   + strlen(" -m")
+					   + strlen(optarg) + 1);
+			strcat(mod_list, " -m");
+			strcat(mod_list, optarg);
+		  }
+		  break;
+
+		case 'N':
+		  npath = optarg;
+		  break;
+
+		case 'o':
+		  opath = optarg;
+		  break;
+
+		case 'S':
+		  synth_flag = 1;
+		  break;
+		case 's':
+	          if (start) {
+			static const char *s = " -s ";
+			size_t l = strlen(start);
+			start = realloc(start, l + strlen(optarg) + strlen(s) + 1);
+			strcpy(start + l, s);
+			strcpy(start + l + strlen(s), optarg);
+		  } else {
+			static const char *s = "-s ";
+			start = malloc(strlen(optarg) + strlen(s) + 1);
+			strcpy(start, s);
+			strcpy(start + strlen(s), optarg);
+		  }
+		  break;
+		case 'T':
+		  if (strcmp(optarg,"min") == 0) {
+			mtm = "min";
+		  } else if (strcmp(optarg,"typ") == 0) {
+			mtm = "typ";
+		  } else if (strcmp(optarg,"max") == 0) {
+			mtm = "max";
+		  } else {
+			fprintf(stderr, "%s: invalid -T%s argument\n",
+				argv[0], optarg);
+			return 1;
+		  }
+		  break;
+		case 't':
+		  targ = optarg;
+		  break;
+		case 'v':
+		  verbose_flag = 1;
+		  break;
+		case 'V':
+		  version_flag = 1;
+		  break;
+		case 'W':
+		  process_warning_switch(optarg);
+		  break;
+		case 'y':
+		  process_library_switch(optarg);
+		  break;
+		case 'Y':
+		  process_library2_switch(optarg);
+		  break;
+		case '?':
+		default:
+		  return 1;
+	    }
+      }
+
+      if (version_flag || verbose_flag) {
+	    printf("Icarus Verilog version " VERSION "\n");
+	    printf("Copyright 1998-2002 Stephen Williams\n");
+	    printf("$Name:  $\n");
+
+	    if (version_flag)
+		  return 0;
+      }
+
+      if (command_filename) {
+	    int rc;
+
+	    if (( fp = fopen(command_filename, "r")) == NULL ) {
+		  fprintf(stderr, "%s: Can't open %s\n",
+			  argv[0], command_filename);
+		  return 1;
+	    }
+
+	    cfreset(fp, command_filename);
+	    rc = cfparse();
+	    if (rc != 0) {
+		  fprintf(stderr, "%s: error reading command file\n",
+			  command_filename);
+		  return 1;
+	    }
+      }
+
+	/* Finally, process all the remaining words on the command
+	   line as file names. */
+      for (idx = optind ;  idx < argc ;  idx += 1)
+	    process_file_name(argv[idx]);
+
+
+      fclose(source_file);
+      source_file = 0;
+
+      if (source_count == 0) {
+	    fprintf(stderr, "%s: No input files.\n", argv[0]);
+ 	    fprintf(stderr, "%s\n", HELP);
+	    return 1;
+      }
+
+	/* Load the iverilog.conf file to get our substitution
+	   strings. */
+
+      { char path[1024];
+        FILE*fd;
+	if (config_path) {
+	      strcpy(path, config_path);
+	} else {
+	      sprintf(path, "%s%civerilog.conf", base,sep);
+	}
+	fd = fopen(path, "r");
+	if (fd == 0) {
+	      fprintf(stderr, "Config file \"%s\" not found\n",path);
+	      return 1;
+	}
+	reset_lexor(fd);
+	yyparse();
+      }
+
+	/* Start building the preprocess command line. */
+
+      sprintf(tmp, "%s%civlpp %s%s -D__ICARUS__=1 -f%s ", base,sep,
+	      verbose_flag?" -v":"",
+	      e_flag?"":" -L", source_path);
+
+      ncmd = strlen(tmp);
+      cmd = malloc(ncmd + 1);
+      strcpy(cmd, tmp);
+
+      if (inc_list) {
+	    cmd = realloc(cmd, ncmd + strlen(inc_list) + 1);
+	    strcat(cmd, inc_list);
+	    ncmd += strlen(inc_list);
+      }
+
+      if (def_list) {
+	    cmd = realloc(cmd, ncmd + strlen(def_list) + 1);
+	    strcat(cmd, def_list);
+	    ncmd += strlen(def_list);
+      }
+
+      if (depfile) {
+	    cmd = realloc(cmd, ncmd + strlen(depfile) + 5);
+	    strcat(cmd, " -M ");
+	    strcat(cmd, depfile);
+	    ncmd += strlen(depfile) + 4;
+      }
+
+	/* If the -E flag was given on the command line, then all we
+	   do is run the preprocessor and put the output where the
+	   user wants it. */
+      if (e_flag) {
+	    int rc;
+	    if (strcmp(opath,"-") != 0) {
+		  sprintf(tmp, " > %s", opath);
+		  cmd = realloc(cmd, ncmd+strlen(tmp)+1);
+		  strcpy(cmd+ncmd, tmp);
+		  ncmd += strlen(tmp);
+	    }
+
+	    if (verbose_flag)
+		  printf("preprocess: %s\n", cmd);
+
+	    rc = system(cmd);
+	    remove(source_path);
+	    fclose(iconfig_file);
+	    remove(iconfig_path);
+
+	    if (rc != 0) {
+		  if (WIFEXITED(rc)) {
+			fprintf(stderr, "errors preprocessing Verilog program.\n");
+			return WEXITSTATUS(rc);
+		  }
+
+		  fprintf(stderr, "Command signaled: %s\n", cmd);
+		  return -1;
+	    }
+
+	    return 0;
+      }
+
+	/* Write the preprocessor command needed to preprocess a
+	   single file. This may be used to preprocess library
+	   files. */
+      fprintf(iconfig_file, "ivlpp:%s%civlpp -D__ICARUS__ -L %s %s\n",
+	      base, sep,
+	      inc_list? inc_list : "",
+	      def_list? def_list : "");
+
+	/* Done writing to the iconfig file. Close it now. */
+      fclose(iconfig_file);
+
+      return t_default(cmd, ncmd);
+
+      return 0;
+}
+
+/*
+ * $Log: main.c,v $
+ * Revision 1.49  2002/12/04 03:26:59  steve
+ *  Mingw32 compatible temp file management.
+ *
+ * Revision 1.48  2002/12/04 02:29:36  steve
+ *  Use O_EXCL when opening temp files.
+ *
+ * Revision 1.47  2002/08/12 01:27:48  steve
+ *  Escape the backslash in the windows file name.
+ *
+ * Revision 1.46  2002/08/10 22:36:59  steve
+ *  No longer any nead for -rdynamic flag
+ *
+ * Revision 1.45  2002/08/10 22:27:13  steve
+ *  Kill links to vvm.
+ *
+ * Revision 1.44  2002/07/15 00:33:50  steve
+ *  Improve temporary file name guess.
+ *
+ * Revision 1.43  2002/07/14 23:32:31  steve
+ *  No longer need the .exe on generated files.
+ *
+ * Revision 1.42  2002/07/14 23:11:35  steve
+ *  Do temp file creation by hand.
+ *
+ * Revision 1.41  2002/05/28 20:40:37  steve
+ *  ivl indexes the search path for libraries, and
+ *  supports case insensitive module-to-file lookup.
+ *
+ * Revision 1.40  2002/05/28 02:25:03  steve
+ *  Pass library paths through -Cfile instead of command line.
+ *
+ * Revision 1.39  2002/05/28 00:50:40  steve
+ *  Add the ivl -C flag for bulk configuration
+ *  from the driver, and use that to run library
+ *  modules through the preprocessor.
+ *
+ * Revision 1.38  2002/05/27 23:14:06  steve
+ *  Predefine __ICARUS__
+ *
+ * Revision 1.37  2002/05/24 01:13:00  steve
+ *  Support language generation flag -g.
+ *
+ * Revision 1.36  2002/04/24 02:02:31  steve
+ *  add -Wno- arguments to the driver.
+ *
+ * Revision 1.35  2002/04/15 00:04:23  steve
+ *  Timescale warnings.
+ *
+ * Revision 1.34  2002/04/04 05:26:13  steve
+ *  Add dependency generation.
+ *
+ * Revision 1.33  2002/03/15 23:27:42  steve
+ *  Patch to allow user to set place for temporary files.
+ *
+ * Revision 1.32  2002/02/03 07:05:37  steve
+ *  Support print of version number.
+ *
+ * Revision 1.31  2001/11/21 02:20:34  steve
+ *  Pass list of file to ivlpp via temporary file.
+ *
+ * Revision 1.30  2001/11/16 05:07:19  steve
+ *  Add support for +libext+ in command files.
+ *
+ * Revision 1.29  2001/11/13 03:30:26  steve
+ *  The +incdir+ plusarg can take multiple directores,
+ *  and add initial support for +define+ in the command file.
+ *
+ * Revision 1.28  2001/11/12 18:47:32  steve
+ *  Support +incdir in command files, and ignore other
+ *  +args flags. Also ignore -a and -v flags.
+ *
+ * Revision 1.27  2001/11/12 01:26:36  steve
+ *  More sophisticated command file parser.
+ *
+ * Revision 1.26  2001/11/11 00:10:05  steve
+ *  Remov XNF dead wood.
+ *
+ * Revision 1.25  2001/10/23 00:37:30  steve
+ *  The -s flag can now be repeated on the iverilog command.
+ *
+ * Revision 1.24  2001/10/20 23:02:40  steve
+ *  Add automatic module libraries.
+ *
+ * Revision 1.23  2001/10/19 23:10:08  steve
+ *  Fix memory fault with -c flag.
+ *
+ * Revision 1.22  2001/10/11 00:12:49  steve
+ *  Detect execv failures.
+ *
+ * Revision 1.21  2001/07/25 03:10:50  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
+ * Revision 1.20  2001/06/30 21:53:42  steve
+ *  Make the vvp target the default.
+ *
+ * Revision 1.19  2001/06/30 04:23:02  steve
+ *  Get include and lib paths right for mingw and vvm.
+ *
+ * Revision 1.18  2001/06/30 00:59:24  steve
+ *  Redo the ivl_root calculator for mingw.
+ *
+ * Revision 1.17  2001/06/27 02:22:26  steve
+ *  Get include and lib paths from Makefile.
+ *
+ * Revision 1.16  2001/06/20 02:25:40  steve
+ *  Edit ivl_install_dir only on mingw
+ *
+ * Revision 1.15  2001/06/15 05:14:21  steve
+ *  Fix library path calculation on non Windows systems
+ *  to include the install directories. (Brendan Simon)
+ *
+ * Revision 1.14  2001/06/12 03:53:10  steve
+ *  Change the VPI call process so that loaded .vpi modules
+ *  use a function table instead of implicit binding.
+ *
+ * Revision 1.13  2001/05/20 18:22:02  steve
+ *  Fix WIFEXITED macro.
+ *
+ * Revision 1.12  2001/05/20 18:06:57  steve
+ *  local declares if the header is missing.
+ *
+ * Revision 1.11  2001/05/20 15:09:40  steve
+ *  Mingw32 support (Venkat Iyer)
+ *
+ * Revision 1.10  2001/05/17 03:14:26  steve
+ *  Update help message.
+ *
+ * Revision 1.9  2001/04/26 16:04:39  steve
+ *  Handle missing or uninstalled .conf files.
+ *
+ * Revision 1.8  2001/02/01 17:12:22  steve
+ *  Forgot to actually allow the -p flag.
+ *
+ * Revision 1.7  2001/01/20 19:02:05  steve
+ *  Switch hte -f flag to the -p flag.
+ */
+

driver/parse.y

@@ -0,0 +1,167 @@
+%{
+/*
+ * Copyright (c) 2000 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#if !defined(WINNT) && !defined(macintosh)
+#ident "$Id: parse.y,v 1.5 2002/03/31 04:07:16 steve Exp $"
+#endif
+
+# include "config.h"
+
+# include  <stdio.h>
+#ifdef HAVE_MALLOC_H
+# include  <malloc.h>
+#endif
+# include  <stdlib.h>
+# include  "globals.h"
+
+
+void yyerror(const char*);
+
+enum drive_code_t {
+      CODE_S,
+      CODE_t,
+};
+
+struct drive_cond {
+      struct drive_cond*next;
+      enum drive_code_t code;
+      char* text;
+};
+
+static struct drive_cond *cur_cond = 0;
+
+static void add_cond(enum drive_code_t code, char*text)
+{
+      struct drive_cond*tmp;
+      tmp = calloc(1, sizeof(struct drive_cond));
+      tmp->code = code;
+      tmp->text = text;
+
+      tmp->next = cur_cond;
+      cur_cond = tmp;
+}
+
+struct drive_pattern {
+      struct drive_pattern*next;
+      char*name;
+      char*text;
+      struct drive_cond*cond;
+};
+
+static struct drive_pattern *patterns = 0;
+static struct drive_pattern *plast = 0;
+
+static void add_pattern(char*name, char*text)
+{
+      struct drive_pattern*tmp;
+      tmp = calloc(1, sizeof(struct drive_pattern));
+      tmp->name = name;
+      tmp->text = text;
+      tmp->cond = cur_cond;
+      tmp->next = 0;
+
+
+      if (plast) {
+	    plast->next = tmp;
+	    plast = tmp;
+      } else {
+	    patterns = tmp;
+	    plast = tmp;
+      }
+}
+
+const char*lookup_pattern(const char*key)
+{
+      struct drive_pattern*cur;
+      struct drive_cond*cc;
+
+      for (cur = patterns ;  cur ;  cur = cur->next) {
+
+	    if (strcmp(key, cur->name) != 0)
+		  continue;
+
+	    for (cc = cur->cond ;  cc ;  cc = cc->next) {
+
+		  switch (cc->code) {
+		      case CODE_S:
+			if (synth_flag)
+			      continue;
+			break;
+		      case CODE_t:
+			if (strcmp(targ, cc->text) == 0)
+			      continue;
+			break;
+		  }
+
+		  break;
+	    }
+
+	    if (cc) continue;
+
+	    return cur->text;
+      }
+
+      return 0;
+}
+
+%}
+
+%union {
+      char*text;
+};
+
+%token <text> PATTERN_NAME PATTERN_TEXT
+%token <text> CT_t
+%token CT_S
+
+%%
+
+start: section_list ;
+
+section_list
+	: section
+	| section_list section
+	;
+
+section : '[' ctoken_list ']' pattern_list { cur_cond = 0; } ;
+
+ctoken_list
+	: ctoken
+	| ctoken_list ctoken
+	;
+
+ctoken  : CT_S  { add_cond(CODE_S, 0); }
+	| CT_t  { add_cond(CODE_t, $1); }
+	;
+
+pattern_list
+	: pattern
+	| pattern_list pattern
+	;
+
+pattern : PATTERN_NAME PATTERN_TEXT
+		{ add_pattern($1, $2); }
+	;
+
+%%
+
+void yyerror(const char*msg)
+{
+      fprintf(stderr, "%s\n", msg);
+}

driver/substit.c

@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2002 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: substit.c,v 1.4 2002/08/12 01:35:01 steve Exp $"
+#endif
+
+# include  <string.h>
+# include  <stdlib.h>
+#ifdef HAVE_MALLOC_H
+# include  <malloc.h>
+#endif
+
+
+char* substitutions(const char*str)
+{
+      size_t nbuf = strlen(str) + 1;
+      char*buf = malloc(nbuf);
+      char*cp = buf;
+
+      while (*str) {
+
+	    if ((str[0] == '$') && (str[1] == '(')) {
+		    /* If I find a $(x) string in the source, replace
+		       it in the destination with the contents of the
+		       environment variable x. */
+		  char*name;
+		  char*value;
+		  const char*ep = strchr(str, ')');
+		  str += 2;
+
+		  name = malloc(ep-str+1);
+		  strncpy(name, str, ep-str);
+		  name[ep-str] = 0;
+
+		  str = ep + 1;
+
+		  value = getenv(name);
+		  free(name);
+		  if (value == 0)
+			continue;
+
+		  if (strlen(value) >= (nbuf - (cp-buf))) {
+			size_t old_size = cp - buf;
+			nbuf = (cp - buf) + strlen(value) + 1;
+			buf = realloc(buf, nbuf);
+			cp = buf + old_size;
+		  }
+
+		  strcpy(cp, value);
+		  cp += strlen(cp);
+
+	    } else {
+		  if ( (cp - buf) == nbuf ) {
+			size_t old_size = nbuf;
+			nbuf = old_size + 32;
+			buf = realloc(buf, nbuf);
+			cp = buf + old_size;
+		  }
+
+		  *cp++ = *str++;
+	    }
+      }
+
+	/* Add the trailing nul to the string, and reallocate the
+	   buffer to be a tight fit. */
+      if ( (cp - buf) == nbuf ) {
+	    size_t old_size = nbuf;
+	    nbuf = old_size + 1;
+	    buf = realloc(buf, nbuf);
+	    buf[old_size] = 0;
+      } else {
+	    *cp++ = 0;
+	    nbuf = cp - buf;
+	    buf = realloc(buf, nbuf);
+      }
+
+      return buf;
+}
+
+
+/*
+ * $Log: substit.c,v $
+ * Revision 1.4  2002/08/12 01:35:01  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.3  2002/08/11 23:47:04  steve
+ *  Add missing Log and Ident strings.
+ *
+ * Revision 1.2  2002/06/25 01:33:01  steve
+ *  include malloc.h only when available.
+ *
+ * Revision 1.1  2002/06/23 20:10:51  steve
+ *  Variable substitution in command files.
+ *
+ */
+

dup_expr.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999 Stephen Williams ([email protected])
+ * Copyright (c) 1999-2002 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -16,10 +16,12 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: dup_expr.cc,v 1.4 2000/05/07 18:20:07 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: dup_expr.cc,v 1.9 2002/11/09 00:25:27 steve Exp $"
 #endif
 
+# include "config.h"
+
 # include  "netlist.h"
 # include  <cassert>
 
@@ -29,17 +31,83 @@ NetEScope* NetEScope::dup_expr() const
       return 0;
 }
 
+NetESelect* NetESelect::dup_expr() const
+{
+      return new NetESelect(expr_->dup_expr(), base_->dup_expr(),
+			    expr_width());
+}
+
 NetESFunc* NetESFunc::dup_expr() const
 {
       NetESFunc*tmp = new NetESFunc(name_, expr_width(), nparms());
-      for (unsigned idx = 0 ;  idx < nparms() ;  idx += 1)
+      assert(tmp);
+      for (unsigned idx = 0 ;  idx < nparms() ;  idx += 1) {
+	    assert(tmp->parm(idx));
 	    tmp->parm(idx, tmp->parm(idx)->dup_expr());
+      }
 
       return tmp;
 }
 
+NetESignal* NetESignal::dup_expr() const
+{
+      NetESignal*tmp = new NetESignal(net_, msi_, lsi_);
+      assert(tmp);
+      tmp->expr_width(expr_width());
+      return tmp;
+}
+
+NetETernary* NetETernary::dup_expr() const
+{
+      NetETernary*tmp = new NetETernary(cond_->dup_expr(),
+					true_val_->dup_expr(),
+					false_val_->dup_expr());
+      return tmp;
+}
+
+NetEUFunc* NetEUFunc::dup_expr() const
+{
+      NetEUFunc*tmp;
+      svector<NetExpr*> tmp_parms (parms_.count());
+
+      for (unsigned idx = 0 ;  idx < tmp_parms.count() ;  idx += 1) {
+	    assert(parms_[idx]);
+	    tmp_parms[idx] = parms_[idx]->dup_expr();
+      }
+
+      tmp = new NetEUFunc(func_, result_->dup_expr(), tmp_parms);
+
+      return tmp;
+}
+
+NetEUnary* NetEUnary::dup_expr() const
+{
+      NetEUnary*tmp = new NetEUnary(op_, expr_->dup_expr());
+      assert(tmp);
+      return tmp;
+}
+
 /*
  * $Log: dup_expr.cc,v $
+ * Revision 1.9  2002/11/09 00:25:27  steve
+ *  Add dup_expr for user defined function calls.
+ *
+ * Revision 1.8  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.7  2002/01/28 00:52:41  steve
+ *  Add support for bit select of parameters.
+ *  This leads to a NetESelect node and the
+ *  vvp code generator to support that.
+ *
+ * Revision 1.6  2001/11/19 01:54:14  steve
+ *  Port close cropping behavior from mcrgb
+ *  Move window array reset to libmc.
+ *
+ * Revision 1.5  2001/07/25 03:10:48  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
  * Revision 1.4  2000/05/07 18:20:07  steve
  *  Import MCD support from Stephen Tell, and add
  *  system function parameter support to the IVL core.
@@ -47,12 +115,5 @@ NetESFunc* NetESFunc::dup_expr() const
  * Revision 1.3  2000/05/04 03:37:58  steve
  *  Add infrastructure for system functions, move
  *  $time to that structure and add $random.
- *
- * Revision 1.2  2000/02/23 02:56:54  steve
- *  Macintosh compilers do not support ident.
- *
- * Revision 1.1  1999/11/27 19:07:57  steve
- *  Support the creation of scopes.
- *
  */
 

elab_anet.cc

@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2000 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: elab_anet.cc,v 1.5 2002/08/12 01:34:58 steve Exp $"
+#endif
+
+# include "config.h"
+
+/*
+ * The elaborate_anet methods elaborate expressions that are intended
+ * to be the left side of procedural continuous assignments.
+ */
+
+# include  "PExpr.h"
+# include  "netlist.h"
+# include  <iostream>
+
+NetNet* PExpr::elaborate_anet(Design*des, NetScope*scope) const
+{
+      cerr << get_line() << ": error: Invalid expression on left side "
+	   << "of precedural continuous asignment." << endl;
+      return 0;
+}
+
+
+NetNet* PEConcat::elaborate_anet(Design*des, NetScope*scope) const
+{
+      if (repeat_) {
+	    cerr << get_line() << ": error: Repeat concatenations make "
+		  "no sense in l-value expressions. I refuse." << endl;
+	    des->errors += 1;
+	    return 0;
+      }
+
+      svector<NetNet*>nets (parms_.count());
+      unsigned pins = 0;
+      unsigned errors = 0;
+
+      for (unsigned idx = 0 ;  idx < nets.count() ;  idx += 1) {
+
+	    if (parms_[idx] == 0) {
+		  cerr << get_line() << ": error: Empty expressions "
+		       << "not allowed in concatenations." << endl;
+		  errors += 1;
+		  continue;
+	    }
+
+	    nets[idx] = parms_[idx]->elaborate_anet(des, scope);
+	    if (nets[idx] == 0)
+		  errors += 1;
+	    else
+		  pins += nets[idx]->pin_count();
+      }
+
+	/* If any of the sub expressions failed to elaborate, then
+	   delete all those that did and abort myself. */
+      if (errors) {
+	    for (unsigned idx = 0 ;  idx < nets.count() ;  idx += 1) {
+		  if (nets[idx]) delete nets[idx];
+	    }
+	    des->errors += 1;
+	    return 0;
+      }
+
+	/* Make the temporary signal that connects to all the
+	   operands, and connect it up. Scan the operands of the
+	   concat operator from least significant to most significant,
+	   which is opposite from how they are given in the list.
+
+	   Allow for a repeat count other then 1 by repeating the
+	   connect loop as many times as necessary. */
+
+      NetNet*osig = new NetNet(scope, des->local_symbol(scope->name()),
+			       NetNet::IMPLICIT_REG, pins);
+
+      pins = 0;
+      for (unsigned idx = nets.count() ;  idx > 0 ;  idx -= 1) {
+	    NetNet*cur = nets[idx-1];
+	    for (unsigned pin = 0;  pin < cur->pin_count();  pin += 1) {
+		  connect(osig->pin(pins), cur->pin(pin));
+		  pins += 1;
+	    }
+      }
+
+      osig->local_flag(true);
+      return osig;
+}
+
+NetNet* PEIdent::elaborate_anet(Design*des, NetScope*scope) const
+{
+      NetNet*sig = des->find_signal(scope, path_);
+
+      if (sig == 0) {
+	    if (NetMemory*mem = des->find_memory(scope, path_)) {
+		  cerr << get_line() << ": error: memories not allowed "
+		       << "on left side of procedural continuous "
+		       << "asignment." << endl;
+		  des->errors += 1;
+		  return 0;
+	    }
+
+	    cerr << get_line() << ": error: reg ``" << path_ << "'' "
+		 << "is undefined in this scope." << endl;
+	    des->errors += 1;
+	    return 0;
+      }
+
+      switch (sig->type()) {
+	  case NetNet::REG:
+	  case NetNet::IMPLICIT_REG:
+	    break;
+
+	  default:
+	    cerr << get_line() << ": error: " << path_ << " is not "
+		 << "a reg in this context." << endl;
+	    des->errors += 1;
+	    return 0;
+      }
+
+      assert(sig);
+
+      if (msb_ || lsb_) {
+
+	    cerr << get_line() << ": error: bit/part selects not allowed "
+		 << "on left side of procedural continuous asignment."
+		 << endl; 
+	    des->errors += 1;
+	    return 0;
+      }
+
+      return sig;
+}
+
+/*
+ * $Log: elab_anet.cc,v $
+ * Revision 1.5  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.4  2001/12/03 04:47:14  steve
+ *  Parser and pform use hierarchical names as hname_t
+ *  objects instead of encoded strings.
+ *
+ * Revision 1.3  2001/07/25 03:10:48  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
+ * Revision 1.2  2001/01/06 02:29:36  steve
+ *  Support arrays of integers.
+ *
+ * Revision 1.1  2000/12/06 06:31:09  steve
+ *  Check lvalue of procedural continuous assign (PR#29)
+ *
+ */
+

elab_expr.cc

@@ -16,18 +16,25 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: elab_expr.cc,v 1.26 2000/05/19 01:55:09 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: elab_expr.cc,v 1.66 2002/09/21 21:28:18 steve Exp $"
 #endif
 
+# include "config.h"
+
 
 # include  "pform.h"
 # include  "netlist.h"
+# include  "netmisc.h"
+# include  "util.h"
 
-NetExpr* PExpr::elaborate_expr(Design*des, NetScope*) const
+NetExpr* PExpr::elaborate_expr(Design*des, NetScope*, bool) const
 {
-      cerr << get_line() << ": I do not know how to elaborate expression: "
-	   << *this << endl;
+      cerr << get_line() << ": internal error: I do not know how to elaborate"
+	   << " expression. " << endl;
+      cerr << get_line() << ":               : Expression is: " << *this
+	   << endl;
+      des->errors += 1;
       return 0;
 }
 
@@ -36,8 +43,11 @@ NetExpr* PExpr::elaborate_expr(Design*des, NetScope*) const
  * and right sides, and creating one of a variety of different NetExpr
  * types. 
  */
-NetEBinary* PEBinary::elaborate_expr(Design*des, NetScope*scope) const
+NetEBinary* PEBinary::elaborate_expr(Design*des, NetScope*scope, bool) const
 {
+      assert(left_);
+      assert(right_);
+
       NetExpr*lp = left_->elaborate_expr(des, scope);
       NetExpr*rp = right_->elaborate_expr(des, scope);
       if ((lp == 0) || (rp == 0)) {
@@ -46,6 +56,7 @@ NetEBinary* PEBinary::elaborate_expr(Design*des, NetScope*scope) const
 	    return 0;
       }
 
+
 	/* If either expression can be evaluated ahead of time, then
 	   do so. This can prove helpful later. */
       { NetExpr*tmp;
@@ -54,6 +65,7 @@ NetEBinary* PEBinary::elaborate_expr(Design*des, NetScope*scope) const
 	      delete lp;
 	      lp = tmp;
 	}
+
 	tmp = rp->eval_tree();
 	if (tmp) {
 	      delete rp;
@@ -108,7 +120,8 @@ NetEBinary* PEBinary::elaborate_expr_base_(Design*des,
 	  case '^':
 	  case '&':
 	  case '|':
-	  case 'O':
+	  case 'O': // NOR (~|)
+	  case 'A': // NAND (~&)
 	  case 'X':
 	    tmp = new NetEBBits(op_, lp, rp);
 	    tmp->set_line(*this);
@@ -142,62 +155,187 @@ NetEBinary* PEBinary::elaborate_expr_base_(Design*des,
       return tmp;
 }
 
+/*
+ * Given a call to a system function, generate the proper expression
+ * nodes to represent the call in the netlist. Since we don't support
+ * size_tf functions, make assumptions about widths based on some
+ * known function names.
+ */
 NetExpr* PECallFunction::elaborate_sfunc_(Design*des, NetScope*scope) const
 {
+
+	/* Catch the special case that the system function is the
+	   $signed function. This function is special, in that it does
+	   not lead to executable code but takes the single parameter
+	   and makes it into a signed expression. No bits are changed,
+	   it just changes the interpretation. */
+      if (strcmp(path_.peek_name(0), "$signed") == 0) {
+	    if ((parms_.count() != 1) || (parms_[0] == 0)) {
+		  cerr << get_line() << ": error: The $signed() function "
+		       << "takes exactly one(1) argument." << endl;
+		  des->errors += 1;
+		  return 0;
+	    }
+
+	    PExpr*expr = parms_[0];
+	    NetExpr*sub = expr->elaborate_expr(des, scope, true);
+	    sub->cast_signed(true);
+	    return sub;
+      }
+
+	/* Interpret the internal $sizeof system function to return
+	   the bit width of the sub-expression. The value of the
+	   sub-expression is not used, so the expression itself can be
+	   deleted. */
+      if ((strcmp(path_.peek_name(0), "$sizeof") == 0)
+	  || (strcmp(path_.peek_name(0), "$bits") == 0)) {
+	    if ((parms_.count() != 1) || (parms_[0] == 0)) {
+		  cerr << get_line() << ": error: The $bits() function "
+		       << "takes exactly one(1) argument." << endl;
+		  des->errors += 1;
+		  return 0;
+	    }
+
+	    if (strcmp(path_.peek_name(0), "$sizeof") == 0)
+		  cerr << get_line() << ": warning: $sizeof is deprecated."
+		       << " Use $bits() instead." << endl;
+
+	    PExpr*expr = parms_[0];
+	    NetExpr*sub = expr->elaborate_expr(des, scope, true);
+	    verinum val (sub->expr_width(), 8*sizeof(unsigned));
+	    delete sub;
+
+	    sub = new NetEConst(val);
+	    sub->set_line(*this);
+
+	    return sub;
+      }
+
       unsigned wid = 32;
 
-      if (name_ == "$time")
+      if (strcmp(path_.peek_name(0), "$time") == 0)
 	    wid = 64;
+      if (strcmp(path_.peek_name(0), "$stime") == 0)
+	    wid = 32;
 
-      NetESFunc*fun = new NetESFunc(name_, wid, parms_.count());
-      for (unsigned idx = 0 ;  idx < parms_.count() ;  idx += 1) {
+
+	/* How many parameters are there? The Verilog language allows
+	   empty parameters in certain contexts, so the parser will
+	   allow things like func(1,,3). It will also cause func() to
+	   be interpreted as a single empty parameter.
+
+	   Functions cannot really take empty parameters, but the
+	   case ``func()'' is the same as no parmaters at all. So
+	   catch that special case here. */
+      unsigned nparms = parms_.count();
+      if ((nparms == 1) && (parms_[0] == 0))
+	    nparms = 0;
+
+      NetESFunc*fun = new NetESFunc(path_.peek_name(0), wid, nparms);
+
+	/* Now run through the expected parameters. If we find that
+	   there are missing parameters, print an error message.
+
+	   While we're at it, try to evaluate the function parameter
+	   expression as much as possible, and use the reduced
+	   expression if one is created. */
+
+      unsigned missing_parms = 0;
+      for (unsigned idx = 0 ;  idx < nparms ;  idx += 1) {
 	    PExpr*expr = parms_[idx];
-	    NetExpr*tmp = expr->elaborate_expr(des, scope);
-	    fun->parm(idx, tmp);
+	    if (expr) {
+		  NetExpr*tmp1 = expr->elaborate_expr(des, scope, true);
+		  if (NetExpr*tmp2 = tmp1->eval_tree()) {
+			delete tmp1;
+			fun->parm(idx, tmp2);
+		  } else {
+			fun->parm(idx, tmp1);
+		  }
+
+	    } else {
+		  missing_parms += 1;
+		  fun->parm(idx, 0);
+	    }
+      }
+
+      if (missing_parms > 0) {
+	    cerr << get_line() << ": error: The function "
+		 << path_.peek_name(0)
+		 << " has been called with empty parameters." << endl;
+	    cerr << get_line() << ":      : Verilog doesn't allow "
+		 << "passing empty parameters to functions." << endl;
+	    des->errors += 1;
       }
 
       return fun;
 }
 
-NetExpr* PECallFunction::elaborate_expr(Design*des, NetScope*scope) const
+NetExpr* PECallFunction::elaborate_expr(Design*des, NetScope*scope, bool) const
 {
-      if (name_[0] == '$')
+      if (path_.peek_name(0)[0] == '$')
 	    return elaborate_sfunc_(des, scope);
 
-      NetFuncDef*def = des->find_function(scope->name(), name_);
+      NetFuncDef*def = des->find_function(scope, path_);
       if (def == 0) {
-	    cerr << get_line() << ": error: No function " << name_ <<
+	    cerr << get_line() << ": error: No function " << path_ <<
 		  " in this context (" << scope->name() << ")." << endl;
 	    des->errors += 1;
 	    return 0;
       }
       assert(def);
 
-      NetScope*dscope = des->find_scope(def->name());
+      NetScope*dscope = def->scope();
       assert(dscope);
 
-      svector<NetExpr*> parms (parms_.count());
+      if (! check_call_matches_definition_(des, dscope))
+	    return 0;
+
+      unsigned parms_count = parms_.count();
+      if ((parms_count == 1) && (parms_[0] == 0))
+	    parms_count = 0;
+
+      
+
+      svector<NetExpr*> parms (parms_count);
 
 	/* Elaborate the input expressions for the function. This is
 	   done in the scope of the function call, and not the scope
 	   of the function being called. The scope of the called
 	   function is elaborated when the definition is elaborated. */
 
+      unsigned missing_parms = 0;
       for (unsigned idx = 0 ;  idx < parms.count() ;  idx += 1) {
-	    NetExpr*tmp = parms_[idx]->elaborate_expr(des, scope);
-	    parms[idx] = tmp;
+	    PExpr*tmp = parms_[idx];
+	    if (tmp) {
+		  parms[idx] = tmp->elaborate_expr(des, scope);
+
+	    } else {
+		  missing_parms += 1;
+		  parms[idx] = 0;
+	    }
+      }
+
+      if (missing_parms > 0) {
+	    cerr << get_line() << ": error: The function " << path_
+		 << " has been called with empty parameters." << endl;
+	    cerr << get_line() << ":      : Verilog doesn't allow "
+		 << "passing empty parameters to functions." << endl;
+	    des->errors += 1;
       }
 
 
 	/* Look for the return value signal for the called
 	   function. This return value is a magic signal in the scope
 	   of the function, that has the name of the function. The
-	   function code assigns to this signal to return a value. */
+	   function code assigns to this signal to return a value.
 
-      NetNet*res = des->find_signal(dscope, name_);
+	   dscope, in this case, is the scope of the function, so the
+	   return value is the name within that scope. */
+
+      NetNet*res = dscope->find_signal(dscope->basename());
       if (res == 0) {
 	    cerr << get_line() << ": internal error: Unable to locate "
-		  "function return value for " << name_ << " in " <<
+		  "function return value for " << path_ << " in " <<
 		  def->name() << "." << endl;
 	    des->errors += 1;
 	    return 0;
@@ -206,62 +344,208 @@ NetExpr* PECallFunction::elaborate_expr(Design*des, NetScope*scope) const
       assert(res);
       NetESignal*eres = new NetESignal(res);
       assert(eres);
-      NetEUFunc*func = new NetEUFunc(def, eres, parms);
+      NetEUFunc*func = new NetEUFunc(dscope, eres, parms);
       return func;
 }
 
 
-NetExpr* PEConcat::elaborate_expr(Design*des, NetScope*scope) const
+NetExpr* PEConcat::elaborate_expr(Design*des, NetScope*scope, bool) const
 {
-      unsigned repeat = 1;
+      NetExpr* repeat = 0;
 
 	/* If there is a repeat expression, then evaluate the constant
 	   value and set the repeat count. */
       if (repeat_) {
-	    verinum*vrep = repeat_->eval_const(des, scope->name());
-	    if (vrep == 0) {
+	    NetExpr*tmp = elab_and_eval(des, scope, repeat_);
+	    assert(tmp);
+	    NetEConst*rep = dynamic_cast<NetEConst*>(tmp);
+
+	    if (rep == 0) {
 		  cerr << get_line() << ": error: "
 			"concatenation repeat expression cannot be evaluated."
 		       << endl;
+		  cerr << get_line() << ":      : The expression is: "
+		       << *tmp << endl;
 		  des->errors += 1;
-		  return 0;
 	    }
 
-	    repeat = vrep->as_ulong();
-	    delete vrep;
+	    repeat = rep;
       }
 
 	/* Make the empty concat expression. */
       NetEConcat*tmp = new NetEConcat(parms_.count(), repeat);
       tmp->set_line(*this);
 
+      unsigned wid_sum = 0;
+
 	/* Elaborate all the parameters and attach them to the concat node. */
       for (unsigned idx = 0 ;  idx < parms_.count() ;  idx += 1) {
 	    assert(parms_[idx]);
-	    NetExpr*ex = parms_[idx]->elaborate_expr(des, scope);
+	    NetExpr*ex = elab_and_eval(des, scope, parms_[idx]);
 	    if (ex == 0) continue;
+
 	    ex->set_line(*parms_[idx]);
+
+	    if (! ex->has_width()) {
+		  cerr << ex->get_line() << ": error: operand of "
+		       << "concatenation has indefinite width: "
+		       << *ex << endl;
+		  des->errors += 1;
+	    }
+
+	    wid_sum += ex->expr_width();
 	    tmp->set(idx, ex);
       }
 
+      tmp->set_width(wid_sum * tmp->repeat());
+
       return tmp;
 }
 
-NetExpr* PEIdent::elaborate_expr(Design*des, NetScope*scope) const
+NetExpr* PEFNumber::elaborate_expr(Design*des, NetScope*scope, bool) const
 {
-      assert(text_[0] != '$');
+      long val = value_->as_long();
+      return new NetEConst(verinum(val));
+}
 
-	//string name = path+"."+text_;
+/*
+ * Elaborate an identifier in an expression. The identifier can be a
+ * parameter name, a signal name or a memory name. It can also be a
+ * scope name (Return a NetEScope) but only certain callers can use
+ * scope names. However, we still support it here.
+ *
+ * Function names are not handled here, they are detected by the
+ * parser and are elaborated by PECallFunction.
+ *
+ * The signal name may be escaped, but that affects nothing here.
+ */
+NetExpr* PEIdent::elaborate_expr(Design*des, NetScope*scope,
+				 bool sys_task_arg) const
+{
       assert(scope);
 
 	// If the identifier name is a parameter name, then return
 	// a reference to the parameter expression.
-      if (const NetExpr*ex = des->find_parameter(scope, text_)) {
+      if (const NetExpr*ex = des->find_parameter(scope, path_)) {
 	    NetExpr*tmp;
 	    if (dynamic_cast<const NetExpr*>(ex))
 		  tmp = ex->dup_expr();
 	    else
-		  tmp = new NetEParam(des, scope, text_);
+		  tmp = new NetEParam(des, scope, path_);
+
+	    if (msb_ && lsb_) {
+		    /* If the parameter has a part select, we support
+		       it by pulling the right bits out and making a
+		       sized unsigned constant. This code assumes the
+		       lsb of a parameter is 0 and the msb is the
+		       width of the parameter. */
+
+		  verinum*lsn = lsb_->eval_const(des, scope);
+		  verinum*msn = msb_->eval_const(des, scope);
+		  if ((lsn == 0) || (msn == 0)) {
+			cerr << get_line() << ": error: "
+			      "Part select expresions must be "
+			      "constant expressions." << endl;
+			des->errors += 1;
+			return 0;
+		  }
+
+		  long lsb = lsn->as_long();
+		  long msb = msn->as_long();
+		  if ((lsb < 0) || (msb < lsb)) {
+			cerr << get_line() << ": error: invalid part "
+			     << "select: " << path_
+			     << "["<<msb<<":"<<lsb<<"]" << endl;
+			des->errors += 1;
+			return 0;
+		  }
+
+		  NetEConst*le = dynamic_cast<NetEConst*>(tmp);
+		  assert(le);
+
+		  verinum result (verinum::V0, msb-lsb+1, true);
+		  verinum exl = le->value();
+
+		    /* Pull the bits from the parameter, one at a
+		       time. If the bit is within the range, simply
+		       copy it to the result. If the bit is outside
+		       the range, we sign extend signed unsized
+		       numbers, zero extend unsigned unsigned numbers,
+		       and X extend sized numbers. */
+		  for (long idx = lsb ;  idx <= msb ;  idx += 1) {
+			if (idx < exl.len())
+			      result.set(idx-lsb, exl.get(idx));
+		        else if (exl.is_string())
+			      result.set(idx-lsb, verinum::V0);
+		        else if (exl.has_len())
+			      result.set(idx-lsb, verinum::Vx);
+		        else if (exl.has_sign())
+			      result.set(idx-lsb, exl.get(exl.len()-1));
+		        else
+			      result.set(idx-lsb, verinum::V0);
+		  }
+
+		    /* If the input is a string, and the part select
+		       is working on byte boundaries, then the result
+		       can be made into a string. */
+		  if (exl.is_string()
+		      && (lsb%8 == 0)
+		      && (result.len()%8 == 0))
+		      result = verinum(result.as_string());
+
+		  delete tmp;
+		  tmp = new NetEConst(result);
+
+	    } else if (msb_) {
+		    /* Handle the case where a parameter has a bit
+		       select attached to it. Generate a NetESelect
+		       object to select the bit as desired. */
+		  NetExpr*mtmp = msb_->elaborate_expr(des, scope);
+		  if (! dynamic_cast<NetEConst*>(mtmp)) {
+			NetExpr*re = mtmp->eval_tree();
+			if (re) {
+			      delete mtmp;
+			      mtmp = re;
+			}
+		  }
+
+		    /* Let's first try to get constant values for both
+		       the parameter and the bit select. If they are
+		       both constant, then evaluate the bit select and
+		       return instead a single-bit constant. */
+
+		  NetEConst*le = dynamic_cast<NetEConst*>(tmp);
+		  NetEConst*re = dynamic_cast<NetEConst*>(mtmp);
+		  if (le && re) {
+
+			verinum lv = le->value();
+			verinum rv = re->value();
+			verinum::V rb = verinum::Vx;
+
+			long ridx = rv.as_long();
+			if ((ridx >= 0) && (ridx < lv.len())) {
+			      rb = lv[ridx];
+
+			} else if ((ridx >= 0) && (!lv.has_len())) {
+			      if (lv.has_sign())
+				    rb = lv[lv.len()-1];
+			      else
+				    rb = verinum::V0;
+			}
+
+			NetEConst*re = new NetEConst(verinum(rb, 1));
+			delete tmp;
+			delete mtmp;
+			tmp = re;
+
+		  } else {
+
+			NetESelect*stmp = new NetESelect(tmp, mtmp, 1);
+			tmp->set_line(*this);
+			tmp = stmp;
+		  }
+	    }
+
 
 	    tmp->set_line(*this);
 	    return tmp;
@@ -269,15 +553,16 @@ NetExpr* PEIdent::elaborate_expr(Design*des, NetScope*scope) const
 
 	// If the identifier names a signal (a register or wire)
 	// then create a NetESignal node to handle it.
-      if (NetNet*net = des->find_signal(scope, text_)) {
+      if (NetNet*net = des->find_signal(scope, path_)) {
 
 	      // If this is a part select of a signal, then make a new
 	      // temporary signal that is connected to just the
-	      // selected bits.
+	      // selected bits. The lsb_ and msb_ expressions are from
+	      // the foo[msb:lsb] expression in the original.
 	    if (lsb_) {
 		  assert(msb_);
-		  verinum*lsn = lsb_->eval_const(des, scope->name());
-		  verinum*msn = msb_->eval_const(des, scope->name());
+		  verinum*lsn = lsb_->eval_const(des, scope);
+		  verinum*msn = msb_->eval_const(des, scope);
 		  if ((lsn == 0) || (msn == 0)) {
 			cerr << get_line() << ": error: "
 			      "Part select expresions must be "
@@ -288,21 +573,51 @@ NetExpr* PEIdent::elaborate_expr(Design*des, NetScope*scope) const
 
 		  assert(lsn);
 		  assert(msn);
-		  unsigned long lsv = lsn->as_ulong();
-		  unsigned long msv = msn->as_ulong();
+
+		    /* The indices of part selects are signed
+		       integers, so allow negative values. However,
+		       the width that they represent is
+		       unsigned. Remember that any order is possible,
+		       i.e. [1:0], [-4,6], etc. */
+
+		  long lsv = lsn->as_long();
+		  long msv = msn->as_long();
 		  unsigned long wid = 1 + ((msv>lsv)? (msv-lsv) : (lsv-msv));
+		  if (wid > net->pin_count()) {
+			cerr << get_line() << ": error: part select ["
+			     << msv << ":" << lsv << "] out of range."
+			     << endl;
+			des->errors += 1;
+			delete lsn;
+			delete msn;
+			return 0;
+		  }
 		  assert(wid <= net->pin_count());
-		  assert(net->sb_to_idx(msv) >= net->sb_to_idx(lsv));
 
-		  string tname = des->local_symbol(scope->name());
-		  NetTmp*tsig = new NetTmp(scope, tname, wid);
+		  if (net->sb_to_idx(msv) < net->sb_to_idx(lsv)) {
+			cerr << get_line() << ": error: part select ["
+			     << msv << ":" << lsv << "] out of order."
+			     << endl;
+			des->errors += 1;
+			delete lsn;
+			delete msn;
+			return 0;
+		  }
 
-		    // Connect the pins from the lsb up to the msb.
-		  unsigned off = net->sb_to_idx(lsv);
-		  for (unsigned idx = 0 ;  idx < wid ;  idx += 1)
-			connect(tsig->pin(idx), net->pin(idx+off));
 
-		  NetESignal*tmp = new NetESignal(tsig);
+		  if (net->sb_to_idx(msv) >= net->pin_count()) {
+			cerr << get_line() << ": error: part select ["
+			     << msv << ":" << lsv << "] out of range."
+			     << endl;
+			des->errors += 1;
+			delete lsn;
+			delete msn;
+			return 0;
+		  }
+
+		  NetESignal*tmp = new NetESignal(net,
+						  net->sb_to_idx(msv),
+						  net->sb_to_idx(lsv));
 		  tmp->set_line(*this);
 
 		  return tmp;
@@ -312,23 +627,30 @@ NetExpr* PEIdent::elaborate_expr(Design*des, NetScope*scope) const
 	      // to the part select, so that I save the effort of
 	      // making a mux part in the netlist.
 	    verinum*msn;
-	    if (msb_ && (msn = msb_->eval_const(des, scope->name()))) {
+	    if (msb_ && (msn = msb_->eval_const(des, scope))) {
 		  assert(idx_ == 0);
 		  unsigned long msv = msn->as_ulong();
 		  unsigned idx = net->sb_to_idx(msv);
 
 		  if (idx >= net->pin_count()) {
-			cerr << get_line() << ": internal error: "
-			     << "bit " << msv << " out of range of net "
+			  /* The bit select is out of range of the
+			     vector. This is legal, but returns a
+			     constant 1'bx value. */
+			verinum x (verinum::Vx);
+			NetEConst*tmp = new NetEConst(x);
+			tmp->set_line(*this);
+
+			cerr << get_line() << ": warning: Bit select ["
+			     << msv << "] out of range of vector "
 			     << net->name() << "[" << net->msb()
 			     << ":" << net->lsb() << "]." << endl;
-			return 0;
+			cerr << get_line() << ":        : Replacing "
+			     << "expression with a constant 1'bx." << endl;
+			delete msn;
+			return tmp;
 		  }
 
-		  string tname = des->local_symbol(scope->name());
-		  NetTmp*tsig = new NetTmp(scope, tname);
-		  connect(tsig->pin(0), net->pin(idx));
-		  NetESignal*tmp = new NetESignal(tsig);
+		  NetESignal*tmp = new NetESignal(net, idx, idx);
 		  tmp->set_line(*this);
 
 		  return tmp;
@@ -341,7 +663,7 @@ NetExpr* PEIdent::elaborate_expr(Design*des, NetScope*scope) const
 	      // device to mux the bit in the net.
 	    if (msb_) {
 		  NetExpr*ex = msb_->elaborate_expr(des, scope);
-		  NetESubSignal*ss = new NetESubSignal(node, ex);
+		  NetEBitSel*ss = new NetEBitSel(node, ex);
 		  ss->set_line(*this);
 		  return ss;
 	    }
@@ -355,12 +677,25 @@ NetExpr* PEIdent::elaborate_expr(Design*des, NetScope*scope) const
 	// If the identifier names a memory, then this is a
 	// memory reference and I must generate a NetEMemory
 	// object to handle it.
-      if (NetMemory*mem = des->find_memory(scope, text_)) {
+      if (NetMemory*mem = des->find_memory(scope, path_)) {
 	    if (msb_ == 0) {
-		  NetEMemory*node = new NetEMemory(mem);
-		  node->set_line(*this);
-		  return node;
+
+		    // If this memory is an argument to a system task,
+		    // then it is OK for it to not have an index.
+		  if (sys_task_arg) {
+			NetEMemory*node = new NetEMemory(mem);
+			node->set_line(*this);
+			return node;
+		  }
+
+		    // If it is not a simple system task argument,
+		    // this a missing index is an error.
+		  cerr << get_line() << ": error: memory " << mem->name()
+		       << " needs an index in this context." << endl;
+		  des->errors += 1;
+		  return 0;
 	    }
+
 	    assert(msb_ != 0);
 	    if (lsb_) {
 		  cerr << get_line() << ": error: part select of a memory: "
@@ -373,7 +708,7 @@ NetExpr* PEIdent::elaborate_expr(Design*des, NetScope*scope) const
 	    assert(idx_ == 0);
 	    NetExpr*i = msb_->elaborate_expr(des, scope);
 	    if (msb_ && i == 0) {
-		  cerr << get_line() << ": error: Unable to exaborate "
+		  cerr << get_line() << ": error: Unable to elaborate "
 			"index expression `" << *msb_ << "'" << endl;
 		  des->errors += 1;
 		  return 0;
@@ -384,8 +719,20 @@ NetExpr* PEIdent::elaborate_expr(Design*des, NetScope*scope) const
 	    return node;
       }
 
-	// Finally, if this is a scope name, then return that.
-      if (NetScope*nsc = des->find_scope(text_)) {
+	// Finally, if this is a scope name, then return that. Look
+	// first to see if this is a name of a local scope. Failing
+	// that, search globally for a heirarchical name.
+      if ((path_.peek_name(1) == 0))
+	    if (NetScope*nsc = scope->child(path_.peek_name(0))) {
+		  NetEScope*tmp = new NetEScope(nsc);
+		  tmp->set_line(*this);
+		  return tmp;
+	    }
+
+	// NOTE: This search pretty much assumes that text_ is a
+	// complete hierarchical name, since there is no mention of
+	// the current scope in the call to find_scope.
+      if (NetScope*nsc = des->find_scope(path_)) {
 	    NetEScope*tmp = new NetEScope(nsc);
 	    tmp->set_line(*this);
 	    return tmp;
@@ -393,12 +740,12 @@ NetExpr* PEIdent::elaborate_expr(Design*des, NetScope*scope) const
 
 	// I cannot interpret this identifier. Error message.
       cerr << get_line() << ": error: Unable to bind wire/reg/memory "
-	    "`" << text_ << "' in `" << scope->name() << "'" << endl;
+	    "`" << path_ << "' in `" << scope->name() << "'" << endl;
       des->errors += 1;
       return 0;
 }
 
-NetEConst* PENumber::elaborate_expr(Design*des, NetScope*) const
+NetEConst* PENumber::elaborate_expr(Design*des, NetScope*, bool) const
 {
       assert(value_);
       NetEConst*tmp = new NetEConst(*value_);
@@ -406,7 +753,7 @@ NetEConst* PENumber::elaborate_expr(Design*des, NetScope*) const
       return tmp;
 }
 
-NetEConst* PEString::elaborate_expr(Design*des, NetScope*) const
+NetEConst* PEString::elaborate_expr(Design*des, NetScope*, bool) const
 {
       NetEConst*tmp = new NetEConst(value());
       tmp->set_line(*this);
@@ -418,7 +765,7 @@ NetEConst* PEString::elaborate_expr(Design*des, NetScope*) const
  * parsed so I can presume that they exist, and call elaboration
  * methods. If any elaboration fails, then give up and return 0.
  */
-NetETernary*PETernary::elaborate_expr(Design*des, NetScope*scope) const
+NetETernary*PETernary::elaborate_expr(Design*des, NetScope*scope, bool) const
 {
       assert(expr_);
       assert(tru_);
@@ -445,7 +792,7 @@ NetETernary*PETernary::elaborate_expr(Design*des, NetScope*scope) const
       return res;
 }
 
-NetEUnary* PEUnary::elaborate_expr(Design*des, NetScope*scope) const
+NetExpr* PEUnary::elaborate_expr(Design*des, NetScope*scope, bool) const
 {
       NetExpr*ip = expr_->elaborate_expr(des, scope);
       if (ip == 0) return 0;
@@ -454,106 +801,148 @@ NetEUnary* PEUnary::elaborate_expr(Design*des, NetScope*scope) const
        * just like in PEBinary::elaborate_expr() ?
        */
 
-      NetEUnary*tmp;
+      NetExpr*tmp;
       switch (op_) {
 	  default:
 	    tmp = new NetEUnary(op_, ip);
 	    tmp->set_line(*this);
 	    break;
+
+	  case '-':
+	    if (NetEConst*ipc = dynamic_cast<NetEConst*>(ip)) {
+		  verinum val = ipc->value();
+		  verinum zero (verinum::V0, val.len(), val.has_len());
+		  val = zero - val;
+		  val.has_sign(ipc->has_sign());
+		  tmp = new NetEConst(val);
+		  delete ip;
+	    } else {
+		  tmp = new NetEUnary(op_, ip);
+		  tmp->set_line(*this);
+	    }
+	    break;
+
+	  case '+':
+	    tmp = ip;
+	    break;
+
+	  case '!': // Logical NOT
+	      /* If the operand to unary ! is a constant, then I can
+		 evaluate this expression here and return a logical
+		 constant in its place. */
+	    if (NetEConst*ipc = dynamic_cast<NetEConst*>(ip)) {
+		  verinum val = ipc->value();
+		  unsigned v1 = 0;
+		  unsigned vx = 0;
+		  for (unsigned idx = 0 ;  idx < val.len() ;  idx += 1)
+			switch (val[idx]) {
+			    case verinum::V0:
+			      break;
+			    case verinum::V1:
+			      v1 += 1;
+			      break;
+			    default:
+			      vx += 1;
+			      break;
+			}
+
+		  verinum::V res;
+		  if (v1 > 0)
+			res = verinum::V0;
+		  else if (vx > 0)
+			res = verinum::Vx;
+		  else
+			res = verinum::V1;
+
+		  verinum vres (res, 1, true);
+		  tmp = new NetEConst(vres);
+		  tmp->set_line(*this);
+		  delete ip;
+	    } else {
+		  tmp = new NetEUReduce(op_, ip);
+		  tmp->set_line(*this);
+	    }
+	    break;
+
+	  case '&': // Reduction AND
+	  case '|': // Reduction OR
+	  case '^': // Reduction XOR
+	  case 'A': // Reduction NAND (~&)
+	  case 'N': // Reduction NOR (~|)
+	  case 'X': // Reduction NXOR (~^)
+	    tmp = new NetEUReduce(op_, ip);
+	    tmp->set_line(*this);
+	    break;
+
 	  case '~':
 	    tmp = new NetEUBits(op_, ip);
 	    tmp->set_line(*this);
 	    break;
       }
+
       return tmp;
 }
 
 /*
  * $Log: elab_expr.cc,v $
- * Revision 1.26  2000/05/19 01:55:09  steve
- *  Catch part select of memories as an error.
+ * Revision 1.66  2002/09/21 21:28:18  steve
+ *  Allow constant bit selects out of range.
  *
- * Revision 1.25  2000/05/07 18:20:07  steve
- *  Import MCD support from Stephen Tell, and add
- *  system function parameter support to the IVL core.
+ * Revision 1.65  2002/09/18 04:08:45  steve
+ *  Spelling errors.
  *
- * Revision 1.24  2000/05/04 03:37:58  steve
- *  Add infrastructure for system functions, move
- *  $time to that structure and add $random.
+ * Revision 1.64  2002/09/12 15:49:43  steve
+ *  Add support for binary nand operator.
  *
- * Revision 1.23  2000/05/02 03:13:30  steve
- *  Move memories to the NetScope object.
+ * Revision 1.63  2002/08/19 02:39:16  steve
+ *  Support parameters with defined ranges.
  *
- * Revision 1.22  2000/05/02 00:58:11  steve
- *  Move signal tables to the NetScope class.
+ * Revision 1.62  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
  *
- * Revision 1.21  2000/04/28 18:43:23  steve
- *  integer division in expressions properly get width.
+ * Revision 1.61  2002/06/14 21:38:41  steve
+ *  Fix expression width for repeat concatenations.
  *
- * Revision 1.20  2000/03/29 04:06:28  steve
- *  Forgot to return elaborate result (Dan Nelsen)
+ * Revision 1.60  2002/05/24 00:44:54  steve
+ *  Add support for $bits (SystemVerilog)
  *
- * Revision 1.19  2000/03/20 16:57:22  steve
- *  select correct bit when reg has non-zero lsb.
+ * Revision 1.59  2002/05/06 02:30:27  steve
+ *  Allow parameters in concatenation of widths are defined.
  *
- * Revision 1.18  2000/03/12 18:22:11  steve
- *  Binary and unary operators in parameter expressions.
+ * Revision 1.58  2002/05/05 21:11:49  steve
+ *  Put off evaluation of concatenation repeat expresions
+ *  until after parameters are defined. This allows parms
+ *  to be used in repeat expresions.
  *
- * Revision 1.17  2000/03/08 04:36:53  steve
- *  Redesign the implementation of scopes and parameters.
- *  I now generate the scopes and notice the parameters
- *  in a separate pass over the pform. Once the scopes
- *  are generated, I can process overrides and evalutate
- *  paremeters before elaboration begins.
+ *  Add the builtin $signed system function.
  *
- * Revision 1.16  2000/02/23 02:56:54  steve
- *  Macintosh compilers do not support ident.
+ * Revision 1.57  2002/04/27 05:03:46  steve
+ *  Preserve stringiness string part select and concatenation.
  *
- * Revision 1.15  2000/01/13 03:35:35  steve
- *  Multiplication all the way to simulation.
+ * Revision 1.56  2002/04/27 02:38:04  steve
+ *  Support selecting bits from parameters.
  *
- * Revision 1.14  2000/01/01 06:18:00  steve
- *  Handle synthesis of concatenation.
+ * Revision 1.55  2002/04/25 05:04:31  steve
+ *  Evaluate constant bit select of constants.
  *
- * Revision 1.13  1999/12/12 06:03:14  steve
- *  Allow memories without indices in expressions.
+ * Revision 1.54  2002/04/14 21:16:48  steve
+ *  Evaluate logical not at elaboration time.
  *
- * Revision 1.12  1999/11/30 04:54:01  steve
- *  Match scope names as last resort.
+ * Revision 1.53  2002/04/14 03:55:25  steve
+ *  Precalculate unary - if possible.
  *
- * Revision 1.11  1999/11/28 23:42:02  steve
- *  NetESignal object no longer need to be NetNode
- *  objects. Let them keep a pointer to NetNet objects.
+ * Revision 1.52  2002/04/13 02:33:17  steve
+ *  Detect missing indices to memories (PR#421)
  *
- * Revision 1.10  1999/11/27 19:07:57  steve
- *  Support the creation of scopes.
+ * Revision 1.51  2002/03/09 02:10:22  steve
+ *  Add the NetUserFunc netlist node.
  *
- * Revision 1.9  1999/11/21 17:35:37  steve
- *  Memory name lookup handles scopes.
- *
- * Revision 1.8  1999/11/10 02:52:24  steve
- *  Create the vpiMemory handle type.
- *
- * Revision 1.7  1999/10/18 00:02:21  steve
- *  Catch unindexed memory reference.
- *
- * Revision 1.6  1999/09/30 02:43:02  steve
- *  Elaborate ~^ and ~| operators.
- *
- * Revision 1.5  1999/09/30 00:48:49  steve
- *  Cope with errors during ternary operator elaboration.
- *
- * Revision 1.4  1999/09/29 22:57:10  steve
- *  Move code to elab_expr.cc
- *
- * Revision 1.3  1999/09/25 02:57:30  steve
- *  Parse system function calls.
- *
- * Revision 1.2  1999/09/21 00:13:40  steve
- *  Support parameters that reference other paramters.
- *
- * Revision 1.1  1999/09/20 02:21:10  steve
- *  Elaborate parameters in phases.
+ * Revision 1.50  2002/01/28 00:52:41  steve
+ *  Add support for bit select of parameters.
+ *  This leads to a NetESelect node and the
+ *  vvp code generator to support that.
  *
+ * Revision 1.49  2002/01/11 05:25:45  steve
+ *  The stime system function is 32bits.
  */
 

elab_lval.cc

@@ -0,0 +1,412 @@
+/*
+ * Copyright (c) 2000 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: elab_lval.cc,v 1.23 2002/11/21 23:27:51 steve Exp $"
+#endif
+
+# include "config.h"
+
+# include  "PExpr.h"
+# include  "netlist.h"
+
+# include  <iostream>
+
+/*
+ * These methods generate a NetAssign_ object for the l-value of the
+ * assignemnt. This is common code for the = and <= statements.
+ *
+ * What gets generated depends on the structure of the l-value. If the
+ * l-value is a simple name (i.e. foo <= <value>) the the NetAssign_
+ * is created the width of the foo reg and connected to all the
+ * bits.
+ *
+ * If there is a part select (i.e. foo[3:1] <= <value>) the NetAssign_
+ * is made only as wide as it needs to be (3 bits in this example) and
+ * connected to the correct bits of foo. A constant bit select is a
+ * special case of the part select. 
+ *
+ * If the bit-select is non-constant (i.e. foo[<expr>] = <value>) the
+ * NetAssign_ is made wide enough to connect to all the bits of foo,
+ * then the mux expression is elaborated and attached to the
+ * NetAssign_ node as a b_mux value. The target must interpret the
+ * presense of a bmux value as taking a single bit and assigning it to
+ * the bit selected by the bmux expression.
+ *
+ * If the l-value expression is non-trivial, but can be fully
+ * evaluated at compile time (meaning any bit selects are constant)
+ * then elaboration will make a single NetAssign_ that connects to a
+ * synthetic reg that in turn connects to all the proper pins of the
+ * l-value.
+ *
+ * This last case can turn up in statements like: {a, b[1]} = c;
+ * rather then create a NetAssign_ for each item in the contatenation,
+ * elaboration makes a single NetAssign_ and connects it up properly.
+ */
+
+
+/*
+ * The default interpretation of an l-value to a procedural assignment
+ * is to try to make a net elaboration, and see if the result is
+ * suitable for assignment.
+ */
+NetAssign_* PExpr::elaborate_lval(Design*des, NetScope*scope) const
+{
+      NetNet*ll = 0;
+      if (ll == 0) {
+	    cerr << get_line() << ": Assignment l-value too complex."
+		 << endl;
+	    return 0;
+      }
+
+      NetAssign_*lv = new NetAssign_(ll);
+      return lv;
+}
+
+/*
+ * Concatenation expressions can appear as l-values. Handle them here.
+ *
+ * If adjacent l-values in the concatenation are not bit selects, then
+ * merge them into a single NetAssign_ object. This can happen is code
+ * like ``{ ...a, b, ...}''. As long as "a" and "b" do not have bit
+ * selects (or the bit selects are constant) we can merge the
+ * NetAssign_ objects.
+ *
+ * Be careful to get the bit order right. In the expression ``{a, b}''
+ * a is the MSB and b the LSB. Connect the LSB to the low pins of the
+ * NetAssign_ object.
+ */
+NetAssign_* PEConcat::elaborate_lval(Design*des, NetScope*scope) const
+{
+      if (repeat_) {
+	    cerr << get_line() << ": error: Repeat concatenations make "
+		  "no sense in l-value expressions. I refuse." << endl;
+	    des->errors += 1;
+	    return 0;
+      }
+
+      NetAssign_*res = 0;
+
+      for (unsigned idx = 0 ;  idx < parms_.count() ;  idx += 1) {
+	    NetAssign_*tmp = parms_[idx]->elaborate_lval(des, scope);
+
+	      /* If the l-value doesn't elaborate, the error was
+		 already detected and printed. We just skip it and let
+		 the compiler catch more errors. */
+	    if (tmp == 0)
+		  continue;
+
+	    assert(tmp);
+
+
+	      /* Link the new l-value to the previous one. */
+
+	    NetAssign_*last = tmp;
+	    while (last->more)
+		  last = last->more;
+
+	    last->more = res;
+	    res = tmp;
+      }
+
+      return res;
+}
+
+/*
+ * Handle the ident as an l-value. This includes bit and part selects
+ * of that ident.
+ */
+NetAssign_* PEIdent::elaborate_lval(Design*des, NetScope*scope) const
+{
+	/* Get the signal referenced by the identifier, and make sure
+	   it is a register. (Wires are not allows in this context. */
+      NetNet*reg = des->find_signal(scope, path_);
+
+      if (reg == 0) {
+	    NetMemory*mem = des->find_memory(scope, path_);
+	    if (mem != 0)
+		  return elaborate_mem_lval_(des, scope, mem);
+
+	    cerr << get_line() << ": error: Could not find variable ``"
+		 << path_ << "'' in ``" << scope->name() <<
+		  "''" << endl;
+
+	    des->errors += 1;
+	    return 0;
+      }
+      assert(reg);
+
+      if (reg->type() != NetNet::REG) {
+	    cerr << get_line() << ": error: " << path_ <<
+		  " is not a reg/integer/time in " << scope->name() <<
+		  "." << endl;
+	    des->errors += 1;
+	    return 0;
+      }
+
+      long msb, lsb;
+      NetExpr*mux;
+
+      if (msb_ && lsb_) {
+	      /* This handles part selects. In this case, there are
+		 two bit select expressions, and both must be
+		 constant. Evaluate them and pass the results back to
+		 the caller. */
+	    verinum*vl = lsb_->eval_const(des, scope);
+	    if (vl == 0) {
+		  cerr << lsb_->get_line() << ": error: "
+			"Part select expressions must be constant."
+		       << endl;
+		  cerr << lsb_->get_line() << ":      : This lsb expression "
+			"violates the rule: " << *lsb_ << endl;
+		  des->errors += 1;
+		  return 0;
+	    }
+	    verinum*vm = msb_->eval_const(des, scope);
+	    if (vm == 0) {
+		  cerr << msb_->get_line() << ": error: "
+			"Part select expressions must be constant."
+		       << endl;
+		  cerr << msb_->get_line() << ":      : This msb expression "
+			"violates the rule: " << *msb_ << endl;
+		  des->errors += 1;
+		  return 0;
+	    }
+
+	    msb = vm->as_long();
+	    lsb = vl->as_long();
+	    mux = 0;
+
+      } else if (msb_) {
+
+	      /* If there is only a single select expression, it is a
+		 bit select. Evaluate the constant value and treat it
+		 as a part select with a bit width of 1. If the
+		 expression it not constant, then return the
+		 expression as a mux. */
+	    assert(lsb_ == 0);
+	    verinum*v = msb_->eval_const(des, scope);
+	    if (v == 0) {
+		  NetExpr*m = msb_->elaborate_expr(des, scope);
+		  assert(m);
+		  msb = 0;
+		  lsb = 0;
+		  mux = m;
+
+	    } else {
+
+		  msb = v->as_long();
+		  lsb = v->as_long();
+		  mux = 0;
+	    }
+
+      } else {
+
+	      /* No select expressions, so presume a part select the
+		 width of the register. */
+
+	    assert(msb_ == 0);
+	    assert(lsb_ == 0);
+	    msb = reg->msb();
+	    lsb = reg->lsb();
+	    mux = 0;
+      }
+
+
+      NetAssign_*lv;
+      if (mux) {
+
+	      /* If there is a non-constant bit select, make a
+		 NetAssign_ to the target reg and attach a
+		 bmux to select the target bit. */
+	    lv = new NetAssign_(reg);
+
+	    lv->set_bmux(mux);
+
+      } else {
+
+	      /* If the bit/part select is constant, then make the
+		 NetAssign_ only as wide as it needs to be and connect
+		 only to the selected bits of the reg. */
+	    unsigned loff = reg->sb_to_idx(lsb);
+	    unsigned moff = reg->sb_to_idx(msb);
+	    unsigned wid = moff - loff + 1;
+
+	    if (moff < loff) {
+		  cerr << get_line() << ": error: part select "
+		       << reg->name() << "[" << msb<<":"<<lsb<<"]"
+		       << " is reversed." << endl;
+		  des->errors += 1;
+		  return 0;
+	    }
+
+	      /* If the part select extends beyond the extreme of the
+		 variable, then report an error. Note that loff is
+		 converted to normalized form so is relative the
+		 variable pins. */
+
+	    if ((wid + loff) > reg->pin_count()) {
+		  cerr << get_line() << ": error: bit/part select "
+		       << reg->name() << "[" << msb<<":"<<lsb<<"]"
+		       << " is out of range." << endl;
+		  des->errors += 1;
+		  return 0;
+	    }
+
+	    lv = new NetAssign_(reg);
+	    lv->set_part(loff, wid);
+
+	    assert(moff < reg->pin_count());
+      }
+
+
+      return lv;
+}
+
+NetAssign_* PEIdent::elaborate_mem_lval_(Design*des, NetScope*scope,
+					NetMemory*mem) const
+{
+      if (msb_ == 0) {
+	    cerr << get_line() << ": error: Assign to memory \""
+		 << mem->name() << "\" requires a word select index."
+		 << endl;
+	    des->errors += 1;
+	    return 0;
+      }
+
+      if (msb_ && lsb_) {
+	    cerr << get_line() << ": error: Cannot use part select on "
+		 << "memory \"" << mem->name() << ".\"" << endl;
+	    des->errors += 1;
+	    return 0;
+      }
+
+      assert(msb_ && !lsb_);
+
+      NetExpr*ix = msb_->elaborate_expr(des, scope);
+      if (ix == 0)
+	    return 0;
+
+	/* Evaluate the memory index expression down as must as
+	   possible. Ideally, we can get it down to a constant. */
+      if (! dynamic_cast<NetEConst*>(ix)) {
+	    NetExpr*tmp = ix->eval_tree();
+	    if (tmp) {
+		  tmp->set_line(*ix);
+		  delete ix;
+		  ix = tmp;
+	    }
+      }
+
+      NetAssign_*lv = new NetAssign_(mem);
+      lv->set_bmux(ix);
+      lv->set_part(0, mem->width());
+      return lv;
+}
+
+NetAssign_* PENumber::elaborate_lval(Design*des, NetScope*) const
+{
+      cerr << get_line() << ": error: Constant values not allowed "
+	   << "in l-value expressions." << endl;
+      des->errors += 1;
+      return 0;
+}
+
+/*
+ * $Log: elab_lval.cc,v $
+ * Revision 1.23  2002/11/21 23:27:51  steve
+ *  Precalculate indices to l-value arrays.
+ *
+ * Revision 1.22  2002/11/21 18:15:40  steve
+ *  Fix const test of msb in assignment l-values.
+ *
+ * Revision 1.21  2002/11/02 01:10:49  steve
+ *  Detect memories without work index in l-value.
+ *
+ * Revision 1.20  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.19  2002/06/04 05:38:44  steve
+ *  Add support for memory words in l-value of
+ *  blocking assignments, and remove the special
+ *  NetAssignMem class.
+ *
+ * Revision 1.18  2002/03/09 04:02:26  steve
+ *  Constant expressions are not l-values for task ports.
+ *
+ * Revision 1.17  2001/12/03 04:47:14  steve
+ *  Parser and pform use hierarchical names as hname_t
+ *  objects instead of encoded strings.
+ *
+ * Revision 1.16  2001/11/08 05:15:50  steve
+ *  Remove string paths from PExpr elaboration.
+ *
+ * Revision 1.15  2001/11/07 04:01:59  steve
+ *  eval_const uses scope instead of a string path.
+ *
+ * Revision 1.14  2001/08/25 23:50:02  steve
+ *  Change the NetAssign_ class to refer to the signal
+ *  instead of link into the netlist. This is faster
+ *  and uses less space. Make the NetAssignNB carry
+ *  the delays instead of the NetAssign_ lval objects.
+ *
+ *  Change the vvp code generator to support multiple
+ *  l-values, i.e. concatenations of part selects.
+ *
+ * Revision 1.13  2001/07/25 03:10:48  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
+ * Revision 1.12  2001/02/09 03:16:48  steve
+ *  Report bit/part select out of range errors. (PR#133)
+ *
+ * Revision 1.11  2001/01/10 03:13:23  steve
+ *  Build task outputs as lval instead of nets. (PR#98)
+ *
+ * Revision 1.10  2001/01/06 06:31:58  steve
+ *  declaration initialization for time variables.
+ *
+ * Revision 1.9  2001/01/06 02:29:36  steve
+ *  Support arrays of integers.
+ *
+ * Revision 1.8  2000/12/12 06:14:51  steve
+ *  sorry for concatenated memories in l-values. (PR#76)
+ *
+ * Revision 1.7  2000/12/01 02:55:37  steve
+ *  Detect part select errors on l-values.
+ *
+ * Revision 1.6  2000/10/31 17:49:02  steve
+ *  Support time variables.
+ *
+ * Revision 1.5  2000/10/26 17:09:46  steve
+ *  Fix handling of errors in behavioral lvalues. (PR#28)
+ *
+ * Revision 1.4  2000/09/10 15:43:59  steve
+ *  Some error checking.
+ *
+ * Revision 1.3  2000/09/10 03:59:59  steve
+ *  Agressively merge NetAssign_ within concatenations.
+ *
+ * Revision 1.2  2000/09/10 02:18:16  steve
+ *  elaborate complex l-values
+ *
+ * Revision 1.1  2000/09/09 15:21:26  steve
+ *  move lval elaboration to PExpr virtual methods.
+ *
+ */
+

elab_pexpr.cc

@@ -16,11 +16,16 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: elab_pexpr.cc,v 1.5 2000/06/13 05:22:16 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: elab_pexpr.cc,v 1.18 2002/12/05 02:14:33 steve Exp $"
 #endif
 
+# include "config.h"
+
 # include  "PExpr.h"
+# include  "util.h"
+
+# include  <iostream>
 
 NetExpr*PExpr::elaborate_pexpr(Design*des, NetScope*sc) const
 {
@@ -61,28 +66,21 @@ NetExpr*PEBinary::elaborate_pexpr (Design*des, NetScope*scope) const
  */
 NetEConcat* PEConcat::elaborate_pexpr(Design*des, NetScope*scope) const
 {
-      unsigned repeat = 1;
+      NetExpr* repeat = 0;
 
 	/* If there is a repeat expression, then evaluate the constant
-	   value and set the repeat count.
-
-	   XXXX Potential bug XXX In principle, the repeat expression
-	   can have a parameter name in it. Since where are in the
-	   working of parameters now, we will not be able to
-	   accurately evaluate such expressions. So eventually, I will
-	   need to be able to defer the evaluation of the expression. */
+	   value and set the repeat count.  */
       if (repeat_) {
-	    verinum*vrep = repeat_->eval_const(des, scope->name());
-	    if (vrep == 0) {
+	    repeat = repeat_->elaborate_pexpr(des, scope);
+	    if (repeat == 0) {
 		  cerr << get_line() << ": error: "
 			"concatenation repeat expression cannot be evaluated."
 		       << endl;
 		  des->errors += 1;
-		  return 0;
 	    }
 
-	    repeat = vrep->as_ulong();
-	    delete vrep;
+	      /* continue on even if the repeat expression doesn't
+		 work, as we can find more errors. */
       }
 
 	/* Make the empty concat expression. */
@@ -96,13 +94,33 @@ NetEConcat* PEConcat::elaborate_pexpr(Design*des, NetScope*scope) const
 	    assert(parms_[idx]);
 	    NetExpr*ex = parms_[idx]->elaborate_pexpr(des, scope);
 	    if (ex == 0) continue;
+
 	    ex->set_line(*parms_[idx]);
+
+	    if (dynamic_cast<NetEParam*>(ex)) {
+
+		    /* If this parameter is a NetEParam, then put off
+		       the width check for later. */
+
+	    } else if (! ex->has_width()) {
+		  cerr << ex->get_line() << ": error: operand of "
+		       << "concatenation has indefinite width: "
+		       << *ex << endl;
+		  des->errors += 1;
+
+	    }
+
 	    tmp->set(idx, ex);
       }
 
       return tmp;
 }
 
+NetExpr*PEFNumber::elaborate_pexpr(Design*des, NetScope*scope) const
+{
+      return elaborate_expr(des, scope);
+}
+
 /*
  * Parameter expressions may reference other parameters, but only in
  * the current scope. Preserve the parameter reference in the
@@ -111,16 +129,42 @@ NetEConcat* PEConcat::elaborate_pexpr(Design*des, NetScope*scope) const
  */
 NetExpr*PEIdent::elaborate_pexpr(Design*des, NetScope*scope) const
 {
-      const NetExpr*ex = scope->get_parameter(text_);
+      hname_t path = path_;
+      char*name = path.remove_tail_name();
+
+      NetScope*pscope = scope;
+      if (path.peek_name(0))
+	    pscope = des->find_scope(scope, path);
+
+      const NetExpr*ex = pscope->get_parameter(name);
       if (ex == 0) {
-	    cerr << get_line() << ": error: identifier ``" << text_ <<
+	    cerr << get_line() << ": error: identifier ``" << path_ <<
 		  "'' is not a parameter in " << scope->name() << "." << endl;
 	    des->errors += 1;
+	    delete name;
 	    return 0;
       }
 
-      NetExpr*res = new NetEParam(des, scope, text_);
+      NetExpr*res = new NetEParam(des, pscope, hname_t(name));
       assert(res);
+      delete name;
+
+      assert(idx_ == 0);
+      if (msb_ && lsb_) {
+	    cerr << get_line() << ": sorry: Cannot part select "
+		  "bits of parameters." << endl;
+	    des->errors += 1;
+
+      } else if (msb_) {
+
+	      /* We have here a bit select. Insert a NetESelect node
+		 to handle it. */
+	    NetExpr*tmp = msb_->elaborate_pexpr(des, scope);
+	    if (tmp != 0) {
+		  res = new NetESelect(res, tmp, 1);
+	    }
+      }
+
       return res;
 }
 
@@ -138,6 +182,17 @@ NetEConst* PEString::elaborate_pexpr(Design*des, NetScope*scope) const
       return elaborate_expr(des, scope);
 }
 
+NetETernary* PETernary::elaborate_pexpr(Design*des, NetScope*scope) const
+{
+      NetExpr*c = expr_->elaborate_pexpr(des, scope);
+      NetExpr*t = tru_->elaborate_pexpr(des, scope);
+      NetExpr*f = fal_->elaborate_pexpr(des, scope);
+      if (c == 0) return 0;
+      if (t == 0) return 0;
+      if (f == 0) return 0;
+      return new NetETernary(c, t, f);
+}
+
 NetExpr*PEUnary::elaborate_pexpr (Design*des, NetScope*scope) const
 {
       NetExpr*ip = expr_->elaborate_pexpr(des, scope);
@@ -157,12 +212,72 @@ NetExpr*PEUnary::elaborate_pexpr (Design*des, NetScope*scope) const
 	    tmp = new NetEUBits(op_, ip);
 	    tmp->set_line(*this);
 	    break;
+	  case '!': // Logical NOT
+	  case '&': // Reduction AND
+	  case '|': // Reduction OR
+	  case '^': // Reduction XOR
+	  case 'A': // Reduction NAND (~&)
+	  case 'N': // Reduction NOR (~|)
+	  case 'X': // Reduction NXOR (~^)
+	    tmp = new NetEUReduce(op_, ip);
+	    tmp->set_line(*this);
+	    break;
       }
       return tmp;
 }
 
 /*
  * $Log: elab_pexpr.cc,v $
+ * Revision 1.18  2002/12/05 02:14:33  steve
+ *  Support bit select in constant expressions.
+ *
+ * Revision 1.17  2002/11/09 01:40:19  steve
+ *  Postpone parameter width check to evaluation.
+ *
+ * Revision 1.16  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.15  2002/05/06 02:30:27  steve
+ *  Allow parameters in concatenation of widths are defined.
+ *
+ * Revision 1.14  2002/05/05 21:11:50  steve
+ *  Put off evaluation of concatenation repeat expresions
+ *  until after parameters are defined. This allows parms
+ *  to be used in repeat expresions.
+ *
+ *  Add the builtin $signed system function.
+ *
+ * Revision 1.13  2002/01/28 00:52:41  steve
+ *  Add support for bit select of parameters.
+ *  This leads to a NetESelect node and the
+ *  vvp code generator to support that.
+ *
+ * Revision 1.12  2001/12/03 04:47:14  steve
+ *  Parser and pform use hierarchical names as hname_t
+ *  objects instead of encoded strings.
+ *
+ * Revision 1.11  2001/11/07 04:01:59  steve
+ *  eval_const uses scope instead of a string path.
+ *
+ * Revision 1.10  2001/10/07 03:38:08  steve
+ *  parameter names do not have defined size.
+ *
+ * Revision 1.9  2001/07/25 03:10:49  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
+ * Revision 1.8  2001/01/14 23:04:56  steve
+ *  Generalize the evaluation of floating point delays, and
+ *  get it working with delay assignment statements.
+ *
+ *  Allow parameters to be referenced by hierarchical name.
+ *
+ * Revision 1.7  2001/01/02 04:21:13  steve
+ *  Support a bunch of unary operators in parameter expressions.
+ *
+ * Revision 1.6  2000/12/16 19:03:30  steve
+ *  Evaluate <= and ?: in parameter expressions (PR#81)
+ *
  * Revision 1.5  2000/06/13 05:22:16  steve
  *  Support concatenation in parameter expressions.
  *

elab_scope.cc

@@ -16,10 +16,14 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: elab_scope.cc,v 1.4 2000/04/09 17:44:30 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: elab_scope.cc,v 1.17 2002/10/19 22:59:49 steve Exp $"
 #endif
 
+# include "config.h"
+
+# include  <iostream>
+
 /*
  * Elaboration happens in two passes, generally. The first scans the
  * pform to generate the NetScope tree and attach it to the Design
@@ -32,6 +36,7 @@
 # include  "PExpr.h"
 # include  "PGate.h"
 # include  "PTask.h"
+# include  "PWire.h"
 # include  "Statement.h"
 # include  "netlist.h"
 # include  <typeinfo>
@@ -49,7 +54,8 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
 	// the pform and just place a NetEParam placeholder in the
 	// place of the elaborated expression.
 
-      typedef map<string,PExpr*>::const_iterator mparm_it_t;
+      typedef map<string,param_expr_t>::const_iterator mparm_it_t;
+      typedef map<hname_t,PExpr*>::const_iterator hparm_it_t;
 
 
 	// This loop scans the parameters in the module, and creates
@@ -58,13 +64,21 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
       for (mparm_it_t cur = parameters.begin()
 		 ; cur != parameters.end() ;  cur ++) {
 
-	    scope->set_parameter((*cur).first, new NetEParam);
+	    NetEParam*tmp = new NetEParam;
+	    if ((*cur).second.msb)
+		  tmp->cast_signed( (*cur).second.signed_flag );
+
+	    scope->set_parameter((*cur).first, tmp, 0, 0, false);
       }
 
       for (mparm_it_t cur = localparams.begin()
 		 ; cur != localparams.end() ;  cur ++) {
 
-	    scope->set_parameter((*cur).first, new NetEParam);
+	    NetEParam*tmp = new NetEParam;
+	    if ((*cur).second.msb)
+		  tmp->cast_signed( (*cur).second.signed_flag );
+
+	    scope->set_parameter((*cur).first, tmp, 0, 0, false);
       }
 
 
@@ -76,11 +90,29 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
       for (mparm_it_t cur = parameters.begin()
 		 ; cur != parameters.end() ;  cur ++) {
 
-	    PExpr*ex = (*cur).second;
+	    PExpr*ex = (*cur).second.expr;
 	    assert(ex);
 
 	    NetExpr*val = ex->elaborate_pexpr(des, scope);
-	    val = scope->set_parameter((*cur).first, val);
+	    NetExpr*msb = 0;
+	    NetExpr*lsb = 0;
+	    bool signed_flag = false;
+
+	      /* If the parameter declaration includes msb and lsb,
+		 then use them to calculate a width for the
+		 result. Then make sure the constant expression of the
+		 parameter value is coerced to have the correct
+		 and defined width. */
+	    if ((*cur).second.msb) {
+		  msb = (*cur).second.msb ->elaborate_pexpr(des, scope);
+		  assert(msb);
+		  lsb = (*cur).second.lsb ->elaborate_pexpr(des, scope);
+		  signed_flag = (*cur).second.signed_flag;
+	    }
+
+	    val->cast_signed(signed_flag);
+	    val = scope->set_parameter((*cur).first, val,
+				       msb, lsb, signed_flag);
 	    assert(val);
 	    delete val;
       }
@@ -88,11 +120,11 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
       for (mparm_it_t cur = localparams.begin()
 		 ; cur != localparams.end() ;  cur ++) {
 
-	    PExpr*ex = (*cur).second;
+	    PExpr*ex = (*cur).second.expr;
 	    assert(ex);
 
 	    NetExpr*val = ex->elaborate_pexpr(des, scope);
-	    val = scope->set_parameter((*cur).first, val);
+	    val = scope->set_parameter((*cur).first, val, 0, 0, false);
 	    assert(val);
 	    delete val;
       }
@@ -107,7 +139,7 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
 	// here becuase the parameter receiving the assignment may be
 	// in a scope not discovered by this pass.
 
-      for (mparm_it_t cur = defparms.begin()
+      for (hparm_it_t cur = defparms.begin()
 		 ; cur != defparms.end() ;  cur ++ ) {
 
 	    PExpr*ex = (*cur).second;
@@ -129,7 +161,7 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
       for (tasks_it_t cur = tasks_.begin()
 		 ; cur != tasks_.end() ;  cur ++ ) {
 
-	    NetScope*task_scope = new NetScope(scope, (*cur).first,
+	    NetScope*task_scope = new NetScope(scope, (*cur).first.c_str(),
 					       NetScope::TASK);
 	    (*cur).second->elaborate_scope(des, task_scope);
       }
@@ -144,7 +176,7 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
       for (funcs_it_t cur = funcs_.begin()
 		 ; cur != funcs_.end() ;  cur ++ ) {
 
-	    NetScope*func_scope = new NetScope(scope, (*cur).first,
+	    NetScope*func_scope = new NetScope(scope, (*cur).first.c_str(),
 					       NetScope::FUNC);
 	    (*cur).second->elaborate_scope(des, func_scope);
       }
@@ -190,16 +222,21 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
 
 void PGModule::elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const
 {
+      if (get_name() == "") {
+	    cerr << get_line() << ": error: Instantiation of module "
+		 << mod->mod_name() << " requires an instance name." << endl;
+	    des->errors += 1;
+	    return;
+      }
+
 	// Missing module instance names have already been rejected.
       assert(get_name() != "");
 
-      string path = sc->name();
-
 	// Check for duplicate scopes. Simply look up the scope I'm
 	// about to create, and if I find it then somebody beat me to
 	// it.
 
-      if (NetScope*tmp = des->find_scope(path + "." + get_name())) {
+      if (NetScope*tmp = sc->child(get_name())) {
 	    cerr << get_line() << ": error: Instance/Scope name " <<
 		  get_name() << " already used in this context." <<
 		  endl;
@@ -207,9 +244,36 @@ void PGModule::elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const
 	    return;
       }
 
-	// Create the new scope as a MODULE with my name.
-      NetScope*my_scope = new NetScope(sc, get_name(), NetScope::MODULE);
+	// check for recursive instantiation by scanning the current
+	// scope and its parents. Look for a module instantiation of
+	// the same module, but farther up in the scope.
 
+      for (NetScope*scn = sc ;  scn ;  scn = scn->parent()) {
+	    if (scn->type() != NetScope::MODULE)
+		  continue;
+
+	    if (strcmp(mod->mod_name(), scn->module_name()) != 0)
+		  continue;
+
+	    cerr << get_line() << ": error: You cannot instantiate "
+		 << "module " << mod->mod_name() << " within itself." << endl;
+
+	    cerr << get_line() << ":      : The offending instance is "
+		 << sc->name() << "." << get_name() << " within "
+		 << scn->name() << "." << endl;
+
+	    des->errors += 1;
+	    return;
+      }
+
+	// Create the new scope as a MODULE with my name.
+      NetScope*my_scope = new NetScope(sc, get_name().c_str(), NetScope::MODULE);
+      my_scope->set_module_name(mod->mod_name());
+
+	// Set time units and precision.
+      my_scope->time_unit(mod->time_unit);
+      my_scope->time_precision(mod->time_precision);
+      des->set_precision(mod->time_precision);
 
 	// This call actually arranges for the description of the
 	// module type to process this instance and handle parameters
@@ -218,8 +282,10 @@ void PGModule::elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const
 	// later.)
       mod->elaborate_scope(des, my_scope);
 
-	// Look for module parameter replacements. This map receives
-	// those replacements.
+	// Look for module parameter replacements. The "replace" map
+	// maps parameter name to replacement expression that is
+	// passed. It is built up by the ordered overrices or named
+	// overrides.
 
       typedef map<string,PExpr*>::const_iterator mparm_it_t;
       map<string,PExpr*> replace;
@@ -233,12 +299,18 @@ void PGModule::elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const
       if (overrides_) {
 	    assert(parms_ == 0);
 	    list<string>::const_iterator cur = mod->param_names.begin();
-	    for (unsigned idx = 0
-		       ;  idx < overrides_->count()
-		       ; idx += 1, cur++) {
-		  replace[*cur] = (*overrides_)[idx];
-	    }
+	    unsigned idx = 0;
+	    for (;;) {
+		  if (idx >= overrides_->count())
+			break;
+		  if (cur == mod->param_names.end())
+			break;
 
+		  replace[*cur] = (*overrides_)[idx];
+
+		  idx += 1;
+		  cur ++;
+	    }
       }
 
 	// Named parameter overrides carry a name with each override
@@ -260,16 +332,21 @@ void PGModule::elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const
 
 	    PExpr*tmp = (*cur).second;
 	    NetExpr*val = tmp->elaborate_pexpr(des, sc);
-	    val = my_scope->set_parameter((*cur).first, val);
-	    assert(val);
-	    delete val;
+	    bool flag = my_scope->replace_parameter((*cur).first, val);
+	    if (! flag) {
+		  cerr << val->get_line() << ": warning: parameter "
+		       << (*cur).first << " not found in "
+		       << sc->name() << "." << endl;
+	    }
       }
 }
 
 /*
  * The isn't really able to create new scopes, but it does create the
  * event name in the current scope, so can be done during the
- * elaborate_scope scan.
+ * elaborate_scope scan. Note that the name_ of the PEvent object has
+ * no hierarchy, but neither does the NetEvent, until it is stored in
+ * the NetScope object.
  */
 void PEvent::elaborate_scope(Design*des, NetScope*scope) const
 {
@@ -284,6 +361,10 @@ void PFunction::elaborate_scope(Design*des, NetScope*scope) const
 
 void PTask::elaborate_scope(Design*des, NetScope*scope) const
 {
+      assert(scope->type() == NetScope::TASK);
+
+      if (statement_)
+	    statement_->elaborate_scope(des, scope);
 }
 
 
@@ -306,7 +387,7 @@ void PBlock::elaborate_scope(Design*des, NetScope*scope) const
       NetScope*my_scope = scope;
 
       if (name_ != "") {
-	    my_scope = new NetScope(scope, name_, bl_type_==BL_PAR
+	    my_scope = new NetScope(scope, name_.c_str(), bl_type_==BL_PAR
 				    ? NetScope::FORK_JOIN
 				    : NetScope::BEGIN_END);
       }
@@ -415,6 +496,52 @@ void PWhile::elaborate_scope(Design*des, NetScope*scope) const
 
 /*
  * $Log: elab_scope.cc,v $
+ * Revision 1.17  2002/10/19 22:59:49  steve
+ *  Redo the parameter vector support to allow
+ *  parameter names in range expressions.
+ *
+ * Revision 1.16  2002/09/01 03:01:48  steve
+ *  Properly cast signedness of parameters with ranges.
+ *
+ * Revision 1.15  2002/08/19 02:39:16  steve
+ *  Support parameters with defined ranges.
+ *
+ * Revision 1.14  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.13  2001/12/30 04:47:57  steve
+ *  Properly handle empty target in positionla parameter override.
+ *
+ * Revision 1.12  2001/12/03 04:47:14  steve
+ *  Parser and pform use hierarchical names as hname_t
+ *  objects instead of encoded strings.
+ *
+ * Revision 1.11  2001/10/20 05:21:51  steve
+ *  Scope/module names are char* instead of string.
+ *
+ * Revision 1.10  2001/10/09 02:01:04  steve
+ *  Tasks can have sub-scopes.
+ *
+ * Revision 1.9  2001/07/25 03:10:49  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
+ * Revision 1.8  2001/04/28 23:18:08  steve
+ *  UDP instances need not have user supplied names.
+ *
+ * Revision 1.7  2000/12/16 01:45:48  steve
+ *  Detect recursive instantiations (PR#2)
+ *
+ * Revision 1.6  2000/07/30 18:25:43  steve
+ *  Rearrange task and function elaboration so that the
+ *  NetTaskDef and NetFuncDef functions are created during
+ *  signal enaboration, and carry these objects in the
+ *  NetScope class instead of the extra, useless map in
+ *  the Design class.
+ *
+ * Revision 1.5  2000/07/22 22:09:03  steve
+ *  Parse and elaborate timescale to scopes.
+ *
  * Revision 1.4  2000/04/09 17:44:30  steve
  *  Catch event declarations during scope elaborate.
  *

elab_sig.cc

@@ -16,17 +16,50 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: elab_sig.cc,v 1.1 2000/05/02 16:27:38 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: elab_sig.cc,v 1.25 2002/08/12 01:34:59 steve Exp $"
 #endif
 
+# include "config.h"
+
+# include  <iostream>
+
 # include  "Module.h"
-# include "PExpr.h"
+# include  "PExpr.h"
 # include  "PGate.h"
+# include  "PTask.h"
 # include  "PWire.h"
 # include  "netlist.h"
+# include  "netmisc.h"
 # include  "util.h"
 
+/*
+ * This local function checks if a named signal is connected to a
+ * port. It looks in the array of ports passed, for NetEIdent objects
+ * within the port_t that have a matching name.
+ */
+static bool signal_is_in_port(const svector<Module::port_t*>&ports,
+			      const hname_t&name)
+{
+      for (unsigned idx = 0 ;  idx < ports.count() ;  idx += 1) {
+
+	    Module::port_t*pp = ports[idx];
+	      // Skip internally unconnected ports.
+	    if (pp == 0)
+		  continue;
+
+	      // This port has an internal connection. In this case,
+	      // the port has 0 or more NetEIdent objects concatenated
+	      // together that form the port.
+	    for (unsigned cc = 0 ;  cc < pp->expr.count() ;  cc += 1) {
+		  assert(pp->expr[cc]);
+		  if (pp->expr[cc]->path() == name)
+			return true;
+	    }
+      }
+
+      return false;
+}
 
 bool Module::elaborate_sig(Design*des, NetScope*scope) const
 {
@@ -34,13 +67,96 @@ bool Module::elaborate_sig(Design*des, NetScope*scope) const
 
 	// Get all the explicitly declared wires of the module and
 	// start the signals list with them.
-      const map<string,PWire*>&wl = get_wires();
+      const map<hname_t,PWire*>&wl = get_wires();
 
-      for (map<string,PWire*>::const_iterator wt = wl.begin()
+	// Scan all the ports of the module, and make sure that each
+	// is connected to wires that have port declarations.
+      for (unsigned idx = 0 ;  idx < ports.count() ;  idx += 1) {
+	    Module::port_t*pp = ports[idx];
+	    if (pp == 0)
+		  continue;
+
+	    map<hname_t,PWire*>::const_iterator wt;
+	    for (unsigned cc = 0 ;  cc < pp->expr.count() ;  cc += 1) {
+		  hname_t port_path (pp->expr[cc]->path());
+		  wt = wl.find(port_path);
+
+		  if (wt == wl.end()) {
+			cerr << get_line() << ": error: "
+			     << "Port " << pp->expr[cc]->path() << " ("
+			     << (idx+1) << ") of module " << name_
+			     << " is not declared within module." << endl;
+			des->errors += 1;
+			continue;
+		  }
+
+		  if ((*wt).second->get_port_type() == NetNet::NOT_A_PORT) {
+			cerr << get_line() << ": error: "
+			     << "Port " << pp->expr[cc]->path() << " ("
+			     << (idx+1) << ") of module " << name_
+			     << " has no direction declaration."
+			     << endl;
+			des->errors += 1;
+		  }
+	    }
+      }
+
+      for (map<hname_t,PWire*>::const_iterator wt = wl.begin()
 		 ; wt != wl.end()
 		 ; wt ++ ) {
 
-	    (*wt).second->elaborate_sig(des, scope);
+	    PWire*cur = (*wt).second;
+	    cur->elaborate_sig(des, scope);
+
+	    NetNet*sig = scope->find_signal_in_child(cur->path());
+
+	      // If this wire is a signal of the module (as opposed to
+	      // a port of a function) and is a port, then check that
+	      // the module knows about it. We know that the signal is
+	      // the name of a signal within a subscope of a module
+	      // (a task, a function, etc.) if the name for the PWire
+	      // has hierarchy.
+
+	    if (sig && (sig->scope() == scope)
+		&& (cur->get_port_type() != NetNet::NOT_A_PORT)) {
+
+		  hname_t name = (*wt).first;
+
+		  if (! signal_is_in_port(ports, name)) {
+
+			cerr << cur->get_line() << ": error: Signal "
+			     << name << " has a declared direction "
+			     << "but is not a port." << endl;
+			des->errors += 1;
+		  }
+	    }
+
+
+	      /* If the signal is an input and is also declared as a
+		 reg, then report an error. */
+
+	    if (sig && (sig->scope() == scope)
+		&& (sig->port_type() == NetNet::PINPUT)
+		&& (sig->type() == NetNet::REG)) {
+
+		  cerr << cur->get_line() << ": error: "
+		       << cur->path() << " in module "
+		       << scope->module_name()
+		       << " declared as input and as a reg type." << endl;
+		  des->errors += 1;
+	    }
+
+	    if (sig && (sig->scope() == scope)
+		&& (sig->port_type() == NetNet::PINOUT)
+		&& (sig->type() == NetNet::REG)) {
+
+		  cerr << cur->get_line() << ": error: "
+		       << cur->path() << " in  module "
+		       << scope->module_name()
+		       << " declared as inout and as a reg type." << endl;
+		  des->errors += 1;
+	    }
+
       }
 
 	// Get all the gates of the module and elaborate them by
@@ -57,6 +173,37 @@ bool Module::elaborate_sig(Design*des, NetScope*scope) const
 	    flag &= (*gt)->elaborate_sig(des, scope);
       }
 
+
+      typedef map<string,PFunction*>::const_iterator mfunc_it_t;
+
+      for (mfunc_it_t cur = funcs_.begin()
+		 ; cur != funcs_.end() ;  cur ++) {
+	    NetScope*fscope = scope->child((*cur).first);
+	    if (scope == 0) {
+		  cerr << (*cur).second->get_line() << ": internal error: "
+		       << "Child scope for function " << (*cur).first
+		       << " missing in " << scope->name() << "." << endl;
+		  des->errors += 1;
+		  continue;
+	    }
+
+	    (*cur).second->elaborate_sig(des, fscope);
+      }
+
+
+	// After all the wires are elaborated, we are free to
+	// elaborate the ports of the tasks defined within this
+	// module. Run through them now.
+
+      typedef map<string,PTask*>::const_iterator mtask_it_t;
+
+      for (mtask_it_t cur = tasks_.begin()
+		 ; cur != tasks_.end() ;  cur ++) {
+	    NetScope*tscope = scope->child((*cur).first);
+	    assert(tscope);
+	    (*cur).second->elaborate_sig(des, tscope);
+      }
+
       return flag;
 }
 
@@ -82,6 +229,128 @@ bool PGModule::elaborate_sig_mod_(Design*des, NetScope*scope,
       return rmod->elaborate_sig(des, my_scope);
 }
 
+/*
+ * A function definition exists within an elaborated module.
+ */
+void PFunction::elaborate_sig(Design*des, NetScope*scope) const
+{
+      string fname = scope->basename();
+      assert(scope->type() == NetScope::FUNC);
+
+	/* Make sure the function has at least one input port. If it
+	   fails this test, print an error message. Keep going so we
+	   can find more errors. */
+      if (ports_ == 0) {
+	    cerr << get_line() << ": error: Function " << fname
+		 << " has no ports." << endl;
+	    cerr << get_line() << ":      : Functions must have"
+		 << " at least one input port." << endl;
+	    des->errors += 1;
+      }
+
+      svector<NetNet*>ports (ports_? ports_->count()+1 : 1);
+
+	/* Get the reg for the return value. I know the name of the
+	   reg variable, and I know that it is in this scope, so look
+	   it up directly. */
+      ports[0] = scope->find_signal(scope->basename());
+      if (ports[0] == 0) {
+	    cerr << get_line() << ": internal error: function scope "
+		 << scope->name() << " is missing return reg "
+		 << fname << "." << endl;
+	    scope->dump(cerr);
+	    des->errors += 1;
+	    return;
+      }
+
+      if (ports_)
+	    for (unsigned idx = 0 ;  idx < ports_->count() ;  idx += 1) {
+
+		    /* Parse the port name into the task name and the reg
+		       name. We know by design that the port name is given
+		       as two components: <func>.<port>. */
+
+		  hname_t path = (*ports_)[idx]->path();
+		  string pname = path.peek_name(1);
+		  string ppath = path.peek_name(0);
+
+		  if (ppath != scope->basename()) {
+			cerr << get_line() << ": internal error: function "
+			     << "port " << (*ports_)[idx]->path()
+			     << " has wrong name for function "
+			     << scope->name() << "." << endl;
+			des->errors += 1;
+		  }
+
+		  NetNet*tmp = scope->find_signal(pname);
+		  if (tmp == 0) {
+			cerr << get_line() << ": internal error: function "
+			     << scope->name() << " is missing port "
+			     << pname << "." << endl;
+			scope->dump(cerr);
+			des->errors += 1;
+		  }
+
+		  ports[idx+1] = tmp;
+	    }
+
+
+      NetFuncDef*def = new NetFuncDef(scope, ports);
+      scope->set_func_def(def);
+}
+
+/*
+ * A task definition is a scope within an elaborated module. When we
+ * are elaborating signals, the scopes have already been created, as
+ * have the reg objects that are the parameters of this task. The
+ * elaborate_sig method of PTask is therefore left to connect the
+ * signals to the ports of the NetTaskDef definition. We know for
+ * certain that signals exist (They are in my scope!) so the port
+ * binding is sure to work.
+ */
+void PTask::elaborate_sig(Design*des, NetScope*scope) const
+{
+      assert(scope->type() == NetScope::TASK);
+
+      svector<NetNet*>ports (ports_? ports_->count() : 0);
+      for (unsigned idx = 0 ;  idx < ports.count() ;  idx += 1) {
+
+	      /* Parse the port name into the task name and the reg
+		 name. We know by design that the port name is given
+		 as two components: <task>.<port>. */
+
+	    hname_t path = (*ports_)[idx]->path();
+	    assert(path.peek_name(0) && path.peek_name(1));
+
+	      /* check that the current scope really does have the
+		 name of the first component of the task port name. Do
+		 this by looking up the task scope in the parent of
+		 the current scope. */
+	    if (scope->parent()->child(path.peek_name(0)) != scope) {
+		  cerr << "internal error: task scope " << path
+		       << " not the same as scope " << scope->name()
+		       << "?!" << endl;
+		  return;
+	    }
+
+	      /* Find the signal for the port. We know by definition
+		 that it is in the scope of the task, so look only in
+		 the scope. */
+	    NetNet*tmp = scope->find_signal(path.peek_name(1));
+
+	    if (tmp == 0) {
+		  cerr << get_line() << ": internal error: "
+		       << "Could not find port " << path.peek_name(1)
+		       << " in scope " << scope->name() << endl;
+		  scope->dump(cerr);
+	    }
+
+	    ports[idx] = tmp;
+      }
+
+      NetTaskDef*def = new NetTaskDef(scope->name(), ports);
+      scope->set_task_def(def);
+}
 
 bool PGate::elaborate_sig(Design*des, NetScope*scope) const
 {
@@ -100,19 +369,14 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
 	/* The parser may produce hierarchical names for wires. I here
 	   follow the scopes down to the base where I actually want to
 	   elaborate the NetNet object. */
-      string basename = name_;
-      for (;;) {
-	    string p = parse_first_name(basename);
-	    if (basename == "") {
-		  basename = p;
-		  break;
-	    }
-
-	    scope = scope->child(p);
-	    assert(scope);
+      { hname_t tmp_path = hname_;
+        free(tmp_path.remove_tail_name());
+	for (unsigned idx = 0 ;  tmp_path.peek_name(idx) ;  idx += 1) {
+	      scope = scope->child(tmp_path.peek_name(idx));
+	      assert(scope);
+	}
       }
 
-      const string path = scope->name();
       NetNet::Type wtype = type_;
       if (wtype == NetNet::IMPLICIT)
 	    wtype = NetNet::WIRE;
@@ -122,9 +386,14 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
       unsigned wid = 1;
       long lsb = 0, msb = 0;
 
+      assert(msb_.count() == lsb_.count());
       if (msb_.count()) {
 	    svector<long>mnum (msb_.count());
 	    svector<long>lnum (msb_.count());
+	      /* There may be places where the signal is declared as a
+		 scaler. Count those here, for consistency check
+		 later. */
+	    unsigned count_scalars = 0;
 
 	      /* There may be multiple declarations of ranges, because
 		 the symbol may have its range declared in i.e. input
@@ -132,29 +401,57 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
 		 here. I will resolve the values later. */
 
 	    for (unsigned idx = 0 ;  idx < msb_.count() ;  idx += 1) {
-		  verinum*mval = msb_[idx]->eval_const(des,path);
-		  if (mval == 0) {
+
+		  if (msb_[idx] == 0) {
+			count_scalars += 1;
+			assert(lsb_[idx] == 0);
+			mnum[idx] = 0;
+			lnum[idx] = 0;
+			continue;
+		  }
+
+		  NetEConst*tmp;
+		  NetExpr*texpr = elab_and_eval(des, scope, msb_[idx]);
+
+		  tmp = dynamic_cast<NetEConst*>(texpr);
+		  if (tmp == 0) {
 			cerr << msb_[idx]->get_line() << ": error: "
 			      "Unable to evaluate constant expression ``" <<
 			      *msb_[idx] << "''." << endl;
 			des->errors += 1;
 			return;
 		  }
-		  verinum*lval = lsb_[idx]->eval_const(des, path);
-		  if (mval == 0) {
-			cerr << lsb_[idx]->get_line() << ": error: "
+
+		  mnum[idx] = tmp->value().as_long();
+		  delete texpr;
+
+		  texpr = elab_and_eval(des, scope, lsb_[idx]);
+		  tmp = dynamic_cast<NetEConst*>(texpr);
+		  if (tmp == 0) {
+			cerr << msb_[idx]->get_line() << ": error: "
 			      "Unable to evaluate constant expression ``" <<
 			      *lsb_[idx] << "''." << endl;
 			des->errors += 1;
 			return;
 		  }
 
-		  mnum[idx] = mval->as_long();
-		  lnum[idx] = lval->as_long();
-		  delete mval;
-		  delete lval;
+		  lnum[idx] = tmp->value().as_long();
+		  delete texpr;
+
 	    }
 
+	      /* Check that the declarations were all scalar or all
+		 vector. It is an error to mix them. Use the
+		 count_scalars to know. */
+	    if ((count_scalars > 0) && (count_scalars != msb_.count())) {
+		  cerr << get_line() << ": error: Signal ``" << hname_
+		       << "'' declared both as a vector and a scalar."
+		       << endl;
+		  des->errors += 1;
+		  return;
+	    }
+
+
 	      /* Make sure all the values for msb and lsb match by
 		 value. If not, report an error. */
 	    for (unsigned idx = 1 ;  idx < msb_.count() ;  idx += 1) {
@@ -162,7 +459,7 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
 			cerr << get_line() << ": error: Inconsistent width, "
 			      "[" << mnum[idx] << ":" << lnum[idx] << "]"
 			      " vs. [" << mnum[0] << ":" << lnum[0] << "]"
-			      " for signal ``" << basename << "''" << endl;
+			      " for signal ``" << hname_ << "''" << endl;
 			des->errors += 1;
 			return;
 		  }
@@ -178,43 +475,146 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
 
       }
 
+      unsigned nattrib = 0;
+      attrib_list_t*attrib_list = evaluate_attributes(attributes, nattrib,
+						      des, scope);
+
       if (lidx_ || ridx_) {
 	    assert(lidx_ && ridx_);
 
 	      // If the register has indices, then this is a
 	      // memory. Create the memory object.
-	    verinum*lval = lidx_->eval_const(des, path);
+	    verinum*lval = lidx_->eval_const(des, scope);
+	    verinum*rval = ridx_->eval_const(des, scope);
+
+	    if ((lval == 0) || (rval == 0)) {
+		  cerr << get_line() << ": internal error: There is "
+		       << "a problem evaluating indices for ``"
+		       << hname_.peek_tail_name() << "''." << endl;
+		  des->errors += 1;
+		  return;
+	    }
+
 	    assert(lval);
-	    verinum*rval = ridx_->eval_const(des, path);
 	    assert(rval);
 
+	    string name = hname_.peek_tail_name();
+
 	    long lnum = lval->as_long();
 	    long rnum = rval->as_long();
 	    delete lval;
 	    delete rval;
-	    NetMemory*sig = new NetMemory(scope, path+"."+basename,
-					  wid, lnum, rnum);
-	    sig->set_attributes(attributes);
+	    NetMemory*sig = new NetMemory(scope, name, wid, lnum, rnum);
 
       } else {
 
-	    NetNet*sig = new NetNet(scope, path + "." +basename, wtype, msb, lsb);
+	      /* Make a hierarchical make for the signal. */
+	    string name = scope->name();
+	    name = name + "." + hname_.peek_tail_name();
+
+	    NetNet*sig = new NetNet(scope, name, wtype, msb, lsb);
 	    sig->set_line(*this);
 	    sig->port_type(port_type_);
-	    sig->set_attributes(attributes);
-
-	    verinum::V iv = verinum::Vz;
-	    if (wtype == NetNet::REG)
-		  iv = verinum::Vx;
-
-	    for (unsigned idx = 0 ;  idx < wid ;  idx += 1)
-		  sig->set_ival(idx, iv);
+	    sig->set_signed(get_signed());
+	    sig->set_isint(get_isint());
 
+	    for (unsigned idx = 0 ;  idx < nattrib ;  idx += 1)
+		  sig->attribute(attrib_list[idx].key, attrib_list[idx].val);
       }
 }
 
 /*
  * $Log: elab_sig.cc,v $
+ * Revision 1.25  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.24  2002/08/05 04:18:45  steve
+ *  Store only the base name of memories.
+ *
+ * Revision 1.23  2002/06/21 04:59:35  steve
+ *  Carry integerness throughout the compilation.
+ *
+ * Revision 1.22  2002/05/23 03:08:51  steve
+ *  Add language support for Verilog-2001 attribute
+ *  syntax. Hook this support into existing $attribute
+ *  handling, and add number and void value types.
+ *
+ *  Add to the ivl_target API new functions for access
+ *  of complex attributes attached to gates.
+ *
+ * Revision 1.21  2002/05/19 23:37:28  steve
+ *  Parse port_declaration_lists from the 2001 Standard.
+ *
+ * Revision 1.20  2002/01/26 05:28:28  steve
+ *  Detect scalar/vector declarion mismatch.
+ *
+ * Revision 1.19  2002/01/23 03:35:17  steve
+ *  Detect incorrect function ports.
+ *
+ * Revision 1.18  2001/12/03 04:47:14  steve
+ *  Parser and pform use hierarchical names as hname_t
+ *  objects instead of encoded strings.
+ *
+ * Revision 1.17  2001/11/07 04:01:59  steve
+ *  eval_const uses scope instead of a string path.
+ *
+ * Revision 1.16  2001/11/01 05:21:26  steve
+ *  Catch ports that have no direction.
+ *
+ * Revision 1.15  2001/10/31 03:11:15  steve
+ *  detect module ports not declared within the module.
+ *
+ * Revision 1.14  2001/07/25 03:10:49  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
+ * Revision 1.13  2001/05/25 02:21:34  steve
+ *  Detect input and input ports declared as reg.
+ *
+ * Revision 1.12  2001/02/17 05:15:33  steve
+ *  Allow task ports to be given real types.
+ *
+ * Revision 1.11  2001/02/10 20:29:39  steve
+ *  In the context of range declarations, use elab_and_eval instead
+ *  of the less robust eval_const methods.
+ *
+ * Revision 1.10  2001/01/13 22:20:08  steve
+ *  Parse parameters within nested scopes.
+ *
+ * Revision 1.9  2001/01/07 07:00:31  steve
+ *  Detect port direction attached to non-ports.
+ *
+ * Revision 1.8  2001/01/04 04:47:51  steve
+ *  Add support for << is signal indices.
+ *
+ * Revision 1.7  2000/12/11 00:31:43  steve
+ *  Add support for signed reg variables,
+ *  simulate in t-vvm signed comparisons.
+ *
+ * Revision 1.6  2000/12/04 17:37:04  steve
+ *  Add Attrib class for holding NetObj attributes.
+ *
+ * Revision 1.5  2000/11/20 00:58:40  steve
+ *  Add support for supply nets (PR#17)
+ *
+ * Revision 1.4  2000/09/07 22:37:48  steve
+ *  ack, detect when lval fails.
+ *
+ * Revision 1.3  2000/07/30 18:25:43  steve
+ *  Rearrange task and function elaboration so that the
+ *  NetTaskDef and NetFuncDef functions are created during
+ *  signal enaboration, and carry these objects in the
+ *  NetScope class instead of the extra, useless map in
+ *  the Design class.
+ *
+ * Revision 1.2  2000/07/14 06:12:57  steve
+ *  Move inital value handling from NetNet to Nexus
+ *  objects. This allows better propogation of inital
+ *  values.
+ *
+ *  Clean up constant propagation  a bit to account
+ *  for regs that are not really values.
+ *
  * Revision 1.1  2000/05/02 16:27:38  steve
  *  Move signal elaboration to a seperate pass.
  *

emit.cc

@@ -16,229 +16,234 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: emit.cc,v 1.45 2000/05/11 23:37:27 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: emit.cc,v 1.70 2002/11/03 20:36:10 steve Exp $"
 #endif
 
+# include "config.h"
+
+# include  <iostream>
+
 /*
  * The emit function is called to generate the output required of the
  * target.
  */
 # include  "target.h"
 # include  "netlist.h"
-# include  <iostream>
 # include  <typeinfo>
 # include  <cassert>
 
-void NetNode::emit_node(ostream&o, struct target_t*tgt) const
+bool NetNode::emit_node(struct target_t*tgt) const
 {
       cerr << "EMIT: Gate type? " << typeid(*this).name() << endl;
+      return false;
 }
 
-void NetLogic::emit_node(ostream&o, struct target_t*tgt) const
+bool NetLogic::emit_node(struct target_t*tgt) const
 {
-      tgt->logic(o, this);
+      tgt->logic(this);
+      return true;
 }
 
-void NetUDP_COMB::emit_node(ostream&o, struct target_t*tgt) const
+bool NetUDP::emit_node(struct target_t*tgt) const
 {
-      tgt->udp_comb(o, this);
+      tgt->udp(this);
+      return true;
 }
 
-void NetUDP::emit_node(ostream&o, struct target_t*tgt) const
+bool NetAddSub::emit_node(struct target_t*tgt) const
 {
-      tgt->udp(o, this);
+      tgt->lpm_add_sub(this);
+      return true;
 }
 
-void NetAddSub::emit_node(ostream&o, struct target_t*tgt) const
+bool NetCaseCmp::emit_node(struct target_t*tgt) const
 {
-      tgt->lpm_add_sub(o, this);
+      tgt->net_case_cmp(this);
+      return true;
 }
 
-void NetAssign::emit_node(ostream&o, struct target_t*tgt) const
+bool NetCAssign::emit_node(struct target_t*tgt) const
 {
-      tgt->net_assign(o, this);
+      tgt->net_cassign(this);
+      return true;
 }
 
-void NetAssignNB::emit_node(ostream&o, struct target_t*tgt) const
+bool NetCLShift::emit_node(struct target_t*tgt) const
 {
-      tgt->net_assign_nb(o, this);
+      tgt->lpm_clshift(this);
+      return true;
 }
 
-void NetCaseCmp::emit_node(ostream&o, struct target_t*tgt) const
+bool NetCompare::emit_node(struct target_t*tgt) const
 {
-      tgt->net_case_cmp(o, this);
+      tgt->lpm_compare(this);
+      return true;
 }
 
-void NetCAssign::emit_node(ostream&o, struct target_t*tgt) const
+bool NetConst::emit_node(struct target_t*tgt) const
 {
-      tgt->net_cassign(o, this);
+      return tgt->net_const(this);
 }
 
-void NetCLShift::emit_node(ostream&o, struct target_t*tgt) const
+bool NetDivide::emit_node(struct target_t*tgt) const
 {
-      tgt->lpm_clshift(o, this);
+      tgt->lpm_divide(this);
+      return true;
 }
 
-void NetCompare::emit_node(ostream&o, struct target_t*tgt) const
+bool NetFF::emit_node(struct target_t*tgt) const
 {
-      tgt->lpm_compare(o, this);
+      tgt->lpm_ff(this);
+      return true;
 }
 
-void NetConst::emit_node(ostream&o, struct target_t*tgt) const
+bool NetForce::emit_node(struct target_t*tgt) const
 {
-      tgt->net_const(o, this);
+      tgt->net_force(this);
+      return true;
 }
 
-void NetDivide::emit_node(ostream&o, struct target_t*tgt) const
+bool NetModulo::emit_node(struct target_t*tgt) const
 {
-      tgt->lpm_divide(o, this);
+      tgt->lpm_modulo(this);
+      return true;
 }
 
-void NetFF::emit_node(ostream&o, struct target_t*tgt) const
+bool NetMult::emit_node(struct target_t*tgt) const
 {
-      tgt->lpm_ff(o, this);
+      tgt->lpm_mult(this);
+      return true;
 }
 
-void NetForce::emit_node(ostream&o, struct target_t*tgt) const
+bool NetMux::emit_node(struct target_t*tgt) const
 {
-      tgt->net_force(o, this);
+      tgt->lpm_mux(this);
+      return true;
 }
 
-void NetMult::emit_node(ostream&o, struct target_t*tgt) const
+bool NetRamDq::emit_node(struct target_t*tgt) const
 {
-      tgt->lpm_mult(o, this);
+      tgt->lpm_ram_dq(this);
+      return true;
 }
 
-void NetMux::emit_node(ostream&o, struct target_t*tgt) const
+bool NetUserFunc::emit_node(struct target_t*tgt) const
 {
-      tgt->lpm_mux(o, this);
+      return tgt->net_function(this);
 }
 
-void NetRamDq::emit_node(ostream&o, struct target_t*tgt) const
+bool NetBUFZ::emit_node(struct target_t*tgt) const
 {
-      tgt->lpm_ram_dq(o, this);
+      return tgt->bufz(this);
 }
 
-void NetBUFZ::emit_node(ostream&o, struct target_t*tgt) const
+bool NetProcTop::emit(struct target_t*tgt) const
 {
-      tgt->bufz(o, this);
+      return tgt->process(this);
 }
 
-bool NetProcTop::emit(ostream&o, struct target_t*tgt) const
-{
-      return tgt->process(o, this);
-}
-
-bool NetProc::emit_proc(ostream&o, struct target_t*tgt) const
+bool NetProc::emit_proc(struct target_t*tgt) const
 {
       cerr << "EMIT: Proc type? " << typeid(*this).name() << endl;
       return false;
 }
 
-bool NetAssign::emit_proc(ostream&o, struct target_t*tgt) const
+bool NetAssign::emit_proc(struct target_t*tgt) const
 {
-      tgt->proc_assign(o, this);
+      tgt->proc_assign(this);
       return true;
 }
 
-bool NetAssignNB::emit_proc(ostream&o, struct target_t*tgt) const
+bool NetAssignNB::emit_proc(struct target_t*tgt) const
 {
-      tgt->proc_assign_nb(o, this);
+      tgt->proc_assign_nb(this);
       return true;
 }
 
-bool NetAssignMem::emit_proc(ostream&o, struct target_t*tgt) const
+bool NetBlock::emit_proc(struct target_t*tgt) const
 {
-      tgt->proc_assign_mem(o, this);
+      return tgt->proc_block(this);
+}
+
+bool NetCase::emit_proc(struct target_t*tgt) const
+{
+      tgt->proc_case(this);
       return true;
 }
 
-bool NetAssignMemNB::emit_proc(ostream&o, struct target_t*tgt) const
+bool NetCAssign::emit_proc(struct target_t*tgt) const
 {
-      tgt->proc_assign_mem_nb(o, this);
+      return tgt->proc_cassign(this);
+}
+
+bool NetCondit::emit_proc(struct target_t*tgt) const
+{
+      return tgt->proc_condit(this);
+}
+
+bool NetDeassign::emit_proc(struct target_t*tgt) const
+{
+      return tgt->proc_deassign(this);
+}
+
+bool NetDisable::emit_proc(struct target_t*tgt) const
+{
+      return tgt->proc_disable(this);
+}
+
+bool NetForce::emit_proc(struct target_t*tgt) const
+{
+      return tgt->proc_force(this);
+}
+
+bool NetForever::emit_proc(struct target_t*tgt) const
+{
+      tgt->proc_forever(this);
       return true;
 }
 
-bool NetBlock::emit_proc(ostream&o, struct target_t*tgt) const
+bool NetPDelay::emit_proc(struct target_t*tgt) const
 {
-      return tgt->proc_block(o, this);
+      return tgt->proc_delay(this);
 }
 
-bool NetCase::emit_proc(ostream&o, struct target_t*tgt) const
+bool NetPDelay::emit_proc_recurse(struct target_t*tgt) const
 {
-      tgt->proc_case(o, this);
+      if (statement_) return statement_->emit_proc(tgt);
       return true;
 }
 
-bool NetCAssign::emit_proc(ostream&o, struct target_t*tgt) const
+bool NetRelease::emit_proc(struct target_t*tgt) const
 {
-      return tgt->proc_cassign(o, this);
+      return tgt->proc_release(this);
 }
 
-bool NetCondit::emit_proc(ostream&o, struct target_t*tgt) const
+bool NetRepeat::emit_proc(struct target_t*tgt) const
 {
-      tgt->proc_condit(o, this);
+      tgt->proc_repeat(this);
       return true;
 }
 
-bool NetDeassign::emit_proc(ostream&o, struct target_t*tgt) const
+bool NetSTask::emit_proc(struct target_t*tgt) const
 {
-      return tgt->proc_deassign(o, this);
-}
-
-bool NetForce::emit_proc(ostream&o, struct target_t*tgt) const
-{
-      return tgt->proc_force(o, this);
-}
-
-bool NetForever::emit_proc(ostream&o, struct target_t*tgt) const
-{
-      tgt->proc_forever(o, this);
+      tgt->proc_stask(this);
       return true;
 }
 
-bool NetPDelay::emit_proc(ostream&o, struct target_t*tgt) const
+bool NetUTask::emit_proc(struct target_t*tgt) const
 {
-      tgt->proc_delay(o, this);
+      tgt->proc_utask(this);
       return true;
 }
 
-void NetPDelay::emit_proc_recurse(ostream&o, struct target_t*tgt) const
+bool NetWhile::emit_proc(struct target_t*tgt) const
 {
-      if (statement_) statement_->emit_proc(o, tgt);
-}
-
-bool NetRelease::emit_proc(ostream&o, struct target_t*tgt) const
-{
-      return tgt->proc_release(o, this);
-}
-
-bool NetRepeat::emit_proc(ostream&o, struct target_t*tgt) const
-{
-      tgt->proc_repeat(o, this);
+      tgt->proc_while(this);
       return true;
 }
 
-bool NetSTask::emit_proc(ostream&o, struct target_t*tgt) const
-{
-      tgt->proc_stask(o, this);
-      return true;
-}
-
-bool NetUTask::emit_proc(ostream&o, struct target_t*tgt) const
-{
-      tgt->proc_utask(o, this);
-      return true;
-}
-
-bool NetWhile::emit_proc(ostream&o, struct target_t*tgt) const
-{
-      tgt->proc_while(o, this);
-      return true;
-}
-
-void NetBlock::emit_recurse(ostream&o, struct target_t*tgt) const
+void NetBlock::emit_recurse(struct target_t*tgt) const
 {
       if (last_ == 0)
 	    return;
@@ -246,69 +251,74 @@ void NetBlock::emit_recurse(ostream&o, struct target_t*tgt) const
       NetProc*cur = last_;
       do {
 	    cur = cur->next_;
-	    cur->emit_proc(o, tgt);
+	    cur->emit_proc(tgt);
       } while (cur != last_);
 }
 
-void NetCondit::emit_recurse_if(ostream&o, struct target_t*tgt) const
+bool NetCondit::emit_recurse_if(struct target_t*tgt) const
 {
       if (if_)
-	    if_->emit_proc(o, tgt);
+	    return if_->emit_proc(tgt);
+      else
+	    return true;
 }
 
-void NetCondit::emit_recurse_else(ostream&o, struct target_t*tgt) const
+bool NetCondit::emit_recurse_else(struct target_t*tgt) const
 {
       if (else_)
-	    else_->emit_proc(o, tgt);
+	    return else_->emit_proc(tgt);
+      else
+	    return true;
 }
 
-void NetEvProbe::emit_node(ostream&o, struct target_t*tgt) const
+bool NetEvProbe::emit_node(struct target_t*tgt) const
 {
-      tgt->net_probe(o, this);
+      tgt->net_probe(this);
+      return true;
 }
 
-bool NetEvTrig::emit_proc(ostream&o, struct target_t*tgt) const
+bool NetEvTrig::emit_proc(struct target_t*tgt) const
 {
-      return tgt->proc_trigger(o, this);
+      return tgt->proc_trigger(this);
 }
 
-bool NetEvWait::emit_proc(ostream&o, struct target_t*tgt) const
+bool NetEvWait::emit_proc(struct target_t*tgt) const
 {
-      return tgt->proc_wait(o, this);
+      return tgt->proc_wait(this);
 }
 
-bool NetEvWait::emit_recurse(ostream&o, struct target_t*tgt) const
+bool NetEvWait::emit_recurse(struct target_t*tgt) const
 {
       if (!statement_) return true;
-      return statement_->emit_proc(o, tgt);
+      return statement_->emit_proc(tgt);
 }
 
-void NetForever::emit_recurse(ostream&o, struct target_t*tgt) const
+void NetForever::emit_recurse(struct target_t*tgt) const
 {
       if (statement_)
-	    statement_->emit_proc(o, tgt);
+	    statement_->emit_proc(tgt);
 }
 
-void NetRepeat::emit_recurse(ostream&o, struct target_t*tgt) const
+void NetRepeat::emit_recurse(struct target_t*tgt) const
 {
       if (statement_)
-	    statement_->emit_proc(o, tgt);
+	    statement_->emit_proc(tgt);
 }
 
-void NetScope::emit_scope(ostream&o, struct target_t*tgt) const
+void NetScope::emit_scope(struct target_t*tgt) const
 {
-      tgt->scope(o, this);
+      tgt->scope(this);
 
       for (NetEvent*cur = events_ ;  cur ;  cur = cur->snext_)
-	    tgt->event(o, cur);
+	    tgt->event(cur);
 
       for (NetScope*cur = sub_ ;  cur ;  cur = cur->sib_)
-	    cur->emit_scope(o, tgt);
+	    cur->emit_scope(tgt);
 
       if (signals_) {
 	    NetNet*cur = signals_->sig_next_;
 	    do {
-		  tgt->signal(o, cur);
+		  tgt->signal(cur);
 		  cur = cur->sig_next_;
 	    } while (cur != signals_->sig_next_);
       }
@@ -316,57 +326,73 @@ void NetScope::emit_scope(ostream&o, struct target_t*tgt) const
       if (memories_) {
 	    NetMemory*cur = memories_->snext_;
 	    do {
-		  tgt->memory(o, cur);
+		  tgt->memory(cur);
 		  cur = cur->snext_;
 	    } while (cur != memories_->snext_);
       }
 }
 
-void NetWhile::emit_proc_recurse(ostream&o, struct target_t*tgt) const
+void NetScope::emit_defs(struct target_t*tgt) const
 {
-      proc_->emit_proc(o, tgt);
+
+      switch (type_) {
+	  case MODULE:
+	    for (NetScope*cur = sub_ ;  cur ;  cur = cur->sib_)
+		  cur->emit_defs(tgt);
+	    break;
+
+	  case FUNC:
+	    tgt->func_def(this);
+	    break;
+	  case TASK:
+	    tgt->task_def(this);
+	    break;
+      }
+
 }
 
-bool Design::emit(ostream&o, struct target_t*tgt) const
+void NetWhile::emit_proc_recurse(struct target_t*tgt) const
+{
+      proc_->emit_proc(tgt);
+}
+
+bool Design::emit(struct target_t*tgt) const
 {
       bool rc = true;
-      tgt->start_design(o, this);
+
+      rc = rc && tgt->start_design(this);
+      if (rc == false)
+	    return false;
 
 	// enumerate the scopes
-      root_scope_->emit_scope(o, tgt);
+      for (list<NetScope*>::const_iterator scope = root_scopes_.begin(); 
+	   scope != root_scopes_.end(); scope++)
+	    (*scope)->emit_scope(tgt);
 
 
 	// emit nodes
       if (nodes_) {
 	    NetNode*cur = nodes_->node_next_;
 	    do {
-		  cur->emit_node(o, tgt);
+		  rc = rc && cur->emit_node(tgt);
 		  cur = cur->node_next_;
 	    } while (cur != nodes_->node_next_);
       }
 
 
-	// emit function definitions
-      {
-	    map<string,NetFuncDef*>::const_iterator ta;
-	    for (ta = funcs_.begin() ; ta != funcs_.end() ;  ta ++) {
-		  tgt->func_def(o, (*ta).second);
-	    }
-      }
+	// emit task and function definitions
+      for (list<NetScope*>::const_iterator scope = root_scopes_.begin(); 
+	   scope != root_scopes_.end(); scope++)
+	    (*scope)->emit_defs(tgt);
 
-	// emit task definitions
-      {
-	    map<string,NetTaskDef*>::const_iterator ta;
-	    for (ta = tasks_.begin() ; ta != tasks_.end() ;  ta ++) {
-		  tgt->task_def(o, (*ta).second);
-	    }
-      }
 
 	// emit the processes
       for (const NetProcTop*idx = procs_ ;  idx ;  idx = idx->next_)
-	    rc = rc && idx->emit(o, tgt);
+	    rc = rc && idx->emit(tgt);
+
+      if (tgt->end_design(this) != 0)
+	    rc = false;
 
-      tgt->end_design(o, this);
       return rc;
 }
 
@@ -385,11 +411,6 @@ void NetEConst::expr_scan(struct expr_scan_t*tgt) const
       tgt->expr_const(this);
 }
 
-void NetEIdent::expr_scan(struct expr_scan_t*tgt) const
-{
-      tgt->expr_ident(this);
-}
-
 void NetEMemory::expr_scan(struct expr_scan_t*tgt) const
 {
       tgt->expr_memory(this);
@@ -406,6 +427,11 @@ void NetEScope::expr_scan(struct expr_scan_t*tgt) const
       tgt->expr_scope(this);
 }
 
+void NetESelect::expr_scan(struct expr_scan_t*tgt) const
+{
+      tgt->expr_select(this);
+}
+
 void NetESFunc::expr_scan(struct expr_scan_t*tgt) const
 {
       tgt->expr_sfunc(this);
@@ -421,7 +447,7 @@ void NetESignal::expr_scan(struct expr_scan_t*tgt) const
       tgt->expr_signal(this);
 }
 
-void NetESubSignal::expr_scan(struct expr_scan_t*tgt) const
+void NetEBitSel::expr_scan(struct expr_scan_t*tgt) const
 {
       tgt->expr_subsignal(this);
 }
@@ -436,19 +462,117 @@ void NetEUnary::expr_scan(struct expr_scan_t*tgt) const
       tgt->expr_unary(this);
 }
 
-bool emit(ostream&o, const Design*des, const char*type)
+bool emit(const Design*des, const char*type)
 {
       for (unsigned idx = 0 ;  target_table[idx] ;  idx += 1) {
 	    const struct target*tgt = target_table[idx];
-	    if (tgt->name == type)
-		  return des->emit(o, tgt->meth);
+	    if (strcmp(tgt->name, type) == 0)
+		  return des->emit(tgt->meth);
 
       }
+
+      cerr << "error: Code generator type " << type
+	   << " not found." << endl;
+      return false;
 }
 
 
 /*
  * $Log: emit.cc,v $
+ * Revision 1.70  2002/11/03 20:36:10  steve
+ *  Error message for mising code generator type.
+ *
+ * Revision 1.69  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.68  2002/06/05 03:44:25  steve
+ *  Add support for memory words in l-value of
+ *  non-blocking assignments, and remove the special
+ *  NetAssignMem_ and NetAssignMemNB classes.
+ *
+ * Revision 1.67  2002/06/04 05:38:44  steve
+ *  Add support for memory words in l-value of
+ *  blocking assignments, and remove the special
+ *  NetAssignMem class.
+ *
+ * Revision 1.66  2002/03/09 02:10:22  steve
+ *  Add the NetUserFunc netlist node.
+ *
+ * Revision 1.65  2002/01/28 00:52:41  steve
+ *  Add support for bit select of parameters.
+ *  This leads to a NetESelect node and the
+ *  vvp code generator to support that.
+ *
+ * Revision 1.64  2002/01/19 19:02:08  steve
+ *  Pass back target errors processing conditionals.
+ *
+ * Revision 1.63  2001/10/19 21:53:24  steve
+ *  Support multiple root modules (Philip Blundell)
+ *
+ * Revision 1.62  2001/08/25 23:50:02  steve
+ *  Change the NetAssign_ class to refer to the signal
+ *  instead of link into the netlist. This is faster
+ *  and uses less space. Make the NetAssignNB carry
+ *  the delays instead of the NetAssign_ lval objects.
+ *
+ *  Change the vvp code generator to support multiple
+ *  l-values, i.e. concatenations of part selects.
+ *
+ * Revision 1.61  2001/07/27 04:51:44  steve
+ *  Handle part select expressions as variants of
+ *  NetESignal/IVL_EX_SIGNAL objects, instead of
+ *  creating new and useless temporary signals.
+ *
+ * Revision 1.60  2001/07/25 03:10:49  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
+ * Revision 1.59  2001/04/22 23:09:46  steve
+ *  More UDP consolidation from Stephan Boettcher.
+ *
+ * Revision 1.58  2001/04/06 02:28:02  steve
+ *  Generate vvp code for functions with ports.
+ *
+ * Revision 1.57  2001/04/02 02:28:12  steve
+ *  Generate code for task calls.
+ *
+ * Revision 1.56  2001/03/27 03:31:06  steve
+ *  Support error code from target_t::end_design method.
+ *
+ * Revision 1.55  2000/11/04 01:54:01  steve
+ *  Modifications in support of gcc 2.96
+ *
+ * Revision 1.54  2000/09/26 01:35:42  steve
+ *  Remove the obsolete NetEIdent class.
+ *
+ * Revision 1.53  2000/09/17 21:26:15  steve
+ *  Add support for modulus (Eric Aardoom)
+ *
+ * Revision 1.52  2000/09/02 20:54:20  steve
+ *  Rearrange NetAssign to make NetAssign_ separate.
+ *
+ * Revision 1.51  2000/08/14 04:39:56  steve
+ *  add th t-dll functions for net_const, net_bufz and processes.
+ *
+ * Revision 1.50  2000/08/09 03:43:45  steve
+ *  Move all file manipulation out of target class.
+ *
+ * Revision 1.49  2000/08/08 01:50:42  steve
+ *  target methods need not take a file stream.
+ *
+ * Revision 1.48  2000/07/30 18:25:43  steve
+ *  Rearrange task and function elaboration so that the
+ *  NetTaskDef and NetFuncDef functions are created during
+ *  signal enaboration, and carry these objects in the
+ *  NetScope class instead of the extra, useless map in
+ *  the Design class.
+ *
+ * Revision 1.47  2000/07/29 16:21:08  steve
+ *  Report code generation errors through proc_delay.
+ *
+ * Revision 1.46  2000/07/27 05:13:44  steve
+ *  Support elaboration of disable statements.
+ *
  * Revision 1.45  2000/05/11 23:37:27  steve
  *  Add support for procedural continuous assignment.
  *
@@ -480,117 +604,5 @@ bool emit(ostream&o, const Design*des, const char*type)
  *  Do not generate NetPEvent or NetNEvent objects in
  *  elaboration. NetEvent, NetEvWait and NetEvProbe
  *  take over those functions in the netlist.
- *
- * Revision 1.38  2000/04/10 05:26:06  steve
- *  All events now use the NetEvent class.
- *
- * Revision 1.37  2000/04/04 03:20:15  steve
- *  Simulate named event trigger and waits.
- *
- * Revision 1.36  2000/04/01 21:40:22  steve
- *  Add support for integer division.
- *
- * Revision 1.35  2000/03/29 04:37:11  steve
- *  New and improved combinational primitives.
- *
- * Revision 1.34  2000/03/08 04:36:53  steve
- *  Redesign the implementation of scopes and parameters.
- *  I now generate the scopes and notice the parameters
- *  in a separate pass over the pform. Once the scopes
- *  are generated, I can process overrides and evalutate
- *  paremeters before elaboration begins.
- *
- * Revision 1.33  2000/02/23 02:56:54  steve
- *  Macintosh compilers do not support ident.
- *
- * Revision 1.32  2000/01/13 03:35:35  steve
- *  Multiplication all the way to simulation.
- *
- * Revision 1.31  1999/11/28 23:42:02  steve
- *  NetESignal object no longer need to be NetNode
- *  objects. Let them keep a pointer to NetNet objects.
- *
- * Revision 1.30  1999/11/27 19:07:57  steve
- *  Support the creation of scopes.
- *
- * Revision 1.29  1999/11/21 00:13:08  steve
- *  Support memories in continuous assignments.
- *
- * Revision 1.28  1999/11/14 23:43:45  steve
- *  Support combinatorial comparators.
- *
- * Revision 1.27  1999/11/14 20:24:28  steve
- *  Add support for the LPM_CLSHIFT device.
- *
- * Revision 1.26  1999/11/04 03:53:26  steve
- *  Patch to synthesize unary ~ and the ternary operator.
- *  Thanks to Larry Doolittle <LRDoolittle@lbl.gov>.
- *
- *  Add the LPM_MUX device, and integrate it with the
- *  ternary synthesis from Larry. Replace the lpm_mux
- *  generator in t-xnf.cc to use XNF EQU devices to
- *  put muxs into function units.
- *
- *  Rewrite elaborate_net for the PETernary class to
- *  also use the LPM_MUX device.
- *
- * Revision 1.25  1999/11/01 02:07:40  steve
- *  Add the synth functor to do generic synthesis
- *  and add the LPM_FF device to handle rows of
- *  flip-flops.
- *
- * Revision 1.24  1999/10/10 01:59:54  steve
- *  Structural case equals device.
- *
- * Revision 1.23  1999/09/22 16:57:23  steve
- *  Catch parallel blocks in vvm emit.
- *
- * Revision 1.22  1999/09/20 02:21:10  steve
- *  Elaborate parameters in phases.
- *
- * Revision 1.21  1999/09/15 01:55:06  steve
- *  Elaborate non-blocking assignment to memories.
- *
- * Revision 1.20  1999/09/03 04:28:38  steve
- *  elaborate the binary plus operator.
- *
- * Revision 1.19  1999/08/31 22:38:29  steve
- *  Elaborate and emit to vvm procedural functions.
- *
- * Revision 1.18  1999/07/17 19:50:59  steve
- *  netlist support for ternary operator.
- *
- * Revision 1.17  1999/07/17 03:39:11  steve
- *  simplified process scan for targets.
- *
- * Revision 1.16  1999/07/07 04:20:57  steve
- *  Emit vvm for user defined tasks.
- *
- * Revision 1.15  1999/07/03 02:12:51  steve
- *  Elaborate user defined tasks.
- *
- * Revision 1.14  1999/06/19 21:06:16  steve
- *  Elaborate and supprort to vvm the forever
- *  and repeat statements.
- *
- * Revision 1.13  1999/06/09 03:00:06  steve
- *  Add support for procedural concatenation expression.
- *
- * Revision 1.12  1999/06/06 20:45:38  steve
- *  Add parse and elaboration of non-blocking assignments,
- *  Replace list<PCase::Item*> with an svector version,
- *  Add integer support.
- *
- * Revision 1.11  1999/05/12 04:03:19  steve
- *  emit NetAssignMem objects in vvm target.
- *
- * Revision 1.10  1999/05/07 01:21:18  steve
- *  Handle total lack of nodes and signals.
- *
- * Revision 1.9  1999/05/01 02:57:53  steve
- *  Handle much more complex event expressions.
- *
- * Revision 1.8  1999/04/25 00:44:10  steve
- *  Core handles subsignal expressions.
  */
 

eval.cc

@@ -16,114 +16,168 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: eval.cc,v 1.14 2000/03/08 04:36:53 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: eval.cc,v 1.32 2002/10/19 22:59:49 steve Exp $"
 #endif
 
+# include "config.h"
+
+# include  <iostream>
+
 # include  "PExpr.h"
 # include  "netlist.h"
+# include  "compiler.h"
 
-verinum* PExpr::eval_const(const Design*, const string&) const
+verinum* PExpr::eval_const(const Design*, const NetScope*) const
 {
       return 0;
 }
 
-verinum* PEBinary::eval_const(const Design*des, const string&path) const
+verinum* PEBinary::eval_const(const Design*des, const NetScope*scope) const
 {
-      verinum*l = left_->eval_const(des, path);
+      verinum*l = left_->eval_const(des, scope);
       if (l == 0) return 0;
-      verinum*r = right_->eval_const(des, path);
+      verinum*r = right_->eval_const(des, scope);
       if (r == 0) {
 	    delete l;
 	    return 0;
       }
-
       verinum*res;
 
       switch (op_) {
 	  case '+': {
-		assert(l->is_defined());
-		assert(r->is_defined());
-		long lv = l->as_long();
-		long rv = r->as_long();
-		res = new verinum(lv+rv, l->len());
+		if (l->is_defined() && r->is_defined()) {
+		      long lv = l->as_long();
+		      long rv = r->as_long();
+		      res = new verinum(lv+rv, l->len());
+		} else {
+		      res = new verinum(verinum::Vx, l->len());
+		}
 		break;
 	  }
 	  case '-': {
-		assert(l->is_defined());
-		assert(r->is_defined());
-		long lv = l->as_long();
-		long rv = r->as_long();
-		res = new verinum(lv-rv, l->len());
+		if (l->is_defined() && r->is_defined()) {
+		      long lv = l->as_long();
+		      long rv = r->as_long();
+		      res = new verinum(lv-rv, l->len());
+		} else {
+		      res = new verinum(verinum::Vx, l->len());
+		}
 		break;
 	  }
 	  case '*': {
-		assert(l->is_defined());
-		assert(r->is_defined());
-		long lv = l->as_long();
-		long rv = r->as_long();
-		res = new verinum(lv * rv, l->len());
+		if (l->is_defined() && r->is_defined()) {
+		      long lv = l->as_long();
+		      long rv = r->as_long();
+		      res = new verinum(lv * rv, l->len());
+		} else {
+		      res = new verinum(verinum::Vx, l->len());
+		}
 		break;
 	  }
 	  case '/': {
-		assert(l->is_defined());
-		assert(r->is_defined());
-		long lv = l->as_long();
-		long rv = r->as_long();
-		res = new verinum(lv / rv, l->len());
+		if (l->is_defined() && r->is_defined()) {
+		      long lv = l->as_long();
+		      long rv = r->as_long();
+		      res = new verinum(lv / rv, l->len());
+		} else {
+		      res = new verinum(verinum::Vx, l->len());
+		}
 		break;
 	  }
 	  case '%': {
-		assert(l->is_defined());
-		assert(r->is_defined());
-		long lv = l->as_long();
-		long rv = r->as_long();
-		res = new verinum(lv % rv, l->len());
+		if (l->is_defined() && r->is_defined()) {
+		      long lv = l->as_long();
+		      long rv = r->as_long();
+		      res = new verinum(lv % rv, l->len());
+		} else {
+		      res = new verinum(verinum::Vx, l->len());
+		}
 		break;
 	  }
+	  case 'l': { // left shift (<<)
+		assert(r->is_defined());
+		unsigned long rv = r->as_ulong();
+		res = new verinum(verinum::V0, l->len());
+		if (rv < res->len()) {
+		      unsigned cnt = res->len() - rv;
+		      for (unsigned idx = 0 ;  idx < cnt ;  idx += 1)
+			    res->set(idx+rv, l->get(idx));
+		}
+		break;
+	  }
+	  case 'r': { // right shift (>>)
+		assert(r->is_defined());
+		unsigned long rv = r->as_ulong();
+		res = new verinum(verinum::V0, l->len());
+		if (rv < res->len()) {
+		      unsigned cnt = res->len() - rv;
+		      for (unsigned idx = 0 ;  idx < cnt ;  idx += 1)
+			    res->set(idx, l->get(idx+rv));
+		}
+		break;
+	  }
+
 	  default:
 	    delete l;
 	    delete r;
 	    return 0;
       }
 
+      delete l;
+      delete r;
       return res;
 }
 
+
 /*
  * Evaluate an identifier as a constant expression. This is only
  * possible if the identifier is that of a parameter.
  */
-verinum* PEIdent::eval_const(const Design*des, const string&path) const
+verinum* PEIdent::eval_const(const Design*des, const NetScope*scope) const
 {
-      const NetScope*scope = des->find_scope(path);
       assert(scope);
-      const NetExpr*expr = des->find_parameter(scope, text_);
+      const NetExpr*expr = des->find_parameter(scope, path_);
 
       if (expr == 0)
 	    return 0;
 
-      assert(msb_ == 0);
-
-      if (dynamic_cast<const NetEParam*>(expr)) {
-	    cerr << get_line() << ": sorry: I cannot evaluate ``" <<
-		  text_ << "'' in this context." << endl;
+      const NetEConst*eval = dynamic_cast<const NetEConst*>(expr);
+      if (eval == 0) {
+	    cerr << get_line() << ": internal error: Unable to evaluate "
+		 << "constant expression (parameter=" << path_
+		 << "): " << *expr << endl;
 	    return 0;
       }
 
-      const NetEConst*eval = dynamic_cast<const NetEConst*>(expr);
       assert(eval);
+
+      if (msb_ || lsb_)
+	    return 0;
+
+
       return new verinum(eval->value());
 }
 
-verinum* PENumber::eval_const(const Design*, const string&) const
+verinum* PEFNumber::eval_const(const Design*, const NetScope*) const
+{
+      long val = value_->as_long();
+      return new verinum(val);
+}
+
+verinum* PENumber::eval_const(const Design*, const NetScope*) const
 {
       return new verinum(value());
 }
 
-verinum* PETernary::eval_const(const Design*des, const string&path) const
+verinum* PEString::eval_const(const Design*, const NetScope*) const
 {
-      verinum*test = expr_->eval_const(des, path);
+      return new verinum(string(text_));
+}
+
+verinum* PETernary::eval_const(const Design*des, const NetScope*scope) const
+{
+      verinum*test = expr_->eval_const(des, scope);
       if (test == 0)
 	    return 0;
 
@@ -131,9 +185,9 @@ verinum* PETernary::eval_const(const Design*des, const string&path) const
       delete test;
       switch (bit) {
 	  case verinum::V0:
-	    return fal_->eval_const(des, path);
+	    return fal_->eval_const(des, scope);
 	  case verinum::V1:
-	    return tru_->eval_const(des, path);
+	    return tru_->eval_const(des, scope);
 	  default:
 	    return 0;
 	      // XXXX It is possible to handle this case if both fal_
@@ -141,61 +195,100 @@ verinum* PETernary::eval_const(const Design*des, const string&path) const
       }
 }
 
+verinum* PEUnary::eval_const(const Design*des, const NetScope*scope) const
+{
+      verinum*val = expr_->eval_const(des, scope);
+      if (val == 0)
+	    return 0;
+
+      switch (op_) {
+	  case '+':
+	    return val;
+
+	  case '-': {
+		  /* We need to expand the value a bit if we are
+		     taking the 2's complement so that we are
+		     guaranteed to not overflow. */
+		verinum tmp (0UL, val->len()+1);
+		for (unsigned idx = 0 ;  idx < val->len() ;  idx += 1)
+		      tmp.set(idx, val->get(idx));
+
+		*val = v_not(tmp) + verinum(verinum::V1, 1);
+		val->has_sign(true);
+		return val;
+	  }
+
+      }
+	    delete val;
+      return 0;
+}
+
 
 /*
  * $Log: eval.cc,v $
- * Revision 1.14  2000/03/08 04:36:53  steve
- *  Redesign the implementation of scopes and parameters.
- *  I now generate the scopes and notice the parameters
- *  in a separate pass over the pform. Once the scopes
- *  are generated, I can process overrides and evalutate
- *  paremeters before elaboration begins.
+ * Revision 1.32  2002/10/19 22:59:49  steve
+ *  Redo the parameter vector support to allow
+ *  parameter names in range expressions.
  *
- * Revision 1.13  2000/02/23 02:56:54  steve
- *  Macintosh compilers do not support ident.
+ * Revision 1.31  2002/10/13 05:01:07  steve
+ *  More verbose eval_const assert message.
  *
- * Revision 1.12  1999/11/30 04:48:17  steve
- *  Handle evaluation of ternary during elaboration.
+ * Revision 1.30  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
  *
- * Revision 1.11  1999/11/28 23:42:02  steve
- *  NetESignal object no longer need to be NetNode
- *  objects. Let them keep a pointer to NetNet objects.
+ * Revision 1.29  2002/06/07 02:57:54  steve
+ *  Simply give up on constants with indices.
  *
- * Revision 1.10  1999/11/21 20:03:24  steve
- *  Handle multiply in constant expressions.
+ * Revision 1.28  2002/06/06 18:57:04  steve
+ *  Better error for identifier index eval.
  *
- * Revision 1.9  1999/10/08 17:48:09  steve
- *  Support + in constant expressions.
+ * Revision 1.27  2002/05/23 03:08:51  steve
+ *  Add language support for Verilog-2001 attribute
+ *  syntax. Hook this support into existing $attribute
+ *  handling, and add number and void value types.
  *
- * Revision 1.8  1999/09/20 02:21:10  steve
- *  Elaborate parameters in phases.
+ *  Add to the ivl_target API new functions for access
+ *  of complex attributes attached to gates.
  *
- * Revision 1.7  1999/09/18 01:52:48  steve
- *  Remove spurious message.
+ * Revision 1.26  2001/12/29 22:10:10  steve
+ *  constant eval of arithmetic with x and z.
  *
- * Revision 1.6  1999/09/16 04:18:15  steve
- *  elaborate concatenation repeats.
+ * Revision 1.25  2001/12/29 00:43:55  steve
+ *  Evaluate constant right shifts.
  *
- * Revision 1.5  1999/08/06 04:05:28  steve
- *  Handle scope of parameters.
+ * Revision 1.24  2001/12/03 04:47:15  steve
+ *  Parser and pform use hierarchical names as hname_t
+ *  objects instead of encoded strings.
  *
- * Revision 1.4  1999/07/17 19:51:00  steve
- *  netlist support for ternary operator.
+ * Revision 1.23  2001/11/07 04:01:59  steve
+ *  eval_const uses scope instead of a string path.
  *
- * Revision 1.3  1999/05/30 01:11:46  steve
- *  Exressions are trees that can duplicate, and not DAGS.
+ * Revision 1.22  2001/11/06 06:11:55  steve
+ *  Support more real arithmetic in delay constants.
  *
- * Revision 1.2  1999/05/10 00:16:58  steve
- *  Parse and elaborate the concatenate operator
- *  in structural contexts, Replace vector<PExpr*>
- *  and list<PExpr*> with svector<PExpr*>, evaluate
- *  constant expressions with parameters, handle
- *  memories as lvalues.
+ * Revision 1.21  2001/07/25 03:10:49  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
  *
- *  Parse task declarations, integer types.
+ * Revision 1.20  2001/02/09 02:49:59  steve
+ *  Be more clear about scope of failure.
  *
- * Revision 1.1  1998/11/03 23:28:58  steve
- *  Introduce verilog to CVS.
+ * Revision 1.19  2001/01/27 05:41:48  steve
+ *  Fix sign extension of evaluated constants. (PR#91)
  *
+ * Revision 1.18  2001/01/14 23:04:56  steve
+ *  Generalize the evaluation of floating point delays, and
+ *  get it working with delay assignment statements.
+ *
+ *  Allow parameters to be referenced by hierarchical name.
+ *
+ * Revision 1.17  2001/01/04 04:47:51  steve
+ *  Add support for << is signal indices.
+ *
+ * Revision 1.16  2000/12/10 22:01:36  steve
+ *  Support decimal constants in behavioral delays.
+ *
+ * Revision 1.15  2000/09/07 22:38:13  steve
+ *  Support unary + and - in constants.
  */
 

eval_attrib.cc

@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2002 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: eval_attrib.cc,v 1.5 2002/08/12 01:34:59 steve Exp $"
+#endif
+
+# include  "config.h"
+# include  "util.h"
+# include  "PExpr.h"
+# include  "netlist.h"
+# include  <iostream>
+# include  <assert.h>
+
+/*
+ * The evaluate_attributes function evaluates the attribute
+ * expressions from the map, and resturns a table in a form suitable
+ * for passing to netlist devices.
+ */
+
+attrib_list_t* evaluate_attributes(const map<string,PExpr*>&att,
+				   unsigned&natt,
+				   const Design*des,
+				   const NetScope*scope)
+{
+      natt = att.size();
+      if (natt == 0)
+	    return 0;
+
+      attrib_list_t*table = new attrib_list_t [natt];
+
+      unsigned idx = 0;
+
+      typedef map<string,PExpr*>::const_iterator iter_t;
+      for (iter_t cur = att.begin() ;  cur != att.end() ;  cur ++, idx++) {
+	    table[idx].key = (*cur).first;
+	    PExpr*exp = (*cur).second;
+
+	      /* If the attribute value is given in the source, then
+		 evalulate it as a constant. If the value is not
+		 given, then assume the value is 1. */
+	    verinum*tmp;
+	    if (exp)
+		  tmp = exp->eval_const(des, scope);
+	    else
+		  tmp = new verinum(1);
+
+	    if (tmp == 0)
+		  cerr << "internal error: no result for " << *exp << endl;
+	    assert(tmp);
+
+	    table[idx].val = *tmp;
+	    delete tmp;
+      }
+
+      assert(idx == natt);
+      return table;
+}
+
+/*
+ * $Log: eval_attrib.cc,v $
+ * Revision 1.5  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.4  2002/08/10 21:59:39  steve
+ *  The default attribute value is 1.
+ *
+ * Revision 1.3  2002/06/06 18:57:18  steve
+ *  Use standard name for iostream.
+ *
+ * Revision 1.2  2002/06/03 03:55:14  steve
+ *  compile warnings.
+ *
+ * Revision 1.1  2002/05/23 03:08:51  steve
+ *  Add language support for Verilog-2001 attribute
+ *  syntax. Hook this support into existing $attribute
+ *  handling, and add number and void value types.
+ *
+ *  Add to the ivl_target API new functions for access
+ *  of complex attributes attached to gates.
+ *
+ */
+

eval_rconst.cc

@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2001 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: eval_rconst.cc,v 1.5 2002/08/12 01:34:59 steve Exp $"
+#endif
+
+# include "config.h"
+
+# include  "PExpr.h"
+
+verireal* PExpr::eval_rconst(const Design*, const NetScope*) const
+{
+      return 0;
+}
+
+verireal* PEFNumber::eval_rconst(const Design*, const NetScope*) const
+{
+      verireal*res = new verireal;
+      *res = *value_;
+      return res;
+}
+
+verireal* PENumber::eval_rconst(const Design*, const NetScope*) const
+{
+      verireal*res = new verireal(value_->as_long());
+      return res;
+}
+
+verireal* PEBinary::eval_rconst(const Design*des, const NetScope*scope) const
+{
+      verireal*lef = left_->eval_rconst(des, scope);
+      verireal*rig = right_->eval_rconst(des, scope);
+      verireal*res = 0;
+
+      switch (op_) {
+	  case '*':
+	    if (lef == 0)
+		  break;
+	    if (rig == 0)
+		  break;
+	    res = new verireal;
+	    *res = (*lef) * (*rig);
+	    break;
+
+	  default:
+	    break;
+      }
+
+      delete lef;
+      delete rig;
+      return res;
+}
+
+
+verireal* PEIdent::eval_rconst(const Design*des, const NetScope*scope) const
+{
+      verinum* val = eval_const(des, scope);
+      if (val == 0)
+	    return 0;
+
+      verireal*res = new verireal(val->as_long());
+      delete val;
+      return res;
+}
+
+/*
+ * $Log: eval_rconst.cc,v $
+ * Revision 1.5  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.4  2001/11/07 04:01:59  steve
+ *  eval_const uses scope instead of a string path.
+ *
+ * Revision 1.3  2001/11/06 06:11:55  steve
+ *  Support more real arithmetic in delay constants.
+ *
+ * Revision 1.2  2001/07/25 03:10:49  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
+ * Revision 1.1  2001/01/14 23:04:56  steve
+ *  Generalize the evaluation of floating point delays, and
+ *  get it working with delay assignment statements.
+ *
+ *  Allow parameters to be referenced by hierarchical name.
+ *
+ */
+

examples/.cvsignore

@@ -0,0 +1,3 @@
+,*
+hello_vpi.vpi
+show_vcd.vcd

examples/clbff.v

@@ -23,7 +23,7 @@
  *
  * To compile this for XNF, try a command like this:
  *
- *    iverilog -txnf -fpart=XC4010XLPQ160 -fncf=clbff.ncf -oclbff.xnf clbff.v
+ *    iverilog -txnf -ppart=XC4010XLPQ160 -pncf=clbff.ncf -oclbff.xnf clbff.v
  *
  * That command causes an clbff.xnf and clbff.ncf file to be created.
  * Next, make the clbff.ngd file with the command:
@@ -74,7 +74,7 @@ module main;
       // This is mapped to a DFF. Since Q and D are two bits wide, the
       // code generator actually makes two DFF devices that share a
       // clock input.
-   always @(posedge clk) Q = D;
+   always @(posedge clk) Q <= D;
 
       // These attribute commands assign pins to the listed wires.
       // This can be done to wires and registers, as internally both

examples/hello.vl

@@ -25,15 +25,17 @@
   *
   *  Compile this program with the command:
   *
-  *      verilog hello.vl
+  *      iverilog -ohello hello.vl
   *  
   *  After churning for a little while, the program will create the output
   *  file "hello" which is compiled, linked and ready to run. Run this
   *  program like so:
   *  
-  *      ./hello
+  *      vvp hello
   *  
-  *  and the program will print the message to its output. Easy!
+  *  and the program will print the message to its output. Easy! For
+  *  more on how to make the iverilog command work, see the iverilog
+  *  manual page.
   */
 
 module main();

examples/hello_vpi.c

@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2002 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: hello_vpi.c,v 1.3 2002/08/12 01:35:01 steve Exp $"
+#endif
+
+/*
+ * This file contains an example VPI module to demonstrate the tools
+ * to create vpi modules. To compile this module, use the iverilog-vpi
+ * command like so:
+ *
+ *    iverilog-vpi hello_vpi.c
+ *
+ * The result is the hello_vpi.vpi module. See the hello_vpi.vl
+ * program for example Verilog code to call this module.
+ */
+
+# include  <vpi_user.h>
+
+static int my_hello_calltf(char *xx)
+{
+      vpi_printf("Hello World, from VPI.\n");
+      return 0;
+}
+
+static void my_hello_register()
+{
+      s_vpi_systf_data tf_data;
+
+      tf_data.type      = vpiSysTask;
+      tf_data.tfname    = "$my_hello";
+      tf_data.calltf    = my_hello_calltf;
+      tf_data.compiletf = 0;
+      tf_data.sizetf    = 0;
+      vpi_register_systf(&tf_data);
+
+}
+
+/*
+ * This is a table of register functions. This table is the external
+ * symbol that the simulator looks for when loading this .vpi module.
+ */
+void (*vlog_startup_routines[])() = {
+      my_hello_register,
+      0
+};
+/*
+ * $Log: hello_vpi.c,v $
+ * Revision 1.3  2002/08/12 01:35:01  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.2  2002/08/11 23:47:04  steve
+ *  Add missing Log and Ident strings.
+ *
+ * Revision 1.1  2002/04/18 03:25:16  steve
+ *  More examples.
+ *
+ */
+

examples/hello_vpi.vl

@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2002 Stephen Williams ([email protected])
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+ /*
+  *  Here we have the canonical "Hello, World" program written in Verilog,
+  *  with VPI. It uses the hello_vpi.vpi module that is compiled from
+  *  the hello_vpi.c program also in this directory. See the
+  *  hello_vpi.c for instructions on how to compile it.
+  *
+  *  Compile this program with the command:
+  *
+  *      iverilog -ohello_vpi hello_vpi.vl
+  *  
+  *  After churning for a little while, the program will create the output
+  *  file "hello" which is compiled, linked and ready to run. Run this
+  *  program like so:
+  *  
+  *      vvp -M. -mhello_vpi hello_vpi
+  *  
+  *  and the program will print the message to its output. Easy! For
+  *  more on how to make the iverilog command work, see the iverilog
+  *  manual page.
+  */
+
+module main();
+ 
+initial 
+  begin
+     $my_hello;
+     $finish ;
+  end
+
+endmodule

examples/outff.v

@@ -23,7 +23,7 @@
  *
  * To compile this for XNF, try a command like this:
  *
- *    iverilog -txnf -fpart=XC4010XLPQ160 -ooutff.xnf -fncf=outff.ncf outff.v
+ *    iverilog -txnf -ppart=XC4010XLPQ160 -ooutff.xnf -pncf=outff.ncf outff.v
  *
  * That command causes an outff.xnf and outff.ncf file to be created.
  * Next, make the outff.ngd file with the command:

examples/pal_reg.v

@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2000 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+/*
+ * This example shows how to use Icarus Verilog to generate PLD output.
+ * The design is intended to fit into a 22v10 in a PLCC package, with
+ * pin assignments locked down by design. The command to compile this
+ * into a jedec file is;
+ *
+ *   iverilog -tpal -ppart=generic-22v10-plcc -opal_reg.jed pal_reg.v
+ *
+ * The output file name (passed through the -o<file> switch) can be
+ * any file you desire. If the compilation and fittin all succeed, the
+ * output file will be a JEDEC file that you can take to your favorite
+ * PROM programmer to program the part.
+ *
+ * This source demonstrates some important principles of synthesizing
+ * a design for a PLD, including how to specify synchronous logic, and
+ * how to assign signals to pins. The pin assignment in particular is
+ * part specific, and must be right for the fitting to succeed.
+ */
+
+
+/*
+ * The register module is an 8 bit register that copies the input to
+ * the output registers on the rising edge of the clk input. The
+ * always statement creates a simple d-type flip-flop that is loaded
+ * on the rising edge of the clock.
+ *
+ * The output drivers are controlled by a single active low output
+ * enable. I used bufif0 devices in this example, but the exact same
+ * thing can be achived with a continuous assignment like so:
+ *
+ *   assign out = oe? 8'hzz : Q;
+ *
+ * Many people prefer the expression form. It is true that it does
+ * seem to express the intent a bit more clearly.
+ */
+module register (out, val, clk, oe);
+
+   output [7:0] out;
+   input [7:0] 	val;
+   input 	clk, oe;
+
+   reg [7:0] 	Q;
+
+   wire [7:0] 	out;
+
+   bufif0 drv[7:0](out, Q, oe);
+
+   always @(posedge clk) Q = val;
+
+endmodule
+
+
+/*
+ * The module pal is used to attach pin information to all the pins of
+ * the device. We use this to lock down the pin assignments of the
+ * synthesized result. The pin number assignments are for a 22v10 in
+ * a PLCC package.
+ *
+ * Note that this module has no logic in it. It is a convention I use
+ * that I put all the functionality in a seperate module (seen above)
+ * and isolate the Icarus Verilog specific $attribute madness into a
+ * top-level module. The advantage of this style is that the entire
+ * module can be `ifdef'ed out when doing simulation and you don't
+ * need to worry that functionality will be affected.
+ */
+module pal;
+
+   wire out7, out6, out5, out4, out3, out2, out1, out0;
+   wire inp7, inp6, inp5, inp4, inp3, inp2, inp1, inp0;
+   wire clk, oe;
+
+   // The PAD attributes attach the wires to pins of the
+   // device. Output pins are prefixed by a 'o', and input pins by an
+   // 'i'. If not all the available output pins are used, then the
+   // remaining are available for the synthesizer to drop internal
+   // registers or extra logic layers.
+   $attribute(out7, "PAD", "o27");
+   $attribute(out6, "PAD", "o26");
+   $attribute(out5, "PAD", "o25");
+   $attribute(out4, "PAD", "o24");
+   $attribute(out3, "PAD", "o23");
+   $attribute(out2, "PAD", "o21");
+   $attribute(out1, "PAD", "o20");
+   $attribute(out0, "PAD", "o19");
+
+   $attribute(inp7, "PAD", "i10");
+   $attribute(inp6, "PAD", "i9");
+   $attribute(inp5, "PAD", "i7");
+   $attribute(inp4, "PAD", "i6");
+   $attribute(inp3, "PAD", "i5");
+   $attribute(inp2, "PAD", "i4");
+   $attribute(inp1, "PAD", "i3");
+   $attribute(inp0, "PAD", "i2");
+
+   //$attribute(clk, "PAD", "CLK");
+   $attribute(oe,  "PAD", "i13");
+
+   register dev({out7, out6, out5, out4, out3, out2, out1, out0},
+		{inp7, inp6, inp5, inp4, inp3, inp2, inp1, inp0},
+		clk, oe);
+
+endmodule // pal

examples/show_vcd.vl

@@ -24,7 +24,7 @@
   *  Like any other Verilog simulation, compile this program with the
   *  command:
   *  
-  *      verilog show_vcd.vl
+  *      iverilog show_vcd.vl
   *  
   *  This will generate the show_vcd command in the current directory.
   *  When you run the command, you will see the output from all the
@@ -41,7 +41,7 @@
   *  To view the output generated by running show_vcd, start the GTKWave
   *  viewer with the command:
   *  
-  *      wave show_vcd.vcd
+  *      gtkwave show_vcd.vcd
   *  
   *  The GTKWave program will display its main window, and show in a small
   *  status box (upper left corner) that it succeeded in loading the dump

examples/sqrt-virtex.v

@@ -0,0 +1,377 @@
+/*
+ * Copyright (c) 2002 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ *
+ *   $Id: sqrt-virtex.v,v 1.2 2002/11/13 01:49:43 steve Exp $"
+ */
+
+/*
+ * This module is a synthesizeable square-root function. It is also a
+ * detailed example of how to target Xilinx Virtex parts using
+ * Icarus Verilog. In fact, for no particular reason other then to
+ * be excessively specific, I will step through the process of
+ * generating a design for a Spartan-II XC2S15-VQ100, and also how to
+ * generate a generic library part for larger Virtex designs.
+ *
+ * In addition to Icarus Verilog, you will need implementation
+ * software from Xilinx. As of this writing, this example was tested
+ * with Foundation 4.2i, but it should work the same with ISE and
+ * Webpack software.
+ *
+ * This example source contains all the Verilog needed to do
+ * everything described below. We use conditional compilation to
+ * select the bits of Verilog that are needed to perform each specific
+ * task.
+ *
+ * SIMULATE THE DESIGN
+ *
+ * This source file includes a simulation test bench. To compile the
+ * program to include this test bench, use the command line:
+ *
+ *    iverilog -DSIMULATE=1 -oa.out sqrt-virtex.v
+ *
+ * This generates the file "a.out" that can then be executed with the
+ * command:
+ *
+ *    vvp a.out
+ *
+ * This causes the simulation to run a long set of example sqrt
+ * calculations. Each result is checked by the test bench to assure
+ * that the result is valid. When it is done, the program prints
+ * "PASSED" and finishes the simulation.
+ *
+ * When you take a close look at the "main" module below, you will see
+ * that it uses Verilog constructs that are not synthesizeable. This
+ * is fine, as we will never try to synthesize it.
+ *
+ * LIBRARY PARTS
+ *
+ * One can use the sqrt32 module to generate an EDIF file suitable for
+ * use as a library part. This part can be imported to the Xilinx
+ * schematic editor, then placed like any other pre-existing
+ * macro. One can also pass the generated EDIF as a precompiled macro
+ * that other designers may use as they see fit.
+ *
+ * To make an EDIF file from the sqrt32 module, execute the command:
+ *
+ *    iverilog -osqrt32.edf -tfpga -parch=virtex sqrt-virtex.v
+ *
+ * The -parch=virtex tells the code generator to generate code for the
+ * virtex architecture family (we don't yet care what specific part)
+ * and the -osqrt32.edf places the output into the file
+ * sqrt32.edf.
+ *
+ * Without any preprocessor directives, the only module is the sqrt32
+ * module, so sqrt32 is compiled as the root. The ports of the module
+ * are automatically made into ports of the sqrt32.edf netlist, and
+ * the contents of the sqrt32 module are connected approprately.
+ *
+ * COMPLETE CHIP DESIGNS
+ *
+ * To make a complete chip design, there are other bits that need to
+ * be accounted for. Signals must be assigned to pins, and some
+ * special devices may need to be created. We also want to write into
+ * the EDIF file complete part information so that the implementation
+ * tools know how to route the complete design. The command to compile
+ * for our target part is:
+ *
+ *    iverilog -ochip.edf -tfpga \
+ *           -parch=virtex -ppart=XC2S15-VQ100 \
+ *           -DMAKE_CHIP=1 sqrt-virtex.v
+ *
+ * This command uses the "chip" module as the root. This module in
+ * turn has ports that are destined to be the pins of the completed
+ * part. The -ppart= option gives complete part information, that is
+ * in turn written into the EDIF file. This saves us the drudgery of
+ * repeating that part number for later commands.
+ *
+ * The next steps involve Xilinx software, and to talk to Xilinx
+ * software, the netlist must be in the form of an "ngd" file, a
+ * binary netlist format. The command:
+ *
+ *    ngdbuild chip.edf chip.ngd
+ *
+ * does the trick. The input to ngdbuild is the chip.edf file created
+ * by Icarus Verilog, and the output is the chip.ngd file that the
+ * implementation tools may read. From this point, it is best to refer
+ * to Xilinx documentation for the software you are using, but the
+ * quick summary is:
+ *
+ *    map -o map.ncd chip.ngd
+ *    par -w map.ncd chip.ncd
+ *
+ * The result of this sequence of commands is the chip.ncd file that
+ * is ready to be viewed by FPGA Edit, or converted to a bit stream,
+ * or whatever.
+ *
+ * POST MAP SIMULATION
+ *
+ * Warm fuzzies are good, and retesting your design after the part
+ * is mapped by the Xilinx backend tools is a cheap source of fuzzies.
+ * The command to make a Verilog file out of the mapped design is:
+ *
+ *    ngd2ver chip.ngd chip_root.v
+ *
+ * This command creates from the chip.ngd the file "chip_root.v" that
+ * contains Verilog code that simulates the mapped design. This output
+ * Verilog has the single root module "chip_root", which came from the
+ * name of the root module when we were making hte EDIF file in the
+ * first place. The module has ports named just line the ports of the
+ * chip_root module below.
+ *
+ * The generated Verilog uses the library in the directory
+ * $(XILINX)/verilog/src/simprims. This directory comes with the ISE
+ * WebPACK installation that you are using. Icarus Verilog is able to
+ * simulate using that library.
+ *
+ * To compile a post-map simulation of the chip_root.v, use the
+ * command:
+ *
+ *    iverilog -DSIMULATE -DPOST_MAP -ob.out \
+ *             -y $(XILINX)/verilog/src/simprims \
+ *             sqrt-virtex.v chip_root.v \
+ *             $(XILINX)/verilog/src/glbl.v
+ *
+ * This command line generates b.out from the source files
+ * sqrt-virtex.v and chip_root.v (the latter from ngd2ver)
+ * and the "-y <path>" flag specifies the library directory that will
+ * be needed. The glbl.v source file is also included to provide the
+ * GSR and related signals.
+ *
+ * The POST_MAP compiler directive causes the GSR manipulations
+ * included in the test bench to be compiled in, to simulate the chip
+ * startup. Other then that, the test bench runs the post-map design
+ * the same way the pre-synthesis design works.
+ *
+ * Run this design with the command:
+ *
+ *    vvp b.out
+ *
+ * And there you go.
+ */
+
+`ifndef POST_MAP
+ /*
+  * This module approximates the square root of an unsigned 32bit
+  * number. The algorithm works by doing a bit-wise binary search.
+  * Starting from the most significant bit, the accumulated value
+  * tries to put a 1 in the bit position. If that makes the square
+  * too big for the input, the bit is left zero, otherwise it is set
+  * in the result. This continues for each bit, decreasing in
+  * significance, until all the bits are calculated or all the
+  * remaining bits are zero.
+  *
+  * Since the result is an integer, this function really calculates
+  * value of the expression:
+  *
+  *      x = floor(sqrt(y))
+  *
+  * where sqrt(y) is the exact square root of y and floor(N) is the
+  * largest integer <= N.
+  *
+  * For 32bit numbers, this will never run more then 16 iterations,
+  * which amounts to 16 clocks.
+  */
+
+module sqrt32(clk, rdy, reset, x, .y(acc));
+   input  clk;
+   output rdy;
+   input  reset;
+
+   input [31:0] x;
+   output [15:0] acc;
+
+
+   // acc holds the accumulated result, and acc2 is the accumulated
+   // square of the accumulated result.
+   reg [15:0] acc;
+   reg [31:0] acc2;
+
+   // Keep track of which bit I'm working on.
+   reg [4:0]  bitl;
+   wire [15:0] bit = 1 << bitl;
+   wire [31:0] bit2 = 1 << (bitl << 1);
+
+   // The output is ready when the bitl counter underflows.
+   wire rdy = bitl[4];
+
+   // guess holds the potential next values for acc, and guess2 holds
+   // the square of that guess. The guess2 calculation is a little bit
+   // subtle. The idea is that:
+   //
+   //      guess2 = (acc + bit) * (acc + bit)
+   //             = (acc * acc) + 2*acc*bit + bit*bit
+   //             = acc2 + 2*acc*bit + bit2
+   //             = acc2 + 2 * (acc<<bitl) + bit
+   //
+   // This works out using shifts because bit and bit2 are known to
+   // have only a single bit in them.
+   wire [15:0] guess  = acc | bit;
+   wire [31:0] guess2 = acc2 + bit2 + ((acc << bitl) << 1);
+
+   (* ivl_synthesis_on *)
+   always @(posedge clk or posedge reset)
+      if (reset) begin
+	 acc = 0;
+	 acc2 = 0;
+	 bitl = 15;
+      end else begin
+	 if (guess2 <= x) begin
+	    acc  <= guess;
+	    acc2 <= guess2;
+	 end
+	 bitl <= bitl - 5'd1;
+      end
+
+endmodule // sqrt32
+
+`endif //  `ifndef POST_MAP
+
+`ifdef SIMULATE
+ /*
+  * This module is a test bench for the sqrt32 module. It runs some
+  * test input values through the sqrt32 module, and checks that the
+  * output is valid. If an invalid output is generated, print and
+  * error message and stop immediately. If all the tested values pass,
+  * then print PASSED after the test is complete.
+  */
+module main;
+
+   reg [31:0] x;
+   reg 	      clk, reset;
+
+   wire [15:0] y;
+   wire        rdy;
+
+`ifdef POST_MAP
+   chip_root dut(.clk(clk), .reset(reset), .rdy(rdy), .x(x), .y(y));
+`else
+   sqrt32 dut(.clk(clk), .reset(reset), .rdy(rdy), .x(x), .y(y));
+`endif
+
+   (* ivl_synthesis_off *)
+   always #5 clk = !clk;
+
+   task reset_dut;
+      begin
+	 reset = 1;
+	 #1 reset = 0;
+	 @(negedge clk) ;
+      end
+   endtask // reset_dut
+
+   task crank_dut;
+      begin
+	 while (rdy == 0) begin
+	    @(posedge clk) /* wait */;
+	 end
+      end
+   endtask // crank_dut
+
+`ifdef POST_MAP
+   reg        GSR;
+   assign      glbl.GSR = GSR;
+`endif
+
+   integer idx;
+
+   (* ivl_synthesis_off *)
+   initial begin
+      reset = 0;
+      clk = 0;
+
+      /* If doing a post-map simulation, when we need to wiggle
+         The GSR bit to simulate chip power-up. */
+`ifdef POST_MAP
+      GSR = 1;
+      #100 GSR = 0;
+`endif
+      #100 x = 1;
+      reset_dut;
+      crank_dut;
+      $display("x=%d, y=%d", x, y);
+
+      x = 3;
+      reset_dut;
+      crank_dut;
+      $display("x=%d, y=%d", x, y);
+
+      x = 4;
+      reset_dut;
+      crank_dut;
+      $display("x=%d, y=%d", x, y);
+
+      for (idx = 0 ;  idx < 200 ;  idx = idx + 1) begin
+	 x = $random;
+	 reset_dut;
+	 crank_dut;
+	 $display("x=%d, y=%d", x, y);
+
+	 if (x < (y * y)) begin
+	    $display("ERROR: y is too big");
+	    $finish;
+	 end
+
+	 if (x > ((y + 1)*(y + 1))) begin
+	    $display("ERROR: y is too small");
+	    $finish;
+	 end
+      end
+
+      $display("PASSED");
+      $finish;
+   end
+
+endmodule // main
+`endif
+
+`ifdef MAKE_CHIP
+ /*
+  * This module represents the chip packaging that we intend to
+  * generate. We bind pins here, and route the clock to the global
+  * clock buffer.
+  */
+module chip_root(clk, rdy, reset, x, y);
+   input  clk;
+   output rdy;
+   input  reset;
+
+   input [31:0] x;
+   output [15:0] y;
+
+   wire 	 clk_int;
+
+   (* cellref="BUFG:O,I" *)
+   buf gbuf (clk_int, clk);
+
+   sqrt32 dut(.clk(clk_int), .reset(reset), .rdy(rdy), .x(x), .y(y));
+
+   /* Assign the clk to GCLK0, which is on pin P39. */
+   $attribute(clk, "PAD", "39");
+
+   // We don't care where the remaining pins go, so set the pin number
+   // to 0. This tells the implementation tools that we want a PAD,
+   // but we don't care which. Also note the use of a comma (,)
+   // separated list to assign pins to the bits of a vector.
+   $attribute(rdy, "PAD", "0");
+   $attribute(reset, "PAD", "0");
+   $attribute(x, "PAD", "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0");
+   $attribute(y, "PAD", "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0");
+
+endmodule // chip_root
+
+`endif

examples/sqrt.vl

@@ -16,9 +16,22 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  *
- *   $Id: sqrt.vl,v 1.1 1999/12/05 21:08:56 steve Exp $"
+ *   $Id: sqrt.vl,v 1.3 2000/11/04 01:53:24 steve Exp $"
  */
 
+ /*
+  * This example shows that Icarus Verilog can run non-trivial
+  * programs, too. This uses a variety of Verilog language features
+  * to implement the module of a square-root device. The program
+  * uses IEEE1364-1995 language features and should work correctly
+  * on any Verilog compiler.
+  *
+  * Run the file with Icarus Verilog under UNIX using the command:
+  *
+  *     % iverilog -osqrt sqrt.v
+  *     % ./sqrt
+  */
+
  /*
   * This module approximates the square root of an unsigned 32bit
   * number. The algorithm works by doing a bit-wise binary search.
@@ -120,7 +133,7 @@ module main;
    initial begin
       clk = 0;
       reset = 1;
-      $monitor($time,,"%m = %b", root.acc, root.acc);
+      $monitor($time,,"%m.acc = %b", root.acc);
       #100 value = 63;
       reset = 0;
    end

examples/xnf_add.vl

@@ -25,10 +25,11 @@
  *
  * To compile this for XNF, try a command like this:
  *
- *    iverilog -txnf -fpart=XC4010XLPQ160 -fncf=xnf_add.ncf -oxnf_add.xnf xnf_add.v
+ *    iverilog -txnf -ppart=XC4010XLPQ160 -pncf=xnf_add.ncf -oxnf_add.xnf xnf_add.v
  *
  * That command causes an xnf_add.xnf and xnf_add.ncf file to be created.
- * Next, make the xnf_add.ngd file with the command:
+ * Next, Use Xilinx Alliance or Foundation tools to make the xnf_add.ngd
+ * file with the command:
  *
  *    xnf2ngd -l xilinxun -u xnf_add.xnf xnf_add.ngo
  *    ngdbuild xnf_add.ngo xnf_add.ngd
@@ -40,8 +41,8 @@
  *    map -o map.ncd xnf_add.ngd
  *    par -w map.ncd xnf_add.ncd
  *
- * At this point, you can use the FPGA Editor to edit the xnf_add.ncd
- * file to see the carry chains made up to support the adder.
+ * At this point, you can use the Xilinx FPGA Editor to edit the xnf_add.ncd
+ * file and see the carry chains made up to support the adder.
  */
 
 module main;

examples/xram16x1.v

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 1999 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+// This example describes a 16x1 RAM that can be synthesized into
+// a CLB ram in a Xilinx FPGA.
+
+module ram16x1 (q, d, a, we, wclk);
+   output q;
+   input d;
+   input [3:0] a;
+   input we;
+   input wclk;
+
+   reg mem[15:0];
+   
+   assign q = mem[a];
+   always @(posedge wclk) if (we) mem[a] = d;
+
+endmodule /* ram16x1 */
+
+module main;
+   wire q;
+   reg d;
+   reg [3:0] a;
+   reg we, wclk;
+    
+   ram16x1 r1 (q, d, a, we, wclk);
+
+   initial begin
+      $monitor("q = %b", q);
+      d = 0;
+      wclk = 0;
+      a = 5;
+      we = 1;
+      #1 wclk = 1;
+      #1 wclk = 0;
+   end
+endmodule /* main */

expr_synth.cc

@@ -16,12 +16,16 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: expr_synth.cc,v 1.14 2000/05/02 00:58:12 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: expr_synth.cc,v 1.37 2002/11/17 23:37:55 steve Exp $"
 #endif
 
-# include  "netlist.h"
+# include "config.h"
 
+# include  <iostream>
+
+# include  "netlist.h"
+# include  "netmisc.h"
 
 NetNet* NetExpr::synthesize(Design*des)
 {
@@ -38,17 +42,18 @@ NetNet* NetEBAdd::synthesize(Design*des)
 {
       assert((op()=='+') || (op()=='-'));
 
-      string path = des->local_symbol("SYNTH");
       NetNet*lsig = left_->synthesize(des);
       NetNet*rsig = right_->synthesize(des);
       
       assert(lsig->pin_count() == rsig->pin_count());
       unsigned width=lsig->pin_count();
 
+      string path = lsig->scope()->name()+"."+lsig->scope()->local_symbol();
       NetNet*osig = new NetNet(lsig->scope(), path, NetNet::IMPLICIT, width);
+      osig->local_flag(true);
 
       string oname = des->local_symbol(path);
-      NetAddSub *adder = new NetAddSub(oname, width);
+      NetAddSub *adder = new NetAddSub(lsig->scope(), oname, width);
       for (unsigned idx = 0 ;  idx < width;  idx += 1) {
 	    connect(lsig->pin(idx), adder->pin_DataA(idx));
 	    connect(rsig->pin(idx), adder->pin_DataB(idx));
@@ -58,10 +63,10 @@ NetNet* NetEBAdd::synthesize(Design*des)
 
       switch (op()) {
 	  case '+':
-	    adder->attribute("LPM_Direction", "ADD");
+	    adder->attribute("LPM_Direction", verinum("ADD"));
 	    break;
 	  case '-':
-	    adder->attribute("LPM_Direction", "SUB");
+	    adder->attribute("LPM_Direction", verinum("SUB"));
 	    break;
       }
 
@@ -76,12 +81,26 @@ NetNet* NetEBAdd::synthesize(Design*des)
  */
 NetNet* NetEBBits::synthesize(Design*des)
 {
-      string path = des->local_symbol("SYNTH");
       NetNet*lsig = left_->synthesize(des);
       NetNet*rsig = right_->synthesize(des);
 
+      NetScope*scope = lsig->scope();
+      assert(scope);
+      string path = des->local_symbol(scope->name());
+
+      if (lsig->pin_count() != rsig->pin_count()) {
+	    cerr << get_line() << ": internal error: bitwise (" << op_
+		 << ") widths do not match: " << lsig->pin_count()
+		 << " != " << rsig->pin_count() << endl;
+	    cerr << get_line() << ":               : width="
+		 << lsig->pin_count() << ": " << *left_ << endl;
+	    cerr << get_line() << ":               : width="
+		 << rsig->pin_count() << ": " << *right_ << endl;
+	    return 0;
+      }
+
       assert(lsig->pin_count() == rsig->pin_count());
-      NetNet*osig = new NetNet(lsig->scope(), path, NetNet::IMPLICIT,
+      NetNet*osig = new NetNet(scope, path, NetNet::IMPLICIT,
 			       lsig->pin_count());
       osig->local_flag(true);
 
@@ -89,21 +108,41 @@ NetNet* NetEBBits::synthesize(Design*des)
 	    string oname = des->local_symbol(path);
 	    NetLogic*gate;
 
+	      /* If the rsig bit is constant, then look for special
+		 cases that I can use to reduce the generated
+		 logic. If I find one, then handle it immediately and
+		 skip the rest of the processing of this bit. */
+	    if (rsig->pin(idx).nexus()->drivers_constant()) {
+		  verinum::V bval = rsig->pin(idx).nexus()->driven_value();
+
+		    /* (A & 0) is (0) */
+		  if ((op() == '&') && bval == verinum::V0) {
+			connect(osig->pin(idx), rsig->pin(idx));
+			continue;
+		  }
+
+		    /* (A & 1) is A */
+		  if ((op() == '&') && bval == verinum::V1) {
+			connect(osig->pin(idx), lsig->pin(idx));
+			continue;
+		  }
+	    }
+
 	    switch (op()) {
 		case '&':
-		  gate = new NetLogic(oname, 3, NetLogic::AND);
+		  gate = new NetLogic(scope, oname, 3, NetLogic::AND);
 		  break;
 		case '|':
-		  gate = new NetLogic(oname, 3, NetLogic::OR);
+		  gate = new NetLogic(scope, oname, 3, NetLogic::OR);
 		  break;
 		case '^':
-		  gate = new NetLogic(oname, 3, NetLogic::XOR);
+		  gate = new NetLogic(scope, oname, 3, NetLogic::XOR);
 		  break;
 		case 'O':
-		  gate = new NetLogic(oname, 3, NetLogic::NOR);
+		  gate = new NetLogic(scope, oname, 3, NetLogic::NOR);
 		  break;
 		case 'X':
-		  gate = new NetLogic(oname, 3, NetLogic::XNOR);
+		  gate = new NetLogic(scope, oname, 3, NetLogic::XNOR);
 		  break;
 		default:
 		  assert(0);
@@ -121,21 +160,98 @@ NetNet* NetEBBits::synthesize(Design*des)
 
 NetNet* NetEBComp::synthesize(Design*des)
 {
-      string path = des->local_symbol("SYNTH");
+      NetEConst*lcon = reinterpret_cast<NetEConst*>(left_);
+      NetEConst*rcon = reinterpret_cast<NetEConst*>(right_);
+
+	/* Handle the special case where one of the inputs is constant
+	   0. We can use an OR gate to do the comparison. Synthesize
+	   the non-const side as normal, then or(nor) the signals
+	   together to get result. */
+      if ((rcon && (rcon->value() == verinum(0UL,rcon->expr_width())))
+	  || (lcon && (lcon->value() == verinum(0UL,lcon->expr_width())))) {
+
+	    NetNet*lsig = rcon
+		  ? left_->synthesize(des)
+		  : right_->synthesize(des);
+	    NetScope*scope = lsig->scope();
+	    assert(scope);
+	    string path = des->local_symbol(scope->name());
+
+	    NetNet*osig = new NetNet(scope, path, NetNet::IMPLICIT, 1);
+	    osig->local_flag(true);
+
+	    NetLogic*gate;
+	    switch (op_) {
+		case 'e':
+		case 'E':
+		  gate = new NetLogic(scope, des->local_symbol(path),
+				      lsig->pin_count()+1, NetLogic::NOR);
+		  break;
+		case 'n':
+		case 'N':
+		  gate = new NetLogic(scope, des->local_symbol(path),
+				      lsig->pin_count()+1, NetLogic::OR);
+		  break;
+
+		case '>':
+		    /* sig > 0 is true if any bit in sig is set. This
+		       is very much like sig != 0. (0 > sig) shouldn't
+		       happen. */
+		  if (rcon) {
+			gate = new NetLogic(scope, des->local_symbol(path),
+					    lsig->pin_count()+1, NetLogic::OR);
+		  } else {
+			assert(0);
+			gate = new NetLogic(scope, des->local_symbol(path),
+				      lsig->pin_count()+1, NetLogic::NOR);
+		  }
+		  break;
+
+		case '<':
+		    /* 0 < sig is handled like sig > 0. */
+		  if (! rcon) {
+			gate = new NetLogic(scope, des->local_symbol(path),
+					    lsig->pin_count()+1, NetLogic::OR);
+		  } else {
+			assert(0);
+			gate = new NetLogic(scope, des->local_symbol(path),
+				      lsig->pin_count()+1, NetLogic::NOR);
+		  }
+		  break;
+
+		default:
+		  assert(0);
+	    }
+
+	    connect(gate->pin(0), osig->pin(0));
+	    for (unsigned idx = 0 ;  idx < lsig->pin_count() ;  idx += 1)
+		  connect(gate->pin(idx+1), lsig->pin(idx));
+
+	    des->add_node(gate);
+	    return osig;
+      }
+
       NetNet*lsig = left_->synthesize(des);
       NetNet*rsig = right_->synthesize(des);
 
+      NetScope*scope = lsig->scope();
+      assert(scope);
+      string path = des->local_symbol(scope->name());
+
       unsigned width = lsig->pin_count();
       if (rsig->pin_count() > lsig->pin_count())
 	    width = rsig->pin_count();
 
-      NetNet*osig = new NetNet(lsig->scope(), path, NetNet::IMPLICIT, 1);
+      lsig = pad_to_width(des, lsig, width);
+      rsig = pad_to_width(des, rsig, width);
+
+      NetNet*osig = new NetNet(scope, path, NetNet::IMPLICIT, 1);
       osig->local_flag(true);
 
 	/* Handle the special case of a single bit equality
 	   operation. Make an XNOR gate instead of a comparator. */
       if ((width == 1) && ((op_ == 'e') || (op_ == 'E'))) {
-	    NetLogic*gate = new NetLogic(des->local_symbol(path),
+	    NetLogic*gate = new NetLogic(scope, des->local_symbol(path),
 					 3, NetLogic::XNOR);
 	    connect(gate->pin(0), osig->pin(0));
 	    connect(gate->pin(1), lsig->pin(0));
@@ -148,7 +264,7 @@ NetNet* NetEBComp::synthesize(Design*des)
 	   operation. This is similar to single bit equality, but uses
 	   an XOR instead of an XNOR gate. */
       if ((width == 1) && ((op_ == 'n') || (op_ == 'N'))) {
-	    NetLogic*gate = new NetLogic(des->local_symbol(path),
+	    NetLogic*gate = new NetLogic(scope, des->local_symbol(path),
 					 3, NetLogic::XOR);
 	    connect(gate->pin(0), osig->pin(0));
 	    connect(gate->pin(1), lsig->pin(0));
@@ -158,7 +274,7 @@ NetNet* NetEBComp::synthesize(Design*des)
       }
 
 
-      NetCompare*dev = new NetCompare(des->local_symbol(path), width);
+      NetCompare*dev = new NetCompare(scope, des->local_symbol(path), width);
       des->add_node(dev);
 
       for (unsigned idx = 0 ;  idx < lsig->pin_count() ;  idx += 1)
@@ -208,29 +324,113 @@ NetNet* NetEBDiv::synthesize(Design*des)
       return 0;
 }
 
+NetNet* NetEBLogic::synthesize(Design*des)
+{
+      NetNet*lsig = left_->synthesize(des);
+      NetNet*rsig = right_->synthesize(des);
+
+      if (lsig == 0)
+	    return 0;
+
+      if (rsig == 0)
+	    return 0;
+
+      NetScope*scope = lsig->scope();
+      assert(scope);
+      string path = des->local_symbol(scope->name());
+
+      NetNet*osig = new NetNet(scope, path, NetNet::IMPLICIT, 1);
+      osig->local_flag(true);
+
+
+      if (op() == 'o') {
+
+	      /* Logic OR can handle the reduction *and* the logical
+		 comparison with a single wide OR gate. So handle this
+		 magically. */
+
+	    string oname = des->local_symbol(path);
+	    NetLogic*olog;
+
+	    olog = new NetLogic(scope, oname,
+				lsig->pin_count()+rsig->pin_count()+1,
+				NetLogic::OR);
+
+	    connect(osig->pin(0), olog->pin(0));
+
+	    unsigned pin = 1;
+	    for (unsigned idx = 0 ;  idx < lsig->pin_count() ;  idx = 1)
+		  connect(olog->pin(pin+idx), lsig->pin(idx));
+
+	    pin += lsig->pin_count();
+	    for (unsigned idx = 0 ;  idx < rsig->pin_count() ;  idx = 1)
+		  connect(olog->pin(pin+idx), rsig->pin(idx));
+
+	    des->add_node(olog);
+
+      } else {
+	    assert(op() == 'a');
+
+	      /* Create the logic AND gate. This is a single bit
+		 output, with inputs for each of the operands. */
+	    NetLogic*olog;
+	    string oname = des->local_symbol(path);
+
+	    olog = new NetLogic(scope, oname, 3, NetLogic::AND);
+
+	    connect(osig->pin(0), olog->pin(0));
+	    des->add_node(olog);
+
+	      /* XXXX Here, I need to reduce the parameters with
+		 reduction or. */
+
+
+	      /* By this point, the left and right parameters have been
+		 reduced to single bit values. Now we just connect them to
+		 the logic gate. */
+	    assert(lsig->pin_count() == 1);
+	    connect(lsig->pin(0), olog->pin(1));
+
+	    assert(rsig->pin_count() == 1);
+	    connect(lsig->pin(0), olog->pin(2));
+      }
+
+
+      return osig;
+}
+
 NetNet* NetEConcat::synthesize(Design*des)
 {
-      NetScope*scope = des->find_root_scope();
-      assert(scope);
-      assert(repeat_ == 1);
+	/* First, synthesize the operands. */
+      NetNet**tmp = new NetNet*[parms_.count()];
+      for (unsigned idx = 0 ;  idx < parms_.count() ;  idx += 1)
+	    tmp[idx] = parms_[idx]->synthesize(des);
 
-      string path = des->local_symbol("SYNTH");
+      assert(tmp[0]);
+      NetScope*scope = tmp[0]->scope();
+      assert(scope);
+
+	/* Make a NetNet object to carry the output vector. */
+      string path = scope->name() + "." + scope->local_symbol();
       NetNet*osig = new NetNet(scope, path, NetNet::IMPLICIT, expr_width());
       osig->local_flag(true);
 
+	/* Connect the output vector to the operands. */
       unsigned obit = 0;
       for (unsigned idx = parms_.count() ;  idx > 0 ;  idx -= 1) {
-	    NetNet*tmp = parms_[idx-1]->synthesize(des);
 
-	    for (unsigned bit = 0 ;  bit < tmp->pin_count() ;  bit += 1) {
-		  connect(osig->pin(obit), tmp->pin(bit));
+	    assert(tmp[idx-1]);
+
+	    for (unsigned bit = 0;  bit < tmp[idx-1]->pin_count(); bit += 1) {
+		  connect(osig->pin(obit), tmp[idx-1]->pin(bit));
 		  obit += 1;
 	    }
 
-	    if (tmp->local_flag())
-		  delete tmp;
+	    if (tmp[idx-1]->local_flag() && tmp[idx-1]->get_refs() == 0)
+		  delete tmp[idx-1];
       }
 
+      delete[]tmp;
       return osig;
 }
 
@@ -239,12 +439,12 @@ NetNet* NetEConst::synthesize(Design*des)
       NetScope*scope = des->find_root_scope();
       assert(scope);
 
-      string path = des->local_symbol("SYNTH");
+      string path = scope->name() + "." + scope->local_symbol();
       unsigned width=expr_width();
 
       NetNet*osig = new NetNet(scope, path, NetNet::IMPLICIT, width);
       osig->local_flag(true);
-      NetConst*con = new NetConst(des->local_symbol(path), value());
+      NetConst*con = new NetConst(scope, des->local_symbol(path), value());
       for (unsigned idx = 0 ;  idx < width;  idx += 1)
 	    connect(osig->pin(idx), con->pin(idx));
 
@@ -258,10 +458,13 @@ NetNet* NetEConst::synthesize(Design*des)
  */
 NetNet* NetEUBits::synthesize(Design*des)
 {
-      string path = des->local_symbol("SYNTH");
       NetNet*isig = expr_->synthesize(des);
 
-      NetNet*osig = new NetNet(isig->scope(), path, NetNet::IMPLICIT,
+      NetScope*scope = isig->scope();
+      assert(scope);
+      string path = des->local_symbol(scope->name());
+
+      NetNet*osig = new NetNet(scope, path, NetNet::IMPLICIT,
 			       isig->pin_count());
       osig->local_flag(true);
 
@@ -271,7 +474,7 @@ NetNet* NetEUBits::synthesize(Design*des)
 
 	    switch (op()) {
 		case '~':
-		  gate = new NetLogic(oname, 2, NetLogic::NOT);
+		  gate = new NetLogic(scope, oname, 2, NetLogic::NOT);
 		  break;
 		default:
 		  assert(0);
@@ -286,14 +489,80 @@ NetNet* NetEUBits::synthesize(Design*des)
       return osig;
 }
 
+NetNet* NetEUReduce::synthesize(Design*des)
+{
+      NetNet*isig = expr_->synthesize(des);
 
+      NetScope*scope = isig->scope();
+      assert(scope);
+      string path = des->local_symbol(scope->name());
+
+      NetNet*osig = new NetNet(scope, path, NetNet::IMPLICIT, 1);
+      osig->local_flag(true);
+
+      string oname = des->local_symbol(path);
+      NetLogic*gate;
+
+      switch (op()) {
+	  case 'N':
+	  case '!':
+	    gate = new NetLogic(scope, oname, isig->pin_count()+1,
+				NetLogic::NOR);
+	    break;
+
+	  case '&':
+	    gate = new NetLogic(scope, oname, isig->pin_count()+1,
+				NetLogic::AND);
+	    break;
+
+	  case '|':
+	    gate = new NetLogic(scope, oname, isig->pin_count()+1,
+				NetLogic::OR);
+	    break;
+
+	  case '^':
+	    gate = new NetLogic(scope, oname, isig->pin_count()+1,
+				NetLogic::XOR);
+	    break;
+
+	  case 'A':
+	    gate = new NetLogic(scope, oname, isig->pin_count()+1,
+				NetLogic::NAND);
+	    break;
+
+	  case 'X':
+	    gate = new NetLogic(scope, oname, isig->pin_count()+1,
+				NetLogic::XNOR);
+	    break;
+
+	  default:
+	    cerr << get_line() << ": internal error: "
+		 << "Unable to synthesize " << *this << "." << endl;
+	    return 0;
+      }
+
+      des->add_node(gate);
+      connect(gate->pin(0), osig->pin(0));
+      for (unsigned idx = 0 ;  idx < isig->pin_count() ;  idx += 1)
+	    connect(gate->pin(1+idx), isig->pin(idx));
+
+      return osig;
+}
+
+/*
+ * Synthesize a ?: operator an a NetMux device. Connect the condition
+ * expression to the select input, then connect the true and false
+ * expressions to the B and A inputs. This way, when the select input
+ * is one, the B input, which is the true expression, is selected.
+ */
 NetNet* NetETernary::synthesize(Design *des)
 {
-      string path = des->local_symbol("SYNTH");
       NetNet*csig = cond_->synthesize(des);
       NetNet*tsig = true_val_->synthesize(des);
       NetNet*fsig = false_val_->synthesize(des);
 
+      string path = csig->scope()->name()+"."+csig->scope()->local_symbol();
+
       assert(csig->pin_count() == 1);
       assert(tsig->pin_count() == fsig->pin_count());
       unsigned width=tsig->pin_count();
@@ -301,7 +570,7 @@ NetNet* NetETernary::synthesize(Design *des)
       osig->local_flag(true);
 
       string oname = des->local_symbol(path);
-      NetMux *mux = new NetMux(oname, width, 2, 1);
+      NetMux *mux = new NetMux(csig->scope(), oname, width, 2, 1);
       for (unsigned idx = 0 ;  idx < width;  idx += 1) {
 	    connect(tsig->pin(idx), mux->pin_Data(idx, 1));
 	    connect(fsig->pin(idx), mux->pin_Data(idx, 0));
@@ -313,13 +582,138 @@ NetNet* NetETernary::synthesize(Design *des)
       return osig;
 }
 
+/*
+ * When synthesizing a signal expression, it is usually fine to simply
+ * return the NetNet that it refers to. If this is a part select,
+ * though, a bit more work needs to be done. Return a temporary that
+ * represents the connections to the selected bits.
+ *
+ * For example, if there is a reg foo, like so:
+ *     reg [5:0] foo;
+ * and this expression node represents a part select foo[3:2], then
+ * create a temporary like so:
+ *
+ *                     foo
+ *                    +---+
+ *                    | 5 |
+ *                    +---+
+ *         tmp        | 4 |
+ *        +---+       +---+
+ *        | 1 | <---> | 3 |
+ *        +---+       +---+
+ *        | 0 | <---> | 2 |
+ *        +---+       +---+
+ *                    | 1 |
+ *                    +---+
+ *                    | 0 |
+ *                    +---+
+ * The temporary is marked as a temporary and returned to the
+ * caller. This causes the caller to get only the selected part of the
+ * signal, and when it hooks up to tmp, it hooks up to the right parts
+ * of foo.
+ */
 NetNet* NetESignal::synthesize(Design*des)
 {
-      return net_;
+      if ((lsi_ == 0) && (msi_ == (net_->pin_count() - 1)))
+	    return net_;
+
+      assert(msi_ >= lsi_);
+      unsigned wid = msi_ - lsi_ + 1;
+
+      NetScope*scope = net_->scope();
+      assert(scope);
+
+      string name = scope->name() + "." + scope->local_symbol();
+      NetNet*tmp = new NetNet(scope, name, NetNet::NetNet::WIRE, wid);
+      tmp->local_flag(true);
+
+      for (unsigned idx = 0 ;  idx < wid ;  idx += 1)
+	    connect(tmp->pin(idx), net_->pin(idx+lsi_));
+
+      return tmp;
 }
 
 /*
  * $Log: expr_synth.cc,v $
+ * Revision 1.37  2002/11/17 23:37:55  steve
+ *  Magnitude compare to 0.
+ *
+ * Revision 1.36  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.35  2002/07/07 22:31:39  steve
+ *  Smart synthesis of binary AND expressions.
+ *
+ * Revision 1.34  2002/07/05 21:26:17  steve
+ *  Avoid emitting to vvp local net symbols.
+ *
+ * Revision 1.33  2002/05/26 01:39:02  steve
+ *  Carry Verilog 2001 attributes with processes,
+ *  all the way through to the ivl_target API.
+ *
+ *  Divide signal reference counts between rval
+ *  and lval references.
+ *
+ * Revision 1.32  2002/05/23 03:08:51  steve
+ *  Add language support for Verilog-2001 attribute
+ *  syntax. Hook this support into existing $attribute
+ *  handling, and add number and void value types.
+ *
+ *  Add to the ivl_target API new functions for access
+ *  of complex attributes attached to gates.
+ *
+ * Revision 1.31  2001/12/30 17:06:52  steve
+ *  Synthesize reduction logic.
+ *
+ * Revision 1.30  2001/12/18 05:34:02  steve
+ *  Comments about MUX synthesis.
+ *
+ * Revision 1.29  2001/11/29 01:58:18  steve
+ *  Handle part selects in l-values of DFF devices.
+ *
+ * Revision 1.28  2001/10/28 01:14:53  steve
+ *  NetObj constructor finally requires a scope.
+ *
+ * Revision 1.27  2001/10/20 05:21:51  steve
+ *  Scope/module names are char* instead of string.
+ *
+ * Revision 1.26  2001/08/31 22:59:48  steve
+ *  synthesize the special case of compare with 0.
+ *
+ * Revision 1.25  2001/08/05 02:49:07  steve
+ *  Properly synthesize part selects.
+ *
+ * Revision 1.24  2001/07/25 03:10:49  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
+ *
+ * Revision 1.23  2001/07/07 01:38:45  steve
+ *  Put synthesized signals in proper scope.
+ *
+ * Revision 1.22  2001/06/15 04:14:18  steve
+ *  Generate vvp code for GT and GE comparisons.
+ *
+ * Revision 1.21  2001/06/07 02:12:43  steve
+ *  Support structural addition.
+ *
+ * Revision 1.20  2001/02/15 06:59:36  steve
+ *  FreeBSD port has a maintainer now.
+ *
+ * Revision 1.19  2001/01/18 03:16:35  steve
+ *  NetMux needs a scope. (PR#115)
+ *
+ * Revision 1.18  2000/11/29 23:16:18  steve
+ *  Do not delete synthesized signals used in expressions.
+ *
+ * Revision 1.17  2000/11/29 05:24:00  steve
+ *  synthesis for unary reduction ! and N operators.
+ *
+ * Revision 1.16  2000/11/29 02:09:52  steve
+ *  Add support for || synthesis (PR#53)
+ *
+ * Revision 1.15  2000/10/07 19:45:43  steve
+ *  Put logic devices into scopes.
+ *
  * Revision 1.14  2000/05/02 00:58:12  steve
  *  Move signal tables to the NetScope class.
  *

functor.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2000 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2002 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -16,10 +16,14 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: functor.cc,v 1.18 2000/05/02 00:58:12 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: functor.cc,v 1.31 2002/08/16 05:18:27 steve Exp $"
 #endif
 
+# include "config.h"
+
+# include  <iostream>
+
 # include  "functor.h"
 # include  "netlist.h"
 
@@ -55,6 +59,10 @@ void functor_t::lpm_divide(class Design*, class NetDivide*)
 {
 }
 
+void functor_t::lpm_modulo(class Design*, class NetModulo*)
+{
+}
+
 void functor_t::lpm_ff(class Design*, class NetFF*)
 {
 }
@@ -67,6 +75,11 @@ void functor_t::lpm_mult(class Design*, class NetMult*)
 {
 }
 
+void functor_t::lpm_mux(class Design*, class NetMux*)
+{
+}
+
+
 void NetScope::run_functor(Design*des, functor_t*fun)
 {
       for (NetScope*cur = sub_ ;  cur ;  cur = cur->sib_) {
@@ -79,21 +92,31 @@ void NetScope::run_functor(Design*des, functor_t*fun)
 	    fun->event(des, tmp);
       }
 
-	// apply to signals
+	// apply to signals. Each iteration, allow for the possibility
+	// that the current signal deletes itself.
       if (signals_) {
+	    unsigned count = 0;
 	    NetNet*cur = signals_->sig_next_;
 	    do {
+		  count += 1;
+		  cur = cur->sig_next_;
+	    } while (cur != signals_->sig_next_);
+
+	    cur = signals_->sig_next_;
+	    for (unsigned idx = 0 ;  idx < count ;  idx += 1) {
 		  NetNet*tmp = cur->sig_next_;
 		  fun->signal(des, cur);
 		  cur = tmp;
-	    } while (cur != signals_->sig_next_);
+	    }
       }
 }
 
 void Design::functor(functor_t*fun)
 {
 	// Scan the scopes
-      root_scope_->run_functor(this, fun);
+      for (list<NetScope*>::const_iterator scope = root_scopes_.begin(); 
+	   scope != root_scopes_.end(); scope++)
+	    (*scope)->run_functor(this, fun);
 
 	// apply to processes
       procs_idx_ = procs_;
@@ -105,12 +128,31 @@ void Design::functor(functor_t*fun)
 
 	// apply to nodes
       if (nodes_) {
-	    NetNode*cur = nodes_->node_next_;
+	    assert(nodes_functor_cur_ == 0);
+	    assert(nodes_functor_nxt_ == 0);
+
+	      /* Scan the circular list of nodes, starting with the
+		 front of the list.
+
+		 This loop interacts with the Design::del_node method
+		 so that the functor is free to delete any nodes it
+		 choose. The destructors of the NetNode objects call
+		 the del_node method, which checks with the
+		 nodes_functor_* members, to keep the iterator
+		 operating safely. */
+	    nodes_functor_cur_ = nodes_;
 	    do {
-		  NetNode*tmp = cur->node_next_;
-		  cur->functor_node(this, fun);
-		  cur = tmp;
-	    } while (nodes_ && cur != nodes_->node_next_);
+		  nodes_functor_nxt_ = nodes_functor_cur_->node_next_;
+		  nodes_functor_cur_->functor_node(this, fun);
+
+		  if (nodes_functor_nxt_ == 0)
+			break;
+
+		  nodes_functor_cur_ = nodes_functor_nxt_;
+	    } while (nodes_ && (nodes_functor_cur_ != nodes_));
+	    nodes_functor_cur_ = 0;
+	    nodes_functor_nxt_ = 0;
+
       }
 }
 
@@ -149,11 +191,21 @@ void NetLogic::functor_node(Design*des, functor_t*fun)
       fun->lpm_logic(des, this);
 }
 
+void NetModulo::functor_node(Design*des, functor_t*fun)
+{
+      fun->lpm_modulo(des, this);
+}
+
 void NetMult::functor_node(Design*des, functor_t*fun)
 {
       fun->lpm_mult(des, this);
 }
 
+void NetMux::functor_node(Design*des, functor_t*fun)
+{
+      fun->lpm_mux(des, this);
+}
+
 proc_match_t::~proc_match_t()
 {
 }
@@ -173,25 +225,23 @@ int NetAssign::match_proc(proc_match_t*that)
       return that->assign(this);
 }
 
-int proc_match_t::assign_mem(NetAssignMem*)
+int proc_match_t::assign_nb(NetAssignNB*)
 {
       return 0;
 }
 
-int NetAssignMem::match_proc(proc_match_t*that)
+int NetAssignNB::match_proc(proc_match_t*that)
 {
-      return that->assign_mem(this);
+      return that->assign_nb(this);
 }
 
 int proc_match_t::block(NetBlock*)
 {
-      cerr << "default (failing) match for block" << endl;
       return 0;
 }
 
 int NetBlock::match_proc(proc_match_t*that)
 {
-      cerr << "NetBlock::match_proc" << endl;
       return that->block(this);
 }
 
@@ -217,70 +267,42 @@ int proc_match_t::event_wait(NetEvWait*)
 
 /*
  * $Log: functor.cc,v $
- * Revision 1.18  2000/05/02 00:58:12  steve
- *  Move signal tables to the NetScope class.
+ * Revision 1.31  2002/08/16 05:18:27  steve
+ *  Fix intermix of node functors and node delete.
  *
- * Revision 1.17  2000/04/20 00:28:03  steve
- *  Catch some simple identity compareoptimizations.
+ * Revision 1.30  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
  *
- * Revision 1.16  2000/04/18 04:50:19  steve
- *  Clean up unneeded NetEvent objects.
+ * Revision 1.29  2002/08/10 22:07:38  steve
+ *  Remove useless error messages.
  *
- * Revision 1.15  2000/04/16 23:32:18  steve
- *  Synthesis of comparator in expressions.
+ * Revision 1.28  2002/06/05 03:44:25  steve
+ *  Add support for memory words in l-value of
+ *  non-blocking assignments, and remove the special
+ *  NetAssignMem_ and NetAssignMemNB classes.
  *
- *  Connect the NetEvent and related classes
- *  together better.
+ * Revision 1.27  2002/06/04 05:38:44  steve
+ *  Add support for memory words in l-value of
+ *  blocking assignments, and remove the special
+ *  NetAssignMem class.
  *
- * Revision 1.14  2000/04/12 20:02:53  steve
- *  Finally remove the NetNEvent and NetPEvent classes,
- *  Get synthesis working with the NetEvWait class,
- *  and get started supporting multiple events in a
- *  wait in vvm.
+ * Revision 1.26  2001/10/19 21:53:24  steve
+ *  Support multiple root modules (Philip Blundell)
  *
- * Revision 1.13  2000/04/01 21:40:22  steve
- *  Add support for integer division.
+ * Revision 1.25  2001/07/25 03:10:49  steve
+ *  Create a config.h.in file to hold all the config
+ *  junk, and support gcc 3.0. (Stephan Boettcher)
  *
- * Revision 1.12  2000/02/23 02:56:54  steve
- *  Macintosh compilers do not support ident.
+ * Revision 1.24  2000/11/19 20:48:30  steve
+ *  Fix cases where signal iteration might die early.
  *
- * Revision 1.11  2000/02/13 04:35:43  steve
- *  Include some block matching from Larry.
+ * Revision 1.23  2000/11/18 04:53:04  steve
+ *  Watch out in functor, it may delete the last signal.
  *
- * Revision 1.10  2000/01/13 03:35:35  steve
- *  Multiplication all the way to simulation.
- *
- * Revision 1.9  2000/01/02 17:57:20  steve
- *  Handle nodes running out during node scan.
- *
- * Revision 1.8  1999/12/30 04:19:12  steve
- *  Propogate constant 0 in low bits of adders.
- *
- * Revision 1.7  1999/12/17 06:18:16  steve
- *  Rewrite the cprop functor to use the functor_t interface.
- *
- * Revision 1.6  1999/12/05 02:24:08  steve
- *  Synthesize LPM_RAM_DQ for writes into memories.
- *
- * Revision 1.5  1999/12/01 06:06:16  steve
- *  Redo synth to use match_proc_t scanner.
- *
- * Revision 1.4  1999/11/18 03:52:19  steve
- *  Turn NetTmp objects into normal local NetNet objects,
- *  and add the nodangle functor to clean up the local
- *  symbols generated by elaboration and other steps.
- *
- * Revision 1.3  1999/11/01 02:07:40  steve
- *  Add the synth functor to do generic synthesis
- *  and add the LPM_FF device to handle rows of
- *  flip-flops.
- *
- * Revision 1.2  1999/07/18 05:52:46  steve
- *  xnfsyn generates DFF objects for XNF output, and
- *  properly rewrites the Design netlist in the process.
- *
- * Revision 1.1  1999/07/17 22:01:13  steve
- *  Add the functor interface for functor transforms.
+ * Revision 1.22  2000/09/17 21:26:15  steve
+ *  Add support for modulus (Eric Aardoom)
  *
+ * Revision 1.21  2000/08/01 02:48:41  steve
+ *  Support <= in synthesis of DFF and ram devices.
  */
 

functor.h

@@ -18,14 +18,21 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: functor.h,v 1.13 2000/04/20 00:28:03 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: functor.h,v 1.20 2002/08/12 01:34:59 steve Exp $"
 #endif
 
 /*
  * The functor is an object that can be applied to a design to
  * transform it. This is different from the target_t, which can only
  * scan the design but not transform it in any way.
+ *
+ * When a functor it scanning a process, signal or node, the functor
+ * is free to manipulate the list by deleting items, including the
+ * node being scanned. The Design class scanner knows how to handle
+ * the situation. However, if objects are added to the netlist, there
+ * is no guarantee that object will be scanned unless the functor is
+ * rerun.
  */
 
 class Design;
@@ -56,6 +63,9 @@ struct functor_t {
 	/* This method is called for each structural constant. */
       virtual void lpm_divide(class Design*des, class NetDivide*);
 
+	/* This method is called for each structural constant. */
+      virtual void lpm_modulo(class Design*des, class NetModulo*);
+
 	/* This method is called for each FF in the design. */
       virtual void lpm_ff(class Design*des, class NetFF*);
 
@@ -64,13 +74,16 @@ struct functor_t {
 
 	/* This method is called for each multiplier. */
       virtual void lpm_mult(class Design*des, class NetMult*);
+
+	/* This method is called for each MUX. */
+      virtual void lpm_mux(class Design*des, class NetMux*);
 };
 
 struct proc_match_t {
       virtual ~proc_match_t();
 
       virtual int assign(class NetAssign*);
-      virtual int assign_mem(class NetAssignMem*);
+      virtual int assign_nb(class NetAssignNB*);
       virtual int condit(class NetCondit*);
       virtual int event_wait(class NetEvWait*);
       virtual int block(class NetBlock*);
@@ -79,34 +92,32 @@ struct proc_match_t {
 
 /*
  * $Log: functor.h,v $
+ * Revision 1.20  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.19  2002/06/05 03:44:25  steve
+ *  Add support for memory words in l-value of
+ *  non-blocking assignments, and remove the special
+ *  NetAssignMem_ and NetAssignMemNB classes.
+ *
+ * Revision 1.18  2002/06/04 05:38:44  steve
+ *  Add support for memory words in l-value of
+ *  blocking assignments, and remove the special
+ *  NetAssignMem class.
+ *
+ * Revision 1.17  2000/09/17 21:26:15  steve
+ *  Add support for modulus (Eric Aardoom)
+ *
+ * Revision 1.16  2000/08/01 02:48:42  steve
+ *  Support <= in synthesis of DFF and ram devices.
+ *
+ * Revision 1.15  2000/07/16 04:56:07  steve
+ *  Handle some edge cases during node scans.
+ *
+ * Revision 1.14  2000/07/15 05:13:44  steve
+ *  Detect muxing Vz as a bufufN.
+ *
  * Revision 1.13  2000/04/20 00:28:03  steve
  *  Catch some simple identity compareoptimizations.
- *
- * Revision 1.12  2000/04/18 04:50:19  steve
- *  Clean up unneeded NetEvent objects.
- *
- * Revision 1.11  2000/04/12 20:02:53  steve
- *  Finally remove the NetNEvent and NetPEvent classes,
- *  Get synthesis working with the NetEvWait class,
- *  and get started supporting multiple events in a
- *  wait in vvm.
- *
- * Revision 1.10  2000/04/01 21:40:22  steve
- *  Add support for integer division.
- *
- * Revision 1.9  2000/02/23 02:56:54  steve
- *  Macintosh compilers do not support ident.
- *
- * Revision 1.8  2000/02/13 04:35:43  steve
- *  Include some block matching from Larry.
- *
- * Revision 1.7  2000/01/13 03:35:35  steve
- *  Multiplication all the way to simulation.
- *
- * Revision 1.6  1999/12/30 04:19:12  steve
- *  Propogate constant 0 in low bits of adders.
- *
- * Revision 1.5  1999/12/17 06:18:16  steve
- *  Rewrite the cprop functor to use the functor_t interface.
  */
 #endif

glossary.txt

@@ -0,0 +1,39 @@
+
+Throughout Icarus Verilog descriptions and source code, I use a
+variety of terms and acronyms that might be specific to Icarus
+Verilog, have an Icarus Verilog specific meaning, or just aren't
+widely known. So here I define these terms.
+
+
+LRM     - Language Reference Manual
+    This is a generic acronym, but in the Verilog world we sometimes
+    mean *the* language reference manual, the IEEE1364 standard.
+
+
+PLI     - Programming Language Interface
+    This is a C API into Verilog simulators that is defined by the
+    IEEE1364. There are two major interfaces, sometimes called PLI 1
+    and PLI 2. PLI 2 is also often called VPI.
+
+
+UDP     - User Defined Primitive
+    These are objects that Verilog programmers define with the
+    "primitive" keyword. They are truth-table based devices. The
+    syntax for defining them is described in the LRM.
+
+
+VPI     -
+    This is the C API that is defined by the Verilog standard, and
+    that Icarus Verilog partially implements. See also PLI.
+
+
+VVM     - Verilog Virtual Machine
+    This is the Icarus Verilog runtime that works with the code
+    generator that generates C++.
+
+
+VVP     - Verilog Virtual Processor
+    This is the Icarus Verilog runtime that reads in custom code in a
+    form that I call "VVP Assembly". See the vvp/ directory for
+    documentation on that.
+

ieee1364-notes.txt

@@ -0,0 +1,447 @@
+
+                Icarus Verilog vs. IEEE1364
+                Copyright 2000 Stephen Williams
+
+The IEEE1364 standard is the bible that defines the correctness of the
+Icarus Verilog implementation and behavior of the compiled
+program. The IEEE1364.1 is also referenced for matters of
+synthesis. So the ultimate definition of right and wrong comes from
+those documents.
+
+That does not mean that a Verilog implementation is fully
+constrained. The standard document allows for implementation specific
+behavior that, when properly accounted for, does not effect the
+intended semantics of the specified language. It is therefore possible
+and common to write programs that produce different results when run
+by different Verilog implementations.
+
+
+STANDARDIZATION ISSUES
+
+These are some issues where the IEEE1364 left unclear, unspecified or
+simply wrong. I'll try to be precise as I can, and reference the
+standard as needed. I've made implementation decisions for Icarus
+Verilog, and I will make clear what those decisions are and how they
+affect the language.
+
+* OBJECTS CAN BE DECLARED ANYWHERE IN THE MODULE
+
+Consider this module:
+
+    module sample1;
+        initial foo = 1;
+	reg foo;
+	wire tmp = bar;
+	initial #1 $display("foo = %b, bar = %b", foo, tmp);
+    endmodule
+
+Notice that the ``reg foo;'' declaration is placed after the first
+initial statement. It turns out that this is a perfectly legal module
+according to the -1995 and -2000 versions of the standard. The
+statement ``reg foo;'' is a module_item_declaration which is in turn a
+module_item. The BNF in the appendix of IEEE1364-1995 treats all
+module_item statements equally, so no order is imposed.
+
+Furthermore, there is no text (that I can find) elsewhere in the
+standard that imposes any ordering restriction. The sorts of
+restrictions I would look for are "module_item_declarations must
+appear before all other module_items" or "variables must be declared
+textually before they are referenced." Such statements simply do not
+exist. (Personally, I think it is fine that they don't.)
+
+The closest is the rules for implicit declarations of variables that
+are otherwise undeclared. In the above example, ``bar'' is implicitly
+declared and is therefore a wire. However, although ``initial foo = 1;''
+is written before foo is declared, foo *is* declared within the
+module, and declared legally by the BNF of the standard.
+
+Here is another example:
+
+    module sample2;
+	initial x.foo = 1;
+        test x;
+	initial #1 $display("foo = %b", x.foo);
+    endmodule
+
+    module test;
+        reg foo;
+    endmodule;
+
+From this example one can clearly see that foo is once again declared
+after its use in behavioral code. One also sees a forward reference of
+an entire module. Once again, the standard places no restriction on
+the order of module declarations in a source file, so this program is,
+according to the standard, perfectly well formed.
+
+Icarus Verilog interprets both of these examples according to "The
+Standard As I Understand It." However, commercial tools in general
+break down with these programs. In particular, the first example
+may generate different errors depending on the tool. The most common
+error is to claim that ``foo'' is declared twice, once (implicitly) as
+a wire and once as a reg.
+
+So the question now becomes, "Is the standard broken, or are the tools
+limited?" Coverage of the standard seems to vary widely from tool to
+tool so it is not clear that the standard really is at fault. It is
+clear, however, that somebody goofed somewhere.
+
+My personal opinion is that there is no logical need to require that
+all module_item_declarations precede any other module items. I
+personally would oppose such a restriction. It may make sense to
+require that declarations of variables within a module be preceded by
+their use, although even that is not necessary for the implementation
+of efficient compilers.
+
+However, the existence hierarchical naming syntax as demonstrated in
+sample2 can have implications that affect any declaration order
+rules. When reaching into a module with a hierarchical name, the
+module being referenced is already completely declared (or not
+declared at all, as in sample2) so module_item order is completely
+irrelevant. But a "declare before use" rule would infect module
+ordering, by requiring that modules that are used be first defined.
+
+
+* TASK AND FUNCTION PARAMETERS CANNOT HAVE EXPLICIT TYPES
+
+Consider a function negate that wants to take a signed integer value
+and return its negative:
+
+	function integer negate;
+	    input [15:0] val;
+	    negate = -val;
+	endfunction
+
+This is not quite right, because the input is implicitly a reg type,
+which is unsigned. The result, then, will always be a negative value,
+even if a negative val is passed in.
+
+It is possible to fix up this specific example to work properly with
+the bit pattern of a 16bit number, but that is not the point. What's
+needed is clarification on whether an input can be declared in the
+port declaration as well as in the contained block declaration.
+
+As I understand the situation, this should be allowed:
+
+	function integer negate;
+	    input [15:0] val;
+	    reg signed [15:0] val;
+	    negate = -val;
+	endfunction
+
+In the -1995 standard, the variable is already implicitly a reg if
+declared within a function or task. However, in the -2000 standard
+there is now (as in this example) a reason why one might want to
+actually declare the type explicitly.
+
+I think that a port *cannot* be declared as an integer or time type
+(though the result can) because the range of the port declaration must
+match the range of the integer/time declaration, but the range of
+integers is unspecified. This, by the way, also applies to module
+ports.
+
+With the above in mind, I have decided to *allow* function and task
+ports to be declared with types, as long as the types are variable
+types, such as reg or integer. Without this, there would be no
+portable way to pass integers into functions/tasks. The standard does
+not say it is allowed, but it doesn't *disallow* it, and other
+commercial tools seem to work similarly.
+
+
+* ROUNDING OF TIME
+
+When the `timescale directive is present, the compiler is supposed to
+round fractional times (after scaling) to the nearest integer. The
+confusing bit here is that it is apparently conventional that if the
+`timescale directive is *not* present, times are rounded towards zero
+always.
+
+
+* VALUE OF X IN PRIMITIVE OUTPUTS
+
+The IEEE1364-1995 standard clearly states in Table 8-1 that the x
+symbols is allowed in input columns, but is not allowed in
+outputs. Furthermore, none of the examples have an x in the output of
+a primitive. Table 8-1 in the IEEE1364-2000 also says the same thing.
+
+However, the BNF clearly states that 0, 1, x and X are valid
+output_symbol characters. The standard is self contradictory. So I
+take it that x is allowed, as that is what Verilog-XL does.
+
+
+* REPEAT LOOPS vs. REPEAT EVENT CONTROL
+
+There seems to be ambiguity in how code like this should be parsed:
+
+	repeat (5) @(posedge clk) <statement>;
+
+There are two valid interpretations of this code, from the
+IEEE1364-1995 standard. One looks like this:
+
+    procedural_timing_control_statement ::=
+          delay_or_event_control  statement_or_null
+
+    delay_or_event_control ::=
+          event_control
+          | repeat ( expression ) event_control
+
+If this interpretation is used, then the statement <statement> should
+be executed after the 5th posedge of clk. However, there is also this
+interpretation:
+
+    loop_statement ::=
+         repeat ( expression ) statement
+
+If *this* interpretation is used, then <statement> should be executed
+5 times on the posedge of clk. The way the -1995 standard is written,
+these are both equally valid interpretations of the example, yet they
+produce very different results. The standard offers no guidance on how
+to resolve this conflict, and the IEEE1364-2000 DRAFT does not improve
+the situation.
+
+Practice suggests that a repeat followed by an event control should be
+interpreted as a loop head, and this is what Icarus Verilog does, as
+well as all the other major Verilog tools, but the standard does not
+say this.
+
+
+* UNSIZED EXPRESSIONS AS PARAMETERS TO CONCATENATION {}
+
+The Verilog standard clearly states in 4.1.14:
+
+	"Unsized constant numbers shall not be allowed in
+	concatenations. This is because the size of each
+	operand in the concatenation is needed to calculate
+	the complete size of the concatenation."
+
+So for example the expression {1'b0, 16} is clearly illegal. It
+also stands to reason that {1'b0, 15+1} is illegal, for exactly the
+same justification. What is the size of the expression (15+1)?
+Furthermore, it is reasonable to expect that (16) and (15+1) are
+exactly the same so far as the compiler is concerned.
+
+Unfortunately, Cadence seems to feel otherwise. In particular, it has
+been reported that although {1'b0, 16} causes an error, {1'b0, 15+1}
+is accepted. Further testing shows that any expression other then a
+simple unsized constant is accepted there, even if all the operands of
+all the operators that make up the expression are unsized integers.
+
+This is a semantic problem. Icarus Verilog doesn't limit the size of
+integer constants. This is valid as stated in 2.5.1 Note 3:
+
+	"The number of bits that make up an unsized number
+	(which is a simple decimal number or a number without
+	the size specification) shall be *at*least* 32."
+	[emphasis added]
+
+Icarus Verilog will hold any integer constant, so the size will be as
+large as it needs to be, whether that is 64bits, 128bits, or
+more. With this in mind, what is the value of these expressions?
+
+	{'h1_00_00_00_00}
+	{'h1 << 32}
+	{'h0_00_00_00_01 << 32}
+	{'h5_00_00_00_00 + 1}
+
+These examples show that the standard is justified in requiring that
+the operands of concatenation have size. The dispute is what it takes
+to cause an expression to have a size, and what that size is.
+Verilog-XL claims that (16) does not have a size, but (15+1) does. The
+size of the expression (15+1) is the size of the adder that is
+created, but how wide is the adder when adding unsized constants?
+
+One might note that the quote from section 4.1.14 says "Unsized
+*constant*numbers* shall not be allowed." It does not say "Unsized
+expressions...", so arguably accepting (15+1) or even (16+0) as an
+operand to a concatenation is not a violation of the letter of the
+law. However, the very next sentence of the quote expresses the
+intent, and accepting (15+1) as having a more defined size then (16)
+seems to be a violation of that intent.
+
+Whatever a compiler decides the size is, the user has no way to
+predict it, and the compiler should not have the right to treat (15+1)
+any differently then (16). Therefore, Icarus Verilog takes the
+position that such expressions are *unsized* and are not allowed as
+operands to concatenations. Icarus Verilog will in general assume that
+operations on unsized numbers produce unsized results. There are
+exceptions when the operator itself does define a size, such as the
+comparison operators or the reduction operators. Icarus Verilog will
+generate appropriate error messages.
+
+
+* MODULE INSTANCE WITH WRONG SIZE PORT LIST
+
+A module declaration like this declares a module that takes three ports:
+
+	module three (a, b, c);
+	  input a, b, c;
+	  reg x;
+	endmodule
+
+This is fine and obvious. It is also clear from the standard that
+these are legal instantiations of this module:
+
+	three u1 (x,y,z);
+	three u2 ( ,y, );
+	three u3 ( , , );
+	three u4 (.b(y));
+
+In some of the above examples, there are unconnected ports. In the
+case of u4, the pass by name connects only port b, and leaves a and c
+unconnected. u2 and u4 are the same thing, in fact, but using
+positional or by-name syntax. The next example is a little less
+obvious:
+
+	three u4 ();
+
+The trick here is that strictly speaking, the parser cannot tell
+whether this is a list of no pass by name ports (that is, all
+unconnected) or an empty positional list. If this were an empty
+positional list, then the wrong number of ports is given, but if it is
+an empty by-name list, it is an obviously valid instantiation. So it
+is fine to accept this case as valid.
+
+These are more doubtful:
+
+	three u5(x,y);
+	three u6(,);
+
+These are definitely positional port lists, and they are definitely
+the wrong length. In this case, the standard is not explicit about
+what to do about positional port lists in module instantiations,
+except that the first is connected to the first, second to second,
+etc. It does not say that the list must be the right length, but every
+example of unconnected ports used by-name syntax, and every example of
+ordered list has the right size list.
+
+Icarus Verilog takes the (very weak) hint that ordered lists should be
+the right length, and will therefore flag instances u5 and u6 as
+errors. The IEEE1364 standard should be more specific one way or the
+other.
+
+* UNKNOWN VALUES IN L-VALUE BIT SELECTS
+
+Consider this example:
+
+	reg [7:0] vec;
+	wire [4:0] idx = <expr>;
+	[...]
+	vec[idx] = 1;
+
+So long as the value of idx is a valid bit select address, the
+behavior of this assignment is obvious. However, there is no explicit
+word in the standard as to what happens if the value is out of
+range. The standard clearly states the value of an expression when the
+bit-select or part select is out of range (the value is x) but does
+not address the behavior when the expression is an l-value.
+
+Icarus Verilog will take the position that bit select expressions in
+the l-value will select oblivion if it is out of range. That is, if
+idx has a value that is not a valid bit select of vec, then the
+assignment will have no effect.
+
+
+* SCHEDULING VALUES IN LOGIC
+
+The interaction between blocking assignments in procedural code and
+logic gates in gate-level code and expressions is poorly defined in
+Verilog. Consider this example:
+
+   reg a;
+   reg b;
+   wire q = a & b;
+
+   initial begin
+      a = 1;
+      b = 0;
+      #1 b = 1;
+      if (q !== 0) begin
+	 $display("FAILED -- q changed too soon? %b", q);
+	 $finish;
+      end
+   end
+
+This is a confusing situation. It is clear from the Verilog standard
+that an assignment to a variable using a blocking assign causes the
+l-value to receive the value before the assignment completes. This
+means that a subsequent read of the assigned variable *must* read back
+what was blocking-assigned.
+
+However, in the example above, the "wire q = a & b" expresses some
+gate logic between a/b and q. The standard does not say whether a read
+out of logic should read the value computed from previous assigns to
+the input from the same thread. Specifically, when "a" and "b" are
+assigned by blocking assignments, will a read of "q" get the computed
+value or the existing value?
+
+In fact, existing commercial tools do it both ways. Some tools print
+the FAILED message in the above example, and some do not. Icarus
+Verilog does not print the FAILED message in the above example,
+because the gate value change is *scheduled* when inputs are assigned,
+but not propagated until the thread gives up the processor.
+
+Icarus Verilog chooses this behavior in order to filter out zero-width
+pulses as early as possible. The implication of this is that a read of
+the output of combinational logic will most likely *not* reflect the
+changes in inputs until the thread that changed the inputs yields
+execution.
+
+
+* BIT AND PART SELECTS OF PARAMETERS
+
+Bit and part selects are supposed to only be supported on vector nets
+and variables (wires, regs, etc.) However, it is common for Verilog
+compilers to also support bit and part select on parameters. Icarus
+Verilog also chooses to support bit and part selects on parameter
+names, but we need to define what that means.
+
+A bit or a part select on a parameter expression returns an unsigned
+value with a defined size. The parameter value is considered be a
+constant vector of bits foo[X:0]. That is, zero based. The bit and
+part selects operate from that assumption.
+
+Verilog 2001 adds syntax to allow the user to explicitly declare the
+parameter range (i.e. parameter [5:0] foo = 9;) so Icarus Verilog will
+(or should) use the explicitly declared vector dimensions to interpret
+bit and part selects.
+
+$Id: ieee1364-notes.txt,v 1.13 2002/08/20 04:11:53 steve Exp $
+$Log: ieee1364-notes.txt,v $
+Revision 1.13  2002/08/20 04:11:53  steve
+ Support parameters with defined ranges.
+
+Revision 1.12  2002/06/11 03:34:33  steve
+ Spelling patch (Larry Doolittle)
+
+Revision 1.11  2002/04/27 02:38:04  steve
+ Support selecting bits from parameters.
+
+Revision 1.10  2002/03/31 01:54:13  steve
+ Notes about scheduling
+
+Revision 1.9  2002/01/26 02:08:07  steve
+ Handle x in l-value of set/x
+
+Revision 1.8  2001/08/01 05:17:31  steve
+ Accept empty port lists to module instantiation.
+
+Revision 1.7  2001/02/17 05:27:31  steve
+ I allow function ports to have types.
+
+Revision 1.6  2001/02/12 16:48:04  steve
+ Rant about bit widths.
+
+Revision 1.5  2001/01/02 17:28:08  steve
+ Resolve repeat ambiguity in favor of loop.
+
+Revision 1.4  2001/01/01 19:12:35  steve
+ repeat loops ambiguity.
+
+Revision 1.3  2000/12/15 00:21:46  steve
+ rounding of time and x in primitives.
+
+Revision 1.2  2000/11/19 22:03:04  steve
+ Integer parameter comments.
+
+Revision 1.1  2000/07/23 18:06:31  steve
+ Document ieee1364 issues.
+

iverilog-vpi.man

@@ -0,0 +1,72 @@
+.TH iverilog-vpi 1 "$Date: 2002/11/23 00:51:53 $" Version "$Date: 2002/11/23 00:51:53 $"
+.SH NAME
+iverilog-vpi - Compile front end for VPI modules
+
+.SH SYNOPSIS
+.B iverilog-vpi
+[--name=\fIname\fP]
+\fIsourcefile\fP...
+
+.SH DESCRIPTION
+.PP
+\fIiverilog-vpi\fP is a tool to simplify the compilation of VPI
+modules for use with Icarus Verilog. It takes on the command line a
+list of C or C++ source files, and generates as output a linked VPI
+module. See the \fBvvp\fP(1) man page for a description of how the
+linked module is loaded by a simulation.
+
+The output is named after the first source file. For example, if the
+first source file is named \fIfoo.c\fP, the output becomes
+\fIfoo.vpi\fP.
+
+.SH OPTIONS
+.l
+\fIiverilog-vpi\fP accepts the following options:
+.TP 8
+.B -l\fIlibrary\fP
+Include the named library in the link of the VPI module. This allows
+VPI modules to further reference external libraries.
+
+.TP 8
+.B --name=\fIname\fP
+Normally, the output VPI module will be named after the first source
+file passed to the command. This flag sets the name (without the .vpi
+suffix) of the output vpi module.
+
+.SH "PC-ONLY OPTIONS"
+
+The PC port of \fIiverilog-vpi\fP includes two special flags needed to
+support the more intractable development environment. These flags help
+the program locate parts that it needs.
+
+.TP 8
+.B -mingw=\fIpath\fP
+Tell the program the root of the Mingw compiler tool suite. The
+\fBvvp\fP runtime is compiled with this compiler, and this is the
+compiler that \fIiverilog-vpi\fP expects to use to compile your source
+code. This is notmally not needed, and if you do use it, it is only
+needed once. The compiler will save the \fIpath\fP in the registry for
+use later.
+
+.TP 8
+.B -ivl=\fIpath\fP
+Set for the use during compilation the root if the Icarus Verilog
+install. This is the place where you installed Icarus Verilog when you
+ran the installer. This flag is also only needed once, and the path is
+stored in the registry for future use.
+
+.SH "AUTHOR"
+.nf
+Steve Williams ([email protected])
+
+.SH SEE ALSO
+iverilog(1), vvp(1),
+.BR "<http://www.icarus.com/eda/verilog/>",
+.BR "<http://www.mingw.org>",
+
+.SH COPYRIGHT
+.nf
+Copyright \(co  2002 Stephen Williams
+
+This document can be freely redistributed according to the terms of the 
+GNU General Public License version 2.0

iverilog-vpi.sh

@@ -0,0 +1,114 @@
+#!/bin/sh
+#
+#    This source code is free software; you can redistribute it
+#    and/or modify it in source code form under the terms of the GNU
+#    Library General Public License as published by the Free Software
+#    Foundation; either version 2 of the License, or (at your option)
+#    any later version.
+#
+#    This program is distributed in the hope that it will be useful,
+#    but WITHOUT ANY WARRANTY; without even the implied warranty of
+#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#    GNU Library General Public License for more details.
+#
+#    You should have received a copy of the GNU Library General Public
+#    License along with this program; if not, write to the Free
+#    Software Foundation, Inc.,
+#    59 Temple Place - Suite 330
+#    Boston, MA 02111-1307, USA
+#
+#ident "$Id: iverilog-vpi.sh,v 1.9 2002/10/19 23:18:52 steve Exp $"
+
+# These are the variables used for compiling files
+CC=gcc
+CXX=gcc
+CFLAGS="@PIC@ -O -I@INCLUDEDIR@"
+
+# These are used for linking...
+LD=gcc
+LDFLAGS="@SHARED@"
+LDLIBS="-L@LIBDIR@ -lveriuser -lvpi"
+
+CCSRC=
+CXSRC=
+OBJ=
+LIB=
+OUT=
+
+# --
+# parse the command line switches. This collects the source files
+# and precompiled object files, and maybe user libraries. As we are
+# going, guess an output file name.
+for parm
+do
+    case $parm
+    in
+
+    *.c) CCSRC="$CCSRC $parm"
+         if [ x$OUT = x ]; then
+	    OUT=`basename $parm .c`
+	 fi
+	 ;;
+
+    *.cc) CXSRC="$CXSRC $parm"
+         if [ x$OUT = x ]; then
+	    OUT=`basename $parm .cc`
+	 fi
+	 ;;
+
+    *.o) OBJ="$OBJ $parm"
+         if [ x$OUT = x ]; then
+	    OUT=`basename $parm .o`
+	 fi
+	 ;;
+
+    --name=*)
+	 OUT=`echo $parm | cut -b8-`
+	 ;;
+
+    -l*) LIB="$LIB $parm"
+	 ;;
+
+    esac
+
+done
+
+if [ x$OUT = x ]; then
+    echo "Usage: $0 [src and obj files]..."
+    exit 0
+fi
+
+# Put the .vpi on the result file.
+OUT=$OUT".vpi"
+
+compile_errors=0
+
+# Compile all the source files into object files
+for src in $CCSRC
+do
+    base=`basename $src .c`
+    obj=$base".o"
+
+    echo "Compiling $src..."
+    $CC -c -o $obj $CFLAGS $src || compile_errors=`expr $compile_errors + 1`
+    OBJ="$OBJ $obj"
+done
+
+for src in $CXSRC
+do
+    base=`basename $src .cc`
+    obj=$base".o"
+
+    echo "Compiling $src..."
+    $CXX -c -o $obj $CFLAGS $src || compile_errors=`expr $compile_errors + 1`
+    OBJ="$OBJ $obj"
+done
+
+if test $compile_errors -gt 0
+then
+    echo "Some ($compile_errors) files failed to compile."
+    exit $compile_errors
+fi
+
+echo "Making $OUT from $OBJ..."
+exec $LD -o $OUT $LDFLAGS $OBJ $LIB $LDLIBS

iverilog.c

@@ -1,432 +0,0 @@
-/*
- * Copyright (c) 2000 Stephen Williams (steve@icarus.com)
- *
- *    This source code is free software; you can redistribute it
- *    and/or modify it in source code form under the terms of the GNU
- *    General Public License as published by the Free Software
- *    Foundation; either version 2 of the License, or (at your option)
- *    any later version.
- *
- *    This program is distributed in the hope that it will be useful,
- *    but WITHOUT ANY WARRANTY; without even the implied warranty of
- *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *    GNU General Public License for more details.
- *
- *    You should have received a copy of the GNU General Public License
- *    along with this program; if not, write to the Free Software
- *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
- */
-#if !defined(WINNT)
-#ident "$Id: iverilog.c,v 1.16 2000/06/16 19:00:06 steve Exp $"
-#endif
-
-#include <stdio.h>
-#include <unistd.h>
-#include <stdlib.h>
-#include <string.h>
-
-#ifndef IVL_ROOT
-# define IVL_ROOT "."
-#endif
-
-#ifndef RDYNAMIC
-# define RDYNAMIC "-rdynamic"
-#endif
-
-const char*base = IVL_ROOT;
-const char*opath = "a.out";
-const char*targ  = "vvm";
-const char*start = 0;
-
-char warning_flags[16] = "";
-
-char*inc_list = 0;
-char*def_list = 0;
-char*mod_list = 0;
-
-char*f_list = 0;
-
-int synth_flag = 0;
-int verbose_flag = 0;
-
-char tmp[4096];
-
-static int t_null(char*cmd, unsigned ncmd)
-{
-      int rc;
-
-      sprintf(tmp, " | %s/ivl %s", base, warning_flags);
-      rc = strlen(tmp);
-      cmd = realloc(cmd, ncmd+rc+1);
-      strcpy(cmd+ncmd, tmp);
-      ncmd += rc;
-
-      if (start) {
-	    sprintf(tmp, " -s%s", start);
-	    rc = strlen(tmp);
-	    cmd = realloc(cmd, ncmd+rc+1);
-	    strcpy(cmd+ncmd, tmp);
-	    ncmd += rc;
-      }
-
-      if (verbose_flag) {
-	    sprintf(tmp, " -v");
-	    rc = strlen(tmp);
-	    cmd = realloc(cmd, ncmd+rc+1);
-	    strcpy(cmd+ncmd, tmp);
-	    ncmd += rc;
-      }
-
-      sprintf(tmp, " -- -");
-      rc = strlen(tmp);
-      cmd = realloc(cmd, ncmd+rc+1);
-      strcpy(cmd+ncmd, tmp);
-      ncmd += rc;
-
-      if (verbose_flag)
-	    printf("translate: %s\n", cmd);
-
-      rc = system(cmd);
-      return rc;
-}
-
-/*
- * This function handles the vvm target. After preprocessing, run the
- * ivl translator to get C++, then run g++ to make an executable
- * program out of that.
- */
-static int t_vvm(char*cmd, unsigned ncmd)
-{
-      int rc;
-
-      sprintf(tmp, " | %s/ivl %s -o %s.cc -tvvm -Fcprop %s -Fnodangle"
-	      " -fVPI_MODULE_PATH=%s", base, warning_flags, opath,
-	      synth_flag?"-Fsynth -Fsyn-rules":"", base);
-
-      rc = strlen(tmp);
-      cmd = realloc(cmd, ncmd+rc+1);
-      strcpy(cmd+ncmd, tmp);
-      ncmd += rc;
-
-      if (f_list) {
-	    rc = strlen(f_list);
-	    cmd = realloc(cmd, ncmd+rc+1);
-	    strcpy(cmd+ncmd, f_list);
-	    ncmd += rc;
-      }
-
-      if (mod_list) {
-	    rc = strlen(mod_list);
-	    cmd = realloc(cmd, ncmd+rc+1);
-	    strcpy(cmd+ncmd, mod_list);
-	    ncmd += rc;
-      }
-
-      if (start) {
-	    sprintf(tmp, " -s%s", start);
-	    rc = strlen(tmp);
-	    cmd = realloc(cmd, ncmd+rc+1);
-	    strcpy(cmd+ncmd, tmp);
-	    ncmd += rc;
-      }
-      sprintf(tmp, " -- -");
-      rc = strlen(tmp);
-      cmd = realloc(cmd, ncmd+rc+1);
-      strcpy(cmd+ncmd, tmp);
-      ncmd += rc;
-
-      if (verbose_flag)
-	    printf("translate: %s\n", cmd);
-
-      rc = system(cmd);
-      if (rc != 0) {
-	    fprintf(stderr, "errors translating Verilog program.\n");
-	    return rc;
-      }
-
-      sprintf(tmp, "%s -O " RDYNAMIC " -fno-exceptions -o %s -I%s "
-	      "-L%s %s.cc -lvvm %s", CXX, opath, IVL_INC, IVL_LIB,
-	      opath, DLLIB);
-
-      if (verbose_flag)
-	    printf("compile: %s\n", tmp);
-
-      rc = system(tmp);
-      if (rc != 0) {
-	    fprintf(stderr, "errors compiling translated program.\n");
-	    return rc;
-      }
-
-      sprintf(tmp, "%s.cc", opath);
-      unlink(tmp);
-
-      return 0;
-}
-
-static int t_xnf(char*cmd, unsigned ncmd)
-{
-      int rc;
-
-      sprintf(tmp, " | %s/ivl %s -o %s -txnf -Fcprop -Fsynth -Fsyn-rules "
-	      "-Fnodangle -Fxnfio", base, warning_flags, opath);
-
-      rc = strlen(tmp);
-      cmd = realloc(cmd, ncmd+rc+1);
-      strcpy(cmd+ncmd, tmp);
-      ncmd += rc;
-
-      if (f_list) {
-	    rc = strlen(f_list);
-	    cmd = realloc(cmd, ncmd+rc+1);
-	    strcpy(cmd+ncmd, f_list);
-	    ncmd += rc;
-      }
-
-      if (start) {
-	    sprintf(tmp, " -s%s", start);
-	    rc = strlen(tmp);
-	    cmd = realloc(cmd, ncmd+rc+1);
-	    strcpy(cmd+ncmd, tmp);
-	    ncmd += rc;
-      }
-      sprintf(tmp, " -- -");
-      rc = strlen(tmp);
-      cmd = realloc(cmd, ncmd+rc+1);
-      strcpy(cmd+ncmd, tmp);
-      ncmd += rc;
-
-      if (verbose_flag)
-	    printf("translate: %s\n", cmd);
-
-      rc = system(cmd);
-
-      return rc;
-}
-
-static void process_warning_switch(const char*name)
-{
-      if (warning_flags[0] == 0)
-	    strcpy(warning_flags, "-W");
-
-      if (strcmp(name,"all") == 0) {
-	    strcat(warning_flags, "i");
-
-      } else if (strcmp(name,"implicit") == 0) {
-	    if (! strchr(warning_flags+2, 'i'))
-		  strcat(warning_flags, "i");
-      }
-}
-
-int main(int argc, char **argv)
-{
-      char*cmd;
-      unsigned ncmd;
-      int e_flag = 0;
-      int opt, idx;
-      char*cp;
-
-      while ((opt = getopt(argc, argv, "B:D:Ef:I:m:o:Ss:t:vW:")) != EOF) {
-
-	    switch (opt) {
-		case 'B':
-		  base = optarg;
-		  break;
-		case 'D':
-		  if (def_list == 0) {
-			def_list = malloc(strlen(" -D")+strlen(optarg)+1);
-			strcpy(def_list, " -D");
-			strcat(def_list, optarg);
-		  } else {
-			def_list = realloc(def_list, strlen(def_list)
-					   + strlen(" -D")
-					   + strlen(optarg) + 1);
-			strcat(def_list, " -D");
-			strcat(def_list, optarg);
-		  }
-		  break;
-		case 'E':
-		  e_flag = 1;
-		  break;
-		case 'f':
-		  if (f_list == 0) {
-			f_list = malloc(strlen(" -f")+strlen(optarg)+1);
-			strcpy(f_list, " -f");
-			strcat(f_list, optarg);
-		  } else {
-			f_list = realloc(f_list, strlen(f_list) +
-					 strlen(" -f") +
-					 strlen(optarg) + 1);
-			strcat(f_list, " -f");
-			strcat(f_list, optarg);
-		  }
-		  break;
-		case 'I':
-		  if (inc_list == 0) {
-			inc_list = malloc(strlen(" -I")+strlen(optarg)+1);
-			strcpy(inc_list, " -I");
-			strcat(inc_list, optarg);
-		  } else {
-			inc_list = realloc(inc_list, strlen(inc_list)
-					   + strlen(" -I")
-					   + strlen(optarg) + 1);
-			strcat(inc_list, " -I");
-			strcat(inc_list, optarg);
-		  }
-		  break;
-		case 'm':
-		  if (mod_list == 0) {
-			mod_list = malloc(strlen(" -m")+strlen(optarg)+1);
-			strcpy(mod_list, " -m");
-			strcat(mod_list, optarg);
-		  } else {
-			mod_list = realloc(mod_list, strlen(mod_list)
-					   + strlen(" -m")
-					   + strlen(optarg) + 1);
-			strcat(mod_list, " -m");
-			strcat(mod_list, optarg);
-		  }
-		  break;
-		case 'o':
-		  opath = optarg;
-		  break;
-		case 'S':
-		  synth_flag = 1;
-		  break;
-		case 's':
-		  start = optarg;
-		  break;
-		case 't':
-		  targ = optarg;
-		  break;
-		case 'v':
-		  verbose_flag = 1;
-		  break;
-		case 'W':
-		  process_warning_switch(optarg);
-		  break;
-		case '?':
-		default:
-		  return 1;
-	    }
-      }
-
-      if (optind == argc) {
-	    fprintf(stderr, "%s: No input files.\n", argv[0]);
-	    return 1;
-      }
-
-	/* Start building the preprocess command line. */
-
-      sprintf(tmp, "%s/ivlpp %s%s", base,
-	      verbose_flag?" -v":"",
-	      e_flag?"":" -L");
-
-      ncmd = strlen(tmp);
-      cmd = malloc(ncmd + 1);
-      strcpy(cmd, tmp);
-
-      if (inc_list) {
-	    cmd = realloc(cmd, ncmd + strlen(inc_list) + 1);
-	    strcat(cmd, inc_list);
-	    ncmd += strlen(inc_list);
-      }
-
-      if (def_list) {
-	    cmd = realloc(cmd, ncmd + strlen(def_list) + 1);
-	    strcat(cmd, def_list);
-	    ncmd += strlen(def_list);
-      }
-
-	/* Add all the verilog source files to the preprocess command line. */
-
-      for (idx = optind ;  idx < argc ;  idx += 1) {
-	    sprintf(tmp, " %s", argv[idx]);
-	    cmd = realloc(cmd, ncmd+strlen(tmp)+1);
-	    strcpy(cmd+ncmd, tmp);
-	    ncmd += strlen(tmp);
-      }
-
-
-	/* If the -E flag was given on the command line, then all we
-	   do is run the preprocessor and put the output where the
-	   user wants it. */
-      if (e_flag) {
-	    if (strcmp(opath,"-") != 0) {
-		  sprintf(tmp, " > %s", opath);
-		  cmd = realloc(cmd, ncmd+strlen(tmp)+1);
-		  strcpy(cmd+ncmd, tmp);
-		  ncmd += strlen(tmp);
-	    }
-
-	    if (verbose_flag)
-		  printf("preprocess: %s\n", cmd);
-
-	    return system(cmd);
-      }
-
-      if (strcmp(targ,"null") == 0)
-	    return t_null(cmd, ncmd);
-      else if (strcmp(targ,"vvm") == 0)
-	    return t_vvm(cmd, ncmd);
-      else if (strcmp(targ,"xnf") == 0)
-	    return t_xnf(cmd, ncmd);
-      else {
-	    fprintf(stderr, "Unknown target: %s\n", targ);
-	    return 1;
-      }
-
-      return 0;
-}
-
-/*
- * $Log: iverilog.c,v $
- * Revision 1.16  2000/06/16 19:00:06  steve
- *  Detect some hosts that do not support -rdynamic.
- *
- * Revision 1.15  2000/05/17 03:53:29  steve
- *  Add the module option to iverilog.
- *
- * Revision 1.14  2000/05/14 19:41:52  steve
- *  Fix -f flag handling.
- *
- * Revision 1.13  2000/05/13 20:55:47  steve
- *  Use yacc based synthesizer.
- *
- * Revision 1.12  2000/05/09 00:02:13  steve
- *  Parameterize LD lib in C++ command line.
- *
- * Revision 1.11  2000/05/05 01:07:42  steve
- *  Add the -I and -D switches to iverilog.
- *
- * Revision 1.10  2000/05/04 20:08:20  steve
- *  Tell ivlpp to generate line number directives.
- *
- * Revision 1.9  2000/05/03 22:14:31  steve
- *  More features of ivl available through iverilog.
- *
- * Revision 1.8  2000/05/01 23:55:22  steve
- *  Better inc and lib paths for iverilog.
- *
- * Revision 1.7  2000/04/29 01:20:14  steve
- *  The -f flag is now in place.
- *
- * Revision 1.6  2000/04/26 21:11:41  steve
- *  Mussed up command string mashing.
- *
- * Revision 1.5  2000/04/26 03:33:32  steve
- *  Do not set width too small to hold significant bits.
- *
- * Revision 1.4  2000/04/23 21:14:32  steve
- *  The -s flag.
- *
- * Revision 1.3  2000/04/21 22:54:47  steve
- *  module path in vvm target.
- *
- * Revision 1.2  2000/04/21 22:51:38  steve
- *  Support the -tnull target type.
- *
- * Revision 1.1  2000/04/21 06:41:03  steve
- *  Add the iverilog driver program.
- *
- */
-

iverilog.conf

@@ -0,0 +1,93 @@
+
+# The iverilog.conf configuration file provides to the iverilog driver
+# strings based on switches that are passed by the user on the command
+# line.
+#
+# Comments start from the hash (#) character and run to the end of the
+# line.
+#
+# Conditions are a list of requirements between [] characters. For the
+# set of patterns following a string to b activated, all the
+# conditions must be true. Valid conditions are:
+#
+#     -S          -- The -S flag is passed to iverilog
+#     -t<string>  -- The -t<string> parameters is passed to iverilog
+#
+#
+# Patterns have a name and text. The name has the form <key> where the
+# key is some key value that is required by iverilog. The commonly
+# used keys are:
+#
+#     <ivl>
+#	The string here is the command line needed to take the
+#       preprocessor output (ivlpp) and compile it with the
+#       target. All target types use this key.
+#
+# The pattern text includes %<code> substitutions. iverilog
+# substitutes values for the %<code> sequences within the text.
+#
+#     %B  Substitute the base libdir, -B flag of iverilog.
+#
+#     %C  Substitute the path to the temporary config file.
+#
+#     %f  Substitute the -f flags from the command line.
+#
+#     %g  Substitule the -g flag
+#
+#     %s  Substitute the start module (-s flag) from the user.
+#
+#     %M  Substitute the value of the -M<depfile> flag.
+#
+#     %N  Substitute the value of the -N<path> flag.
+#
+#     %o  Substitute the value of the -o<path> flag, or the default
+#         output path if there is no -o flag.
+#
+#     %T  Substitute min, typ or max depending on the -T flag from the
+#         command line.
+#
+#
+#     %W  Substitute the ivl warning flags.
+#
+#     %[<c><text>]
+#       This substitution pattern is magical, and is the only
+#       multicharacter pattern. This tests the code <c>, and
+#       substitutes <text> into the output only if <c> is true.
+#       The <text> may include further substitution strings, and is
+#       terminated by a ``]'' character.
+
+
+# This is the null (no op) target. Thre is a synthesis version and a
+# non-synthesis version. Normally, this does not matter, but this can
+# be useful and interesting if the -N flag is included.
+
+[-tnull -S]
+<ivl>%B/ivl %[v-v] -C%C %g %W %s %[M-M%M] %[N-N%N] %[T-T%T] -tdll -fDLL=%B/null.tgt -Fsynth -Fsyn-rules -- -
+
+[-tnull]
+<ivl>%B/ivl %[v-v] -C%C %g %W %s %[M-M%M] %[N-N%N] %[T-T%T] -tdll -fDLL=%B/null.tgt -- -
+
+# --
+# The vvp target generates code that the vvp simulation engine can execute.
+# These rules support synthesized and non-synthesized variants.
+
+[-tvvp -S]
+<ivl>%B/ivl %[v-v] -C%C %g %W %s %[M-M%M] %[N-N%N] %[T-T%T] -tdll -fDLL=%B/vvp.tgt -fVVP_EXECUTABLE=%B/../../bin/vvp -Fsynth2 -Fsynth -Fsyn-rules -Fcprop -Fnodangle %f %m -o%o -- -
+
+[-tvvp]
+<ivl>%B/ivl %[v-v] -C%C %g %W %s %[M-M%M] %[N-N%N] %[T-T%T] -tdll -fDLL=%B/vvp.tgt -fVVP_EXECUTABLE=%B/../../bin/vvp -Fcprop -Fnodangle %f %m -o%o -- -
+
+# This is the XNF code generator.
+
+[-txnf]
+<ivl>%B/ivl -C%C %[v-v] %g %s %[M-M%M] %[N-N%N] %[T-T%T] -txnf -Fsynth -Fsyn-rules -Fxnfio -Fcprop -Fnodangle -o%o -- -
+
+# And this is another XNF code generator, under development.
+[-tfpga]
+<ivl>%B/ivl -C%C %[v-v] %g %s %[M-M%M] %[N-N%N] %[T-T%T] %f -tdll -fDLL=%B/fpga.tgt -Fsynth2 -Fsynth -Fsyn-rules -Fcprop -Fnodangle -o%o -- -
+
+# --
+# This is the pal code generator. The target module requires the -fpart=<type>
+# flag to specify the part type.
+[-tpal]
+<ivl>%B/ivl -C%C %[v-v] %g %s %[M-M%M] %[N-N%N] %[T-T%T] %f -tdll -fDLL=%B/pal.tgt -Fsynth -Fsyn-rules -Fcprop -Fnodangle -o%o -- -

iverilog.man

@@ -1,156 +0,0 @@
-.TH iverilog 1 "$Date: 2000/05/17 03:53:29 $" Version "$Date: 2000/05/17 03:53:29 $"
-.SH NAME
-iverilog - Icarus Verilog compiler
-
-.SH SYNOPSIS
-.B iverilog
-[-ESv] [-Dmacro[=defn]] [-fflag=value] [-Iincludepath] [-mmodule] [-ooutputfilename] [-s topmodule] [-ttype] [-Wclass] sourcefile[s]
-
-.SH DESCRIPTION
-.PP
-\fIiverilog\fP is a compiler that translates Verilog source code into
-executable programs for simulation, or other netlist formats for
-further processing. The currenty supported targets are \fIvvm\fP (for
-executable simulation) and \fIxnf\fP for synthesis. Other target
-types are added as code generators are implemented.
-
-.SH OPTIONS
-.l
-\fIiverilog\fP accepts the following options:
-.TP 8
-.B -B\fIbase\fP
-The \fIiverilog\fP program uses external programs to preprocess and
-compile the verilog source. Normally, the path used to locate these
-tools is built into the \fIiverilog\fP program. However, the \fB-B\fP
-switch allows the user to select a different set of programs. The path
-given is used to locate \fIivlpp\fP, \fIivl\fP and the VPI modules.
-.TP 8
-.B -D\fImacro\fP
-Defines macro \fImacro\fP with the string `1' as its definition. This
-form is normally only used to trigger ifdef conditionals in the
-Verilog source.
-.TP 8
-.B -D\fImacro=defn\fP
-Defines macro \fImacro\fP as \fIdefn\fP.
-.TP 8
-.B -E
-Preprocess the Verilog source, but do not compile it. The output file
-is the Verilog input, but with file inclusions and macro references
-expanded and removed. This is useful, for example, to preprocess
-verilog source for use by other compilers.
-.TP 8
-.B -f\fIflag=value\fP
-Assign a value to a target specific flag. The \fB-f\fP switch may be
-used as often as necessary to specify all the desired flags. The flags
-that are used depend on the target that is selected, and are described
-in target specific documentation. Flags that are not used are ignored.
-.TP 8
-.B -I\fIincludedir\fP 
-Append directory \fIincludepdir\fP to list of directoriess searched
-for Verilog include files. The \fB-I\fP switch may be used many times
-to specify several directories to search, the directories are searched
-in the order they appear on the command line.
-.TP 8
-.B -m\fImodule\fP
-Add this module to the list of VPI modules to be loaded by the
-simulation. Many modules can be specified, and all will be loaded, in
-the order specified.
-.TP 8
-.B -o \fIfilename\fP
-Place output in the file \fIfilename\fP. If no output file name is
-specified, \fIiverilog\fP uses the default name \fBa.out\fP.
-.TP 8
-.B -S
-Synthesize. Normally, if the target can accept behavioral
-descriptions the compiler will leave processes in behavioral
-form. The \fB-S\fP switch causes the compiler to perform synthesis
-even if it is not necessary for the target. If the target type is a
-netlist format, the \fB-S\fP switch is unnecessary and has no effect.
-.TP 8
-.B -s \fItopmodule\fP
-Specify the top level module to elaborate. Icarus Verilog will by default
-choose the only module that has no ports. However, this simplistic
-heuristic is often not sufficient, and sometimes not what is wanted
-anyhow.
-.TP 8
-.B -t\fItarget\fP
-Use this switch to specify the target output format. See the
-\fBTARGETS\fP section below for a list of valid output formats.
-.TP 8
-.B -v
-Turn on verbose messages. This will print the command lines that are
-executed to perform the actual compilation, along with version
-information from the various components.
-.TP 8
-.B -W\fIclass\fP
-Turn on different classes of warnings. See the \fBWARNING TYPES\fP
-section below for desctriptions of the different warning groups. If
-multiple \fB-W\fP switches are used, the warning set is the union of
-all the requested classes.
-
-.SH TARGETS
-
-The Icarus Verilog compiler supports a variety of targets, for
-different purposes, and the \fB-t\fP switch is used to select the
-desired target.
-
-.TP 8
-.B null
-The null target causes no code to be generated. It is useful for
-checking the syntax of the Verilog source.
-.TP 8
-.B vvm
-This is the default. The target is an executable program that uses the
-vvm simulation runtime. The compiler actually generates C++ code, then
-compiles and links that code to make the output executable.
-.TP 8
-.B xnf
-This is the Xilinx Netlist Format used by many tools for placing
-devices in FPGAs or other programmable devices. The Icarus Verilog XNF
-code generator can generate complete designs or XNF macros that can be
-imported into larger designs by other tools.
-
-.SH "WARNING TYPES"
-These are the types of warnings that can be selected by the \fB-W\fP
-switch.
-
-.TP 8
-.B all
-This enables all supported warning categories.
-
-.TP 8
-.B implicit
-This enables warnings for creation of implicit declarations. For
-example, if a scaler wire X is used but not declared in the Verilog
-source, this will print a warning at its first use.
-
-.SH EXAMPLES 
-These examples assume that you have a Verilog source file called hello.v in
-the current directory
-
-To compile hello.v to an executable file called a.out:
-
-	verilog hello.v
-
-To compile hello.v to an executable file called hello:
-
-	verilog -o hello hello.v
-
-To compile hello.v to a file in XNF-format called hello.xnf
-
-	verilog -txnf -ohello.xnf hello.v
-
-
-.SH "AUTHOR"
-.nf
-Steve Williams ([email protected])
-
-.SH SEE ALSO
-.BR "<http://www.icarus.com/eda/verilog/>"
-
-.SH COPYRIGHT
-.nf
-Copyright \(co  2000 Stephen Williams
-
-This document can be freely redistributed according to the terms of the 
-GNU General Public License version 2.0

ivl.def

@@ -0,0 +1,176 @@
+EXPORTS
+
+ivl_design_const
+ivl_design_consts
+ivl_design_flag
+ivl_design_process
+ivl_design_root
+ivl_design_roots
+ivl_design_time_precision
+
+ivl_const_bits
+ivl_const_pin
+ivl_const_pins
+ivl_const_signed
+
+ivl_event_any
+ivl_event_basename
+ivl_event_name
+ivl_event_nany
+ivl_event_neg
+ivl_event_nneg
+ivl_event_npos
+ivl_event_pos
+
+ivl_expr_type
+ivl_expr_bits
+ivl_expr_def
+ivl_expr_lsi
+ivl_expr_memory
+ivl_expr_name
+ivl_expr_opcode
+ivl_expr_oper1
+ivl_expr_oper2
+ivl_expr_oper3
+ivl_expr_parm
+ivl_expr_parms
+ivl_expr_repeat
+ivl_expr_scope
+ivl_expr_signal
+ivl_expr_signed
+ivl_expr_string
+ivl_expr_uvalue
+ivl_expr_width
+
+ivl_logic_attr
+ivl_logic_attr_cnt
+ivl_logic_attr_val
+ivl_logic_delay
+ivl_logic_name
+ivl_logic_basename
+ivl_logic_scope
+ivl_logic_type
+ivl_logic_pin
+ivl_logic_pins
+ivl_logic_udp
+
+ivl_lpm_aset_value
+ivl_lpm_async_clr
+ivl_lpm_async_set
+ivl_lpm_basename
+ivl_lpm_clk
+ivl_lpm_data
+ivl_lpm_datab
+ivl_lpm_data2
+ivl_lpm_data2_width
+ivl_lpm_define
+ivl_lpm_enable
+ivl_lpm_memory
+ivl_lpm_name
+ivl_lpm_q
+ivl_lpm_scope
+ivl_lpm_select
+ivl_lpm_selects
+ivl_lpm_size
+ivl_lpm_type
+ivl_lpm_width
+
+ivl_lval_idx
+ivl_lval_mem
+ivl_lval_mux
+ivl_lval_part_off
+ivl_lval_pin
+ivl_lval_pins
+ivl_lval_sig
+
+ivl_memory_basename
+ivl_memory_root
+ivl_memory_scope
+ivl_memory_size
+ivl_memory_width
+
+ivl_nexus_get_private
+ivl_nexus_name
+ivl_nexus_ptrs
+ivl_nexus_ptr
+ivl_nexus_set_private
+
+ivl_nexus_ptr_con
+ivl_nexus_ptr_drive0
+ivl_nexus_ptr_drive1
+ivl_nexus_ptr_pin
+ivl_nexus_ptr_lpm
+ivl_nexus_ptr_log
+ivl_nexus_ptr_sig
+
+ivl_scope_basename
+ivl_scope_children
+ivl_scope_def
+ivl_scope_event
+ivl_scope_events
+ivl_scope_logs
+ivl_scope_log
+ivl_scope_lpms
+ivl_scope_lpm
+ivl_scope_mem
+ivl_scope_mems
+ivl_scope_name
+ivl_scope_parent
+ivl_scope_port
+ivl_scope_ports
+ivl_scope_sigs
+ivl_scope_sig
+ivl_scope_type
+ivl_scope_tname
+
+ivl_signal_attr
+ivl_signal_attr_cnt
+ivl_signal_attr_val
+ivl_signal_integer
+ivl_signal_local
+ivl_signal_pin
+ivl_signal_pins
+ivl_signal_port
+ivl_signal_signed
+ivl_signal_type
+ivl_signal_name
+ivl_signal_basename
+
+ivl_process_attr_cnt
+ivl_process_attr_val
+ivl_process_scope
+ivl_process_stmt
+ivl_process_type
+
+ivl_statement_type
+
+ivl_stmt_block_count
+ivl_stmt_block_scope
+ivl_stmt_block_stmt
+ivl_stmt_call
+ivl_stmt_case_count
+ivl_stmt_case_expr
+ivl_stmt_case_stmt
+ivl_stmt_cond_expr
+ivl_stmt_cond_false
+ivl_stmt_cond_true
+ivl_stmt_delay_expr
+ivl_stmt_delay_val
+ivl_stmt_event
+ivl_stmt_lval
+ivl_stmt_lvals
+ivl_stmt_lwidth
+ivl_stmt_name
+ivl_stmt_nexus
+ivl_stmt_nexus_count
+ivl_stmt_parm
+ivl_stmt_parm_count
+ivl_stmt_rval
+ivl_stmt_sub_stmt
+
+ivl_udp_init
+ivl_udp_name
+ivl_udp_nin
+ivl_udp_row
+ivl_udp_rows
+ivl_udp_sequ

ivl_target.txt

@@ -0,0 +1,51 @@
+
+Icarus Verilog LOADABLE TARGET API (ivl_target)
+
+  Copyright 2002 Stephen Williams <[email protected]>
+  $Id: ivl_target.txt,v 1.3 2002/06/11 03:34:33 steve Exp $
+
+
+The ivl_target API is the interface available to modules that the
+Icarus Verilog compiler loads to act as a code generator. The API
+provides an interface to the elaborated, possibly synthesized, design
+for code generators that are intended to write netlist files or
+executable programs.
+
+The functions and types of the API are summarized in the ivl_target.h
+header file. This document describes how the functions and types of
+the API are used to access and interpret the netlist of the design.
+
+
+LPM DEVICES
+
+All LPM devices support a small set of common LPM functions, as
+described in the ivl_target header file. The ivl_lpm_t object has a
+type enumerated by ivl_lpm_type_t, and that type is accessible via the
+ivl_lpm_type function.
+
+The following are type specific aspects of LPM devices.
+
+* IVL_LPM_UFUNC
+
+This LPM represents a user defined function. It is a way to connect
+behavioral code into a structural network. The UFUNC device has a
+vector output and a set of inputs. The ivl_lpm_define function returns
+the definition as an ivl_scope_t object.
+
+The output vector is accessible through the ivl_lpm_q, and the output
+has the width defined by ivl_lpm_width. This similar to most every
+other LPM device with outputs.
+
+There are ivl_lpm_size() input ports, each with the width
+ivl_lpm_data2_width(). The actual nexus is indexed by ivl_lpm_data2().
+
+$Log: ivl_target.txt,v $
+Revision 1.3  2002/06/11 03:34:33  steve
+ Spelling patch (Larry Doolittle)
+
+Revision 1.2  2002/03/17 19:31:17  steve
+ Add API to support user defined function.
+
+Revision 1.1  2002/03/09 02:10:22  steve
+ Add the NetUserFunc netlist node.
+