Allow sole module to be a root.
This commit is contained in:
steve
parent
f7d62b96aa
commit
c86da66b77
122
main.cc
122
main.cc
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@ -19,7 +19,7 @@ const char COPYRIGHT[] =
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT) && !defined(macintosh)
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#ident "$Id: main.cc,v 1.38 2000/09/12 01:17:40 steve Exp $"
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#ident "$Id: main.cc,v 1.39 2000/11/22 20:48:32 steve Exp $"
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#endif
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const char NOTICE[] =
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@ -247,6 +247,11 @@ int main(int argc, char*argv[])
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return rc;
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}
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/* If the user did not give a specific module to start with,
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then look for the single module that has no ports. If there
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are multiple modules with no ports, then give up. */
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if (start_module == "") {
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for (map<string,Module*>::iterator mod = modules.begin()
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; mod != modules.end()
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@ -263,20 +268,36 @@ int main(int argc, char*argv[])
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}
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}
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/* Select a root module, and elaborate the design. */
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/* If the previous attempt to find a start module failed, but
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there is only one module, then just let the user get away
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with it. */
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if ((start_module == "") && (modules.size() == 1)) {
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map<string,Module*>::iterator mod = modules.begin();
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Module*cur = (*mod).second;
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start_module = cur->get_name();
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}
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/* If there is *still* no guess for the root module, then give
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up completely, and complain. */
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if (start_module == "") {
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cerr << "No top level modules, and no -s option." << endl;
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return 1;
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}
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/* On with the process of elaborating the module. */
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Design*des = elaborate(modules, primitives, start_module);
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if (des == 0) {
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cerr << "Unable to elaborate module " << start_module <<
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"." << endl;
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cerr << start_module << ": error: "
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<< "Unable to elaborate module." << endl;
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return 1;
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}
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if (des->errors) {
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cerr << des->errors << " error(s) elaborating design." << endl;
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cerr << start_module << ": error: " << des->errors
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<< " elaborating module." << endl;
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return des->errors;
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}
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@ -306,6 +327,9 @@ int main(int argc, char*argv[])
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/*
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* $Log: main.cc,v $
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* Revision 1.39 2000/11/22 20:48:32 steve
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* Allow sole module to be a root.
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*
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* Revision 1.38 2000/09/12 01:17:40 steve
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* Version information for vlog_vpi_info.
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*
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@ -337,93 +361,5 @@ int main(int argc, char*argv[])
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* Get synthesis working with the NetEvWait class,
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* and get started supporting multiple events in a
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* wait in vvm.
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*
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* Revision 1.30 2000/03/17 21:50:25 steve
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* Switch to control warnings.
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*
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* Revision 1.29 2000/02/23 02:56:54 steve
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* Macintosh compilers do not support ident.
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*
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* Revision 1.28 2000/01/13 05:11:25 steve
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* Support for multiple VPI modules.
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*
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* Revision 1.27 1999/12/30 17:37:14 steve
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* Remove the now useless sigfold functor.
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*
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* Revision 1.26 1999/11/29 17:02:21 steve
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* include getopt if present.
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*
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* Revision 1.25 1999/11/18 03:52:19 steve
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* Turn NetTmp objects into normal local NetNet objects,
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* and add the nodangle functor to clean up the local
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* symbols generated by elaboration and other steps.
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*
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* Revision 1.24 1999/11/01 02:07:40 steve
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* Add the synth functor to do generic synthesis
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* and add the LPM_FF device to handle rows of
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* flip-flops.
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*
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* Revision 1.23 1999/09/22 16:57:23 steve
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* Catch parallel blocks in vvm emit.
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*
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* Revision 1.22 1999/08/03 04:14:49 steve
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* Parse into pform arbitrarily complex module
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* port declarations.
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*
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* Revision 1.21 1999/07/18 05:52:46 steve
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* xnfsyn generates DFF objects for XNF output, and
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* properly rewrites the Design netlist in the process.
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*
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* Revision 1.20 1999/07/17 22:01:13 steve
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* Add the functor interface for functor transforms.
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*
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* Revision 1.19 1999/07/10 23:29:21 steve
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* pform even on parse errors.
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*
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* Revision 1.18 1999/06/19 03:46:42 steve
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* Add the -v switch.
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*
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* Revision 1.17 1999/06/17 05:33:12 steve
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* Redundant declaration of pform_parse.
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*
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* Revision 1.16 1999/06/15 03:44:53 steve
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* Get rid of the STL vector template.
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*
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* Revision 1.15 1999/05/05 03:27:15 steve
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* More intelligent selection of module to elaborate.
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*
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* Revision 1.14 1999/04/23 04:34:32 steve
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* Make debug output file parameters.
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*
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* Revision 1.13 1999/02/01 00:26:49 steve
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* Carry some line info to the netlist,
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* Dump line numbers for processes.
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* Elaborate prints errors about port vector
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* width mismatch
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* Emit better handles null statements.
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*
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* Revision 1.12 1999/01/24 01:35:36 steve
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* Support null target for generating no output.
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*
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* Revision 1.11 1998/12/20 02:05:41 steve
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* Function to calculate wire initial value.
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*
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* Revision 1.10 1998/12/09 04:02:47 steve
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* Support the include directive.
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*
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* Revision 1.9 1998/12/07 04:53:17 steve
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* Generate OBUF or IBUF attributes (and the gates
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* to garry them) where a wire is a pad. This involved
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* figuring out enough of the netlist to know when such
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* was needed, and to generate new gates and signales
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* to handle what's missing.
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*
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* Revision 1.8 1998/12/02 04:37:13 steve
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* Add the nobufz function to eliminate bufz objects,
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* Object links are marked with direction,
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* constant propagation is more careful will wide links,
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* Signal folding is aware of attributes, and
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* the XNF target can dump UDP objects based on LCA
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* attributes.
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*/
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