Update to 0.7 release.

and bump the vpithunk magic number.

.cvsignore

@@ -2,10 +2,14 @@ lexor_keyword.cc
 parse.h
 parse.cc
 parse.cc.output
+parse.output
 syn-rules.cc
 syn-rules.cc.output
+syn-rules.output
 lexor.cc
 iverilog-vpi
+iverilog-vpi.pdf
+iverilog-vpi.ps
 ivl
 ivl.exp
 dep

Attrib.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT)
-#ident "$Id: Attrib.cc,v 1.4 2002/05/26 01:39:02 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: Attrib.cc,v 1.5 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include "config.h"
@@ -123,6 +123,9 @@ const verinum& Attrib::attr_value(unsigned idx) const
 
 /*
  * $Log: Attrib.cc,v $
+ * Revision 1.5  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.4  2002/05/26 01:39:02  steve
  *  Carry Verilog 2001 attributes with processes,
  *  all the way through to the ivl_target API.

Attrib.h

@@ -18,8 +18,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT)
-#ident "$Id: Attrib.h,v 1.3 2002/05/26 01:39:02 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: Attrib.h,v 1.4 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include  <string>
@@ -62,6 +62,9 @@ class Attrib {
 
 /*
  * $Log: Attrib.h,v $
+ * Revision 1.4  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.3  2002/05/26 01:39:02  steve
  *  Carry Verilog 2001 attributes with processes,
  *  all the way through to the ivl_target API.

HName.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT)
-#ident "$Id: HName.cc,v 1.3 2002/01/05 04:36:06 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: HName.cc,v 1.5 2002/11/02 03:27:52 steve Exp $"
 #endif
 
 # include  "config.h"
@@ -75,6 +75,11 @@ hname_t::~hname_t()
       }
 }
 
+unsigned hname_t::component_count() const
+{
+      return count_;
+}
+
 void hname_t::append(const char*text)
 {
       char**tmp;
@@ -253,6 +258,13 @@ ostream& operator<< (ostream&out, const hname_t&that)
 
 /*
  * $Log: HName.cc,v $
+ * Revision 1.5  2002/11/02 03:27:52  steve
+ *  Allow named events to be referenced by
+ *  hierarchical names.
+ *
+ * Revision 1.4  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.3  2002/01/05 04:36:06  steve
  *  include malloc.h only when available.
  *

HName.h

@@ -18,14 +18,15 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT)
-#ident "$Id: HName.h,v 1.1 2001/12/03 04:47:14 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: HName.h,v 1.4 2002/11/02 03:27:51 steve Exp $"
 #endif
 
-#ifdef HAVE_IOSFWD
-# include  <iosfwd>
-#else
-class ostream;
+# include  <iostream>
+#ifdef __GNUC__
+#if __GNUC__ > 2
+using namespace std;
+#endif
 #endif
 
 /*
@@ -60,6 +61,10 @@ class hname_t {
       const char*peek_name(unsigned idx) const;
       const char*peek_tail_name() const;
 
+	// Return the number of components in the hierarchical
+	// name. If this is a simple name, this will return 1.
+      unsigned component_count() const;
+
       friend ostream& operator<< (ostream&, const hname_t&);
 
     private:
@@ -78,6 +83,16 @@ extern bool operator == (const hname_t&, const hname_t&);
 
 /*
  * $Log: HName.h,v $
+ * Revision 1.4  2002/11/02 03:27:51  steve
+ *  Allow named events to be referenced by
+ *  hierarchical names.
+ *
+ * Revision 1.3  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.2  2002/06/14 03:25:51  steve
+ *  Compiler portability.
+ *
  * Revision 1.1  2001/12/03 04:47:14  steve
  *  Parser and pform use hierarchical names as hname_t
  *  objects instead of encoded strings.

LineInfo.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: LineInfo.cc,v 1.2 2001/07/25 03:10:48 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: LineInfo.cc,v 1.3 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include "config.h"
@@ -44,6 +44,9 @@ void LineInfo::set_line(const LineInfo&that)
 
 /*
  * $Log: LineInfo.cc,v $
+ * Revision 1.3  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.2  2001/07/25 03:10:48  steve
  *  Create a config.h.in file to hold all the config
  *  junk, and support gcc 3.0. (Stephan Boettcher)

LineInfo.h

@@ -18,8 +18,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: LineInfo.h,v 1.5 2000/11/30 17:31:42 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: LineInfo.h,v 1.6 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include  <string>
@@ -52,6 +52,9 @@ class LineInfo {
 
 /*
  * $Log: LineInfo.h,v $
+ * Revision 1.6  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.5  2000/11/30 17:31:42  steve
  *  Change LineInfo to store const C strings.
  *

Makefile.in

@@ -16,7 +16,7 @@
 #    59 Temple Place - Suite 330
 #    Boston, MA 02111-1307, USA
 #
-#ident "$Id: Makefile.in,v 1.125 2002/05/28 05:21:30 steve Exp $"
+#ident "$Id: Makefile.in,v 1.140 2002/12/10 05:45:44 steve Exp $"
 #
 #
 SHELL = /bin/sh
@@ -25,7 +25,7 @@ SHELL = /bin/sh
 # by the compiler. It reflects the assigned version number for the
 # product as a whole. Most components also print the CVS Name: token
 # in order to get a more automatic version stamp as well.
-VERSION = 0.6
+VERSION = 0.7
 
 prefix = @prefix@
 exec_prefix = @exec_prefix@
@@ -67,12 +67,8 @@ ifeq ('@HAVE_IPAL@','yes')
 TARGETS += tgt-pal
 endif
 
-ifeq (@ENABLE_VVM@,yes)
-SUB_VVM = vvm
-endif
-
 all: ivl@EXEEXT@ libvpi.a
-	for dir in $(SUBDIRS) $(SUB_VVM); do (cd $$dir ; $(MAKE) all); done
+	for dir in $(SUBDIRS) ; do (cd $$dir ; $(MAKE) all); done
 	cd vpi ; $(MAKE) all
 	cd ivlpp ; $(MAKE) all
 	cd driver ; $(MAKE) VERSION=$(VERSION) all
@@ -87,6 +83,10 @@ all: dosify.exe
 dosify.exe: dosify.c
 	$(CC) -o dosify.exe dosify.c
 
+ifeq (@MINGW32@,yes)
+SUBDIRS += driver-vpi
+endif
+
 else
 all: iverilog-vpi
 endif
@@ -105,40 +105,36 @@ clean:
 	cd ivlpp ; $(MAKE) clean
 	cd tgt-verilog ; $(MAKE) clean
 	cd tgt-stub ; $(MAKE) clean
-	for dir in $(SUBDIRS) $(SUB_VVM); do (cd $$dir ; $(MAKE) clean); done
+	for dir in $(SUBDIRS); do (cd $$dir ; $(MAKE) clean); done
 	for tgt in $(TARGETS); do (cd $$tgt ; $(MAKE) clean); done
 
 distclean: clean
-	for dir in $(SUBDIRS) $(SUB_VVM); do (cd $$dir ; $(MAKE) distclean); done
+	for dir in $(SUBDIRS); do (cd $$dir ; $(MAKE) distclean); done
 	for tgt in $(TARGETS); do (cd $$tgt ; $(MAKE) distclean); done
-	rm -f vvm/Makefile
 	rm -f vpi/Makefile
 	rm -f ivlpp/Makefile
 	rm -f driver/Makefile
 	rm -f config.status config.cache config.log
 	rm -f Makefile
+	rm -f tgt-pal/Makefile tgt-stub/Makefile tgt-verilog/Makefile
 
-ifeq (@ENABLE_VVM@,yes)
-TT_VVM = mangle.o t-vvm.o
-endif
+TT = t-dll.o t-dll-api.o t-dll-expr.o t-dll-proc.o t-xnf.o
+FF = cprop.o nodangle.o synth.o synth2.o syn-rules.o xnfio.o
 
-TT = t-dll.o t-dll-api.o t-dll-expr.o t-dll-proc.o $(TT_VVM) t-xnf.o
-FF = nodangle.o synth.o syn-rules.o xnfio.o
-
-O = main.o cprop.o design_dump.o dup_expr.o elaborate.o elab_expr.o \
+O = main.o async.o design_dump.o dup_expr.o elaborate.o elab_expr.o \
 elab_lval.o elab_net.o elab_anet.o elab_pexpr.o elab_scope.o \
 elab_sig.o emit.o eval.o eval_attrib.o eval_rconst.o \
 eval_tree.o expr_synth.o functor.o lexor.o lexor_keyword.o link_const.o \
 load_module.o netlist.o netmisc.o net_assign.o \
 net_design.o net_event.o net_expr.o net_force.o net_func.o \
-net_link.o net_modulo.o net_nex_input.o \
+net_link.o net_modulo.o net_nex_input.o net_nex_output.o \
 net_proc.o net_scope.o net_udp.o pad_to_width.o \
 parse.o parse_misc.o pform.o pform_dump.o \
-set_width.o \
+set_width.o sync.o \
 verinum.o verireal.o target.o targets.o \
 Attrib.o HName.o LineInfo.o Module.o PDelays.o PEvent.o \
 PExpr.o PGate.o \
-PTask.o PFunction.o PWire.o Statement.o \
+PTask.o PFunction.o PWire.o Statement.o StringHeap.o \
 $(FF) $(TT)
 
 Makefile: Makefile.in config.h.in config.status
@@ -178,13 +174,14 @@ ifeq (@WIN32@,yes)
 
 else
 iverilog-vpi: iverilog-vpi.sh
-	sed -e 's;@SHARED@;@shared@;' -e 's;@PIC@;@PICFLAG@;' $< > $@
+	sed -e 's;@SHARED@;@shared@;' -e 's;@PIC@;@PICFLAG@;' \
+	    -e 's;@INCLUDEDIR@;@includedir@;' -e 's;@LIBDIR@;@libdir@;' $< > $@
 	chmod +x $@
 endif
 
 %.o: %.cc
 	@[ -d dep ] || mkdir dep
-	$(CXX) $(CPPFLAGS) $(CXXFLAGS) -MD -c $< -o $*.o
+	$(CXX) @ident_support@ $(CPPFLAGS) $(CXXFLAGS) -MD -c $< -o $*.o
 	mv $*.d dep/$*.d
 
 
@@ -223,7 +220,7 @@ INSTALL_DOCDIR = $(mandir)/man1
 endif
 
 ifeq (@WIN32@,yes)
-WIN32_INSTALL = $(prefix)/hello.vl $(prefix)/sqrt.vl $(prefix)/QUICK_START.txt
+WIN32_INSTALL = $(prefix)/hello.vl $(prefix)/sqrt.vl $(prefix)/sqrt-virtex.v $(prefix)/QUICK_START.txt
 else
 WIN32_INSTALL = $(bindir)/iverilog-vpi
 endif
@@ -232,11 +229,11 @@ install: all installdirs $(libdir)/ivl/ivl@EXEEXT@ $(libdir)/ivl/iverilog.conf $
 	cd vpi ; $(MAKE) install
 	cd ivlpp ; $(MAKE) install
 	cd driver ; $(MAKE) install
-	for tgt in $(SUBDIRS) $(SUB_VVM); do (cd $$tgt ; $(MAKE) install); done
+	for tgt in $(SUBDIRS); do (cd $$tgt ; $(MAKE) install); done
 	for tgt in $(TARGETS); do (cd $$tgt ; $(MAKE) install); done
 
 $(bindir)/iverilog-vpi: ./iverilog-vpi
-	$(INSTALL_PROGRAM) ./iverilog-vpi $(bindir)/iverilog-vpi
+	$(INSTALL_SCRIPT) ./iverilog-vpi $(bindir)/iverilog-vpi
 
 $(libdir)/libvpi.a : ./libvpi.a
 	$(INSTALL_DATA) libvpi.a $(libdir)/libvpi.a
@@ -245,7 +242,10 @@ $(libdir)/ivl/ivl@EXEEXT@: ./ivl@EXEEXT@
 	$(INSTALL_PROGRAM) ./ivl@EXEEXT@ $(libdir)/ivl/ivl@EXEEXT@
 	$(STRIP) $(strip_dynamic) $(libdir)/ivl/ivl@EXEEXT@
 
-$(libdir)/ivl/iverilog.conf: $(srcdir)/iverilog.conf
+# Install iverilog.conf whenever ivl.exe is installed. This
+# forces iverilog.conf to be treated similarly, in spite of
+# dates in the source bundle.
+$(libdir)/ivl/iverilog.conf: $(libdir)/ivl/ivl@EXEEXT@
 	$(INSTALL_DATA) $(srcdir)/iverilog.conf $(libdir)/ivl/iverilog.conf
 
 $(includedir)/ivl_target.h: $(srcdir)/ivl_target.h
@@ -277,27 +277,36 @@ $(prefix)/sqrt.vl: $(srcdir)/examples/sqrt.vl
 	./dosify.exe $(srcdir)/examples/sqrt.vl tmp.vl
 	mv tmp.vl $(prefix)/sqrt.vl
 
+$(prefix)/sqrt-virtex.v: $(srcdir)/examples/sqrt-virtex.v
+	./dosify.exe $(srcdir)/examples/sqrt-virtex.v tmp.vl
+	mv tmp.vl $(prefix)/sqrt-virtex.v
+
 $(prefix)/QUICK_START.txt: $(srcdir)/QUICK_START.txt
 	./dosify.exe $(srcdir)/QUICK_START.txt tmp.txt
 	mv tmp.txt $(prefix)/QUICK_START.txt
 endif
 
 installdirs: mkinstalldirs
-	$(srcdir)/mkinstalldirs $(bindir) $(includedir) $(libdir)/ivl
-
+	$(srcdir)/mkinstalldirs $(bindir) $(includedir) $(libdir)/ivl \
+	    $(mandir) $(mandir)/man1
 
 uninstall:
-	rm -f $(libdir)/ivl/ivl@EXEEXT@
+	rm -f $(libdir)/ivl/iverilog.conf
+	rm -f $(libdir)/ivl/ivl
+	-rmdir $(libdir)/ivl
+	rm -f $(libdir)/libvpi.a
 	rm -f $(bindir)/verilog
+	rm -f $(bindir)/iverilog-vpi
 	rm -f $(bindir)/gverilog@EXEEXT@
 	rm -f $(includedir)/ivl_target.h
 	rm -f $(includedir)/vpi_user.h
 	rm -f $(includedir)/acc_user.h
 	rm -f $(includedir)/veriuser.h
+	rm -f $(mandir)/man1/iverilog-vpi.1
 	cd driver ; $(MAKE) uninstall
 	cd vpi ; $(MAKE) uninstall
 	cd ivlpp ; $(MAKE) uninstall
-	for tgt in $(SUBDIRS) $(SUB_VVM); do (cd $$tgt ; $(MAKE) uninstall); done
+	for tgt in $(SUBDIRS); do (cd $$tgt ; $(MAKE) uninstall); done
 	for tgt in $(TARGETS); do (cd $$tgt ; $(MAKE) uninstall); done
 
 

Module.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: Module.cc,v 1.18 2002/05/19 23:37:28 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: Module.cc,v 1.19 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include "config.h"
@@ -139,6 +139,9 @@ const list<PProcess*>& Module::get_behaviors() const
 
 /*
  * $Log: Module.cc,v $
+ * Revision 1.19  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.18  2002/05/19 23:37:28  steve
  *  Parse port_declaration_lists from the 2001 Standard.
  *

Module.h

@@ -18,8 +18,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: Module.h,v 1.25 2002/05/19 23:37:28 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: Module.h,v 1.27 2002/08/19 02:39:16 steve Exp $"
 #endif
 
 # include  <list>
@@ -67,8 +67,14 @@ class Module : public LineInfo {
 	/* The module has parameters that are evaluated when the
 	   module is elaborated. During parsing, I put the parameters
 	   into this map. */
-      map<string,PExpr*>parameters;
-      map<string,PExpr*>localparams;
+      struct param_expr_t {
+	    PExpr*expr;
+	    PExpr*msb;
+	    PExpr*lsb;
+	    bool signed_flag;
+      };
+      map<string,param_expr_t>parameters;
+      map<string,param_expr_t>localparams;
 
 	/* The module also has defparam assignments which don't create
 	   new parameters within the module, but may be used to set
@@ -145,6 +151,12 @@ class Module : public LineInfo {
 
 /*
  * $Log: Module.h,v $
+ * Revision 1.27  2002/08/19 02:39:16  steve
+ *  Support parameters with defined ranges.
+ *
+ * Revision 1.26  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.25  2002/05/19 23:37:28  steve
  *  Parse port_declaration_lists from the 2001 Standard.
  *

PDelays.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PDelays.cc,v 1.8 2001/12/29 20:19:31 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PDelays.cc,v 1.9 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include "config.h"
@@ -131,6 +131,9 @@ void PDelays::eval_delays(Design*des, NetScope*scope,
 
 /*
  * $Log: PDelays.cc,v $
+ * Revision 1.9  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.8  2001/12/29 20:19:31  steve
  *  Do not delete delay expressions of UDP instances.
  *

PDelays.h

@@ -1,7 +1,7 @@
 #ifndef __PDelays_H
 #define __PDelays_H
 /*
- * Copyright (c) 1999 Stephen Williams ([email protected])
+ * Copyright (c) 1999-2002 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -18,17 +18,18 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PDelays.h,v 1.5 2001/12/29 20:19:31 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PDelays.h,v 1.7 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include  "svector.h"
 # include  <string>
+# include  <iostream>
 
-#ifdef HAVE_IOSFWD
-# include  <iosfwd>
-#else
-class ostream;
+#ifdef __GNUC__
+#if __GNUC__ > 2
+using namespace std;
+#endif
 #endif
 
 class Design;
@@ -71,6 +72,12 @@ ostream& operator << (ostream&o, const PDelays&);
 
 /*
  * $Log: PDelays.h,v $
+ * Revision 1.7  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.6  2002/06/14 03:25:51  steve
+ *  Compiler portability.
+ *
  * Revision 1.5  2001/12/29 20:19:31  steve
  *  Do not delete delay expressions of UDP instances.
  *

PEvent.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PEvent.cc,v 1.2 2001/07/25 03:10:48 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PEvent.cc,v 1.3 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include "config.h"
@@ -40,6 +40,9 @@ string PEvent::name() const
 
 /*
  * $Log: PEvent.cc,v $
+ * Revision 1.3  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.2  2001/07/25 03:10:48  steve
  *  Create a config.h.in file to hold all the config
  *  junk, and support gcc 3.0. (Stephan Boettcher)

PEvent.h

@@ -18,8 +18,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PEvent.h,v 1.5 2001/12/03 04:47:14 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PEvent.h,v 1.6 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include  "LineInfo.h"
@@ -53,6 +53,9 @@ class PEvent : public LineInfo {
 
 /*
  * $Log: PEvent.h,v $
+ * Revision 1.6  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.5  2001/12/03 04:47:14  steve
  *  Parser and pform use hierarchical names as hname_t
  *  objects instead of encoded strings.

PExpr.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PExpr.cc,v 1.29 2001/12/30 21:32:03 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PExpr.cc,v 1.32 2002/11/09 19:20:48 steve Exp $"
 #endif
 
 # include "config.h"
@@ -46,7 +46,7 @@ bool PExpr::is_constant(Module*) const
       return false;
 }
 
-NetNet* PExpr::elaborate_lnet(Design*des, NetScope*) const
+NetNet* PExpr::elaborate_lnet(Design*des, NetScope*, bool) const
 {
       cerr << get_line() << ": error: expression not valid in assign l-value: "
 	   << *this << endl;
@@ -161,12 +161,12 @@ bool PEIdent::is_constant(Module*mod) const
 {
       if (mod == 0) return false;
 
-      { map<string,PExpr*>::const_iterator cur;
+      { map<string,Module::param_expr_t>::const_iterator cur;
         cur = mod->parameters.find(path_.peek_name(0));
 	if (cur != mod->parameters.end()) return true;
       }
 
-      { map<string,PExpr*>::const_iterator cur;
+      { map<string,Module::param_expr_t>::const_iterator cur;
         cur = mod->localparams.find(path_.peek_name(0));
 	if (cur != mod->localparams.end()) return true;
       }
@@ -256,6 +256,15 @@ bool PEUnary::is_constant(Module*m) const
 
 /*
  * $Log: PExpr.cc,v $
+ * Revision 1.32  2002/11/09 19:20:48  steve
+ *  Port expressions for output ports are lnets, not nets.
+ *
+ * Revision 1.31  2002/08/19 02:39:16  steve
+ *  Support parameters with defined ranges.
+ *
+ * Revision 1.30  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.29  2001/12/30 21:32:03  steve
  *  Support elaborate_net for PEString objects.
  *

PExpr.h

@@ -18,8 +18,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PExpr.h,v 1.60 2002/05/23 03:08:51 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PExpr.h,v 1.63 2002/11/09 19:20:48 steve Exp $"
 #endif
 
 # include  <string>
@@ -80,7 +80,8 @@ class PExpr : public LineInfo {
 
 	// This method elaborates the expression as gates, but
 	// restricted for use as l-values of continuous assignments.
-      virtual NetNet* elaborate_lnet(Design*des, NetScope*scope) const;
+      virtual NetNet* elaborate_lnet(Design*des, NetScope*scope,
+				     bool implicit_net_ok =false) const;
 
 	// Expressions that can be in the l-value of procedural
 	// assignments can be elaborated with this method.
@@ -126,7 +127,8 @@ class PEConcat : public PExpr {
 	// continuous assignments.
       virtual NetNet* elaborate_anet(Design*des, NetScope*scope) const;
 
-      virtual NetNet* elaborate_lnet(Design*des, NetScope*scope) const;
+      virtual NetNet* elaborate_lnet(Design*des, NetScope*scope,
+				     bool implicit_net_ok =false) const;
       virtual NetNet* elaborate_net(Design*des, NetScope*scope,
 				    unsigned width,
 				    unsigned long rise,
@@ -216,7 +218,8 @@ class PEIdent : public PExpr {
       virtual NetNet* elaborate_anet(Design*des, NetScope*scope) const;
 
 	// Identifiers are allowed (with restrictions) is assign l-values.
-      virtual NetNet* elaborate_lnet(Design*des, NetScope*scope) const;
+      virtual NetNet* elaborate_lnet(Design*des, NetScope*scope,
+				     bool implicit_net_ok =false) const;
 
 	// Identifiers are also allowed as procedural assignment l-values.
       virtual NetAssign_* elaborate_lval(Design*des, NetScope*scope) const;
@@ -270,6 +273,10 @@ class PEIdent : public PExpr {
 				    Link::strength_t drive0,
 				    Link::strength_t drive1) const;
 
+    private:
+      NetAssign_* elaborate_mem_lval_(Design*des, NetScope*scope,
+				      NetMemory*mem) const;
+
 };
 
 class PENumber : public PExpr {
@@ -497,6 +504,17 @@ class PECallFunction : public PExpr {
 
 /*
  * $Log: PExpr.h,v $
+ * Revision 1.63  2002/11/09 19:20:48  steve
+ *  Port expressions for output ports are lnets, not nets.
+ *
+ * Revision 1.62  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.61  2002/06/04 05:38:43  steve
+ *  Add support for memory words in l-value of
+ *  blocking assignments, and remove the special
+ *  NetAssignMem class.
+ *
  * Revision 1.60  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute

PFunction.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PFunction.cc,v 1.5 2001/07/25 03:10:48 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PFunction.cc,v 1.6 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include "config.h"
@@ -54,6 +54,9 @@ void PFunction::set_output(PWire*o)
 
 /*
  * $Log: PFunction.cc,v $
+ * Revision 1.6  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.5  2001/07/25 03:10:48  steve
  *  Create a config.h.in file to hold all the config
  *  junk, and support gcc 3.0. (Stephan Boettcher)

PGate.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PGate.cc,v 1.13 2001/11/22 06:20:59 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PGate.cc,v 1.14 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include "config.h"
@@ -192,6 +192,9 @@ const char* PGModule::get_type()
 
 /*
  * $Log: PGate.cc,v $
+ * Revision 1.14  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.13  2001/11/22 06:20:59  steve
  *  Use NetScope instead of string for scope path.
  *

PGate.h

@@ -18,8 +18,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PGate.h,v 1.23 2002/05/23 03:08:51 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PGate.h,v 1.24 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include  "svector.h"
@@ -222,6 +222,9 @@ class PGModule  : public PGate {
 
 /*
  * $Log: PGate.h,v $
+ * Revision 1.24  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.23  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute

PTask.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PTask.cc,v 1.6 2001/07/25 03:10:48 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PTask.cc,v 1.7 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include "config.h"
@@ -48,6 +48,9 @@ void PTask::set_statement(Statement*s)
 
 /*
  * $Log: PTask.cc,v $
+ * Revision 1.7  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.6  2001/07/25 03:10:48  steve
  *  Create a config.h.in file to hold all the config
  *  junk, and support gcc 3.0. (Stephan Boettcher)

PTask.h

@@ -18,8 +18,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PTask.h,v 1.11 2001/11/22 06:20:59 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PTask.h,v 1.12 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include  "LineInfo.h"
@@ -98,6 +98,9 @@ class PFunction : public LineInfo {
 
 /*
  * $Log: PTask.h,v $
+ * Revision 1.12  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.11  2001/11/22 06:20:59  steve
  *  Use NetScope instead of string for scope path.
  *

PUdp.h

@@ -18,8 +18,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PUdp.h,v 1.6 2002/05/23 03:08:51 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PUdp.h,v 1.7 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include  <map>
@@ -84,6 +84,9 @@ class PUdp {
 
 /*
  * $Log: PUdp.h,v $
+ * Revision 1.7  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.6  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute

PWire.cc

@@ -16,23 +16,34 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PWire.cc,v 1.8 2002/01/26 05:28:28 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PWire.cc,v 1.10 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include "config.h"
-
 # include  "PWire.h"
 # include  <assert.h>
 
 PWire::PWire(const hname_t&n, NetNet::Type t, NetNet::PortType pt)
-: hname_(n), type_(t), port_type_(pt), signed_(false), lidx_(0), ridx_(0)
+: hname_(n), type_(t), port_type_(pt), signed_(false), isint_(false),
+lidx_(0), ridx_(0)
 {
+      if (t == NetNet::INTEGER) {
+	    type_ = NetNet::REG;
+	    signed_ = true;
+	    isint_ = true;
+      }
 }
 
 PWire::PWire(char*n, NetNet::Type t, NetNet::PortType pt)
-: hname_(n), type_(t), port_type_(pt), signed_(false), lidx_(0), ridx_(0)
+: hname_(n), type_(t), port_type_(pt), signed_(false), isint_(false),
+lidx_(0), ridx_(0)
 {
+      if (t == NetNet::INTEGER) {
+	    type_ = NetNet::REG;
+	    signed_ = true;
+	    isint_ = true;
+      }
 }
 
 NetNet::Type PWire::get_wire_type() const
@@ -57,6 +68,10 @@ bool PWire::set_wire_type(NetNet::Type t)
 	    if (t == NetNet::REG) { type_ = t; return true; }
 	    return false;
 	  case NetNet::REG:
+	    if (t == NetNet::INTEGER) {
+		  isint_ = true;
+		  return true;
+	    }
 	    if (t == NetNet::REG) return true;
 	    return false;
 	  default:
@@ -103,6 +118,11 @@ bool PWire::get_signed() const
       return signed_;
 }
 
+bool PWire::get_isint() const
+{
+      return isint_;
+}
+
 void PWire::set_range(PExpr*m, PExpr*l)
 {
       msb_ = svector<PExpr*>(msb_,m);
@@ -120,6 +140,12 @@ void PWire::set_memory_idx(PExpr*ldx, PExpr*rdx)
 
 /*
  * $Log: PWire.cc,v $
+ * Revision 1.10  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.9  2002/06/21 04:59:35  steve
+ *  Carry integerness throughout the compilation.
+ *
  * Revision 1.8  2002/01/26 05:28:28  steve
  *  Detect scalar/vector declarion mismatch.
  *

PWire.h

@@ -18,8 +18,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: PWire.h,v 1.12 2002/05/23 03:08:51 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: PWire.h,v 1.14 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include  "netlist.h"
@@ -64,6 +64,7 @@ class PWire : public LineInfo {
 
       void set_signed(bool flag);
       bool get_signed() const;
+      bool get_isint() const;
 
       void set_range(PExpr*msb, PExpr*lsb);
 
@@ -81,6 +82,7 @@ class PWire : public LineInfo {
       NetNet::Type type_;
       NetNet::PortType port_type_;
       bool signed_;
+      bool isint_;		// original type of integer
 
 	// These members hold expressions for the bit width of the
 	// wire. If they do not exist, the wire is 1 bit wide.
@@ -99,6 +101,12 @@ class PWire : public LineInfo {
 
 /*
  * $Log: PWire.h,v $
+ * Revision 1.14  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.13  2002/06/21 04:59:35  steve
+ *  Carry integerness throughout the compilation.
+ *
  * Revision 1.12  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute

README.txt

@@ -39,7 +39,7 @@ on a UNIX-like system:
 	- GNU Make
 	  The Makefiles use some GNU extensions, so a basic POSIX
 	  make will not work. Linux systems typically come with a
-	  satisfactory make. BSD based systems (i.e. NetBSD, FreeBSD)
+	  satisfactory make. BSD based systems (i.e., NetBSD, FreeBSD)
 	  typically have GNU make as the gmake program.
 
 	- ISO C++ Compiler
@@ -152,10 +152,10 @@ The elaborate() function performs the elaboration.
 
 One can see a human readable version of the final, elaborated and
 optimized netlist by using the ``-N <path>'' flag to the compiler. If
-elaboration succeeds, the final netlist (i.e. after optimizations but
+elaboration succeeds, the final netlist (i.e., after optimizations but
 before code generation) will be dumped into the file named <path>.
 
-Elaboration is actually performed it two steps: scopes and parameters
+Elaboration is actually performed in two steps: scopes and parameters
 first, followed by the structural and behavioral elaboration.
 
 3.3.1 Scope Elaboration
@@ -184,19 +184,19 @@ simply passing through the pform.
 
 This is actually a collection of processing steps that perform
 optimizations that do not depend on the target technology. Examples of
-some useful transformations would be,
+some useful transformations are
 
-	- eliminate null effect circuitry,
+	- eliminate null effect circuitry
 	- combinational reduction
 	- constant propagation
 
 The actual functions performed are specified on the ivl command line by
-the -F flags (See below).
+the -F flags (see below).
 
 3.5 Code Generation
 
 This step takes the design netlist and uses it to drive the code
-generator. (See target.h.) This may require transforming the
+generator (see target.h). This may require transforming the
 design to suit the technology.
 
 The emit() method of the Design class performs this step. It runs
@@ -208,6 +208,9 @@ command line.
 
 3.6 ATTRIBUTES
 
+    NOTE: The $attribute syntax will soon be deprecated in favor of the
+    Verilog-2001 attribute syntax, which is cleaner and standardized.
+
 The parser accepts, as an extension to Verilog, the $attribute module
 item. The syntax of the $attribute item is:
 
@@ -266,7 +269,7 @@ endmodule
 
 --------------------------------------------------------------
 
-Insure that "iverilog" is on your search path, and the vpi library 
+Ensure that "iverilog" is on your search path, and the vpi library 
 is available.
 
 To compile the program:
@@ -304,8 +307,25 @@ constructs.
 
   - trireg is not supported. tri0 and tri1 are supported.
 
-  - force to nets are not supported. Force to variables, and
-    assign/deassign, are supported.
+  - tran primitives, i.e. tran, tranif1, tranif0, rtran, rtranif1
+    and rtranif0 are not supported.
+
+  - Module instance arrays are not supported, although gate instance
+    arrays do work.
+
+  - Net delays, of the form "wire #N foo;" do not work. Delays in
+    every other context do work properly, including the V2001 form
+    "wire #5 foo = bar;"
+
+  - Event controls inside non-blocking assignments are not supported.
+    i.e.: a <= @(posedge clk) b;
+
+  - Lists of named events of the form @(event_1 or event_2) are not
+    supported. Named events are otherwise supported, and lists of
+    other kinds of events are also supported.
+
+  - Macro arguments are not supported. `define macros are supported,
+    but they cannot take arguments.
 
 5.1 Nonstandard Constructs or Behaviors
 
@@ -345,7 +365,7 @@ language that are defined.
     Preprocessing Library Modules
 
 	Icarus Verilog does preprocess modules that are loaded from
-	libraries via the -y mechinism. However, the only macros
+	libraries via the -y mechanism. However, the only macros
 	defined during compilation of that file are those that it
 	defines itself (or includes) or that are defined on the
 	command line or command file.
@@ -372,10 +392,21 @@ language that are defined.
 	Icarus Verilog allows the programmer to specify the field
 	with. The "%t" format in Icarus Verilog works exactly as it
 	does in standard Verilog. However, if the programmer chooses
-	to specify a minimum width, i.e. "%5t" Then for that display
+	to specify a minimum width (i.e., "%5t"), then for that display
 	Icarus Verilog will override the $timeformat minimum width and
 	use the explicit minimum width.
 
+    vpiScope iterator on vpiScope objects.
+
+	In the VPI, the normal way to iterate over vpiScope objects
+	contained within a vpiScope object, is the vpiInternalScope
+	iterator. Icarus Verilog adds support for the vpiScope
+	iterator of a vpiScope object, that iterates over *everything*
+	the is contained in the current scope. This is useful in cases
+	where one wants to iterate over all the objects in a scope
+	without iterating over all the contained types explicitly.
+
+
 6.0 CREDITS
 
 Except where otherwise noted, Icarus Verilog, ivl and ivlpp are
@@ -391,7 +422,7 @@ Verilog guidance, and especially testing from many people, including
 	Guy Hutchison <[email protected]>
 	Ales Hvezda <[email protected]>
 	Venkat Iyer <[email protected]>
-	Yasuhisa Kato <ykato@mac.com>
+	Yasuhisa Kato <kato@y.email.ne.jp>
         James Lee <[email protected]>
 	Peter Monta <[email protected]>
 	Daniel H. Nelsen <[email protected]>
@@ -428,7 +459,7 @@ removed from the list) send e-mail to me.
 	Hamish Moffatt <[email protected]>
 
       Macintosh -- MacO/S
-	Yasuhisa Kato <ykato@mac.com>
+	Yasuhisa Kato <kato@y.email.ne.jp>
 
       Mac O/S X
         Timothy J. Wood <[email protected]>
@@ -451,10 +482,10 @@ just the systems where precompiled binaries are publicly available.
 
 6.2 TEST SUITE MANAGER
 
-Steve Wilson <[email protected]> or <[email protected]> has taken on
-the large task of managing the test suite. He has maintained the
-regression test scripts, the driver list, received submissions from
-myself and others, and has written a great many tests on his own. Any
-compiler writer, for any language, will tell you that the test suite
-is at least as important as the compiler code itself.
+Steve Wilson <[email protected]> has taken on the large task of managing
+the test suite. He has maintained the regression test scripts, the
+driver list, received submissions from myself and others, and has
+written a great many tests on his own. Any compiler writer, for any
+language, will tell you that the test suite is at least as important
+as the compiler code itself.
 

Statement.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: Statement.cc,v 1.27 2002/04/21 22:31:02 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: Statement.cc,v 1.28 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include "config.h"
@@ -295,6 +295,9 @@ PWhile::~PWhile()
 
 /*
  * $Log: Statement.cc,v $
+ * Revision 1.28  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.27  2002/04/21 22:31:02  steve
  *  Redo handling of assignment internal delays.
  *  Leave it possible for them to be calculated

Statement.h

@@ -18,8 +18,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: Statement.h,v 1.34 2002/05/26 01:39:02 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: Statement.h,v 1.36 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include  <string>
@@ -119,8 +119,6 @@ class PAssign  : public PAssign_ {
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
 
     private:
-      NetProc*assign_to_memory_(class NetMemory*, PExpr*,
-				Design*des, NetScope*scope) const;
 };
 
 class PAssignNB  : public PAssign_ {
@@ -455,6 +453,14 @@ class PWhile  : public Statement {
 
 /*
  * $Log: Statement.h,v $
+ * Revision 1.36  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.35  2002/06/04 05:38:44  steve
+ *  Add support for memory words in l-value of
+ *  blocking assignments, and remove the special
+ *  NetAssignMem class.
+ *
  * Revision 1.34  2002/05/26 01:39:02  steve
  *  Carry Verilog 2001 attributes with processes,
  *  all the way through to the ivl_target API.

StringHeap.cc

@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2002 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ *  ---
+ *    You should also have recieved a copy of the Picture Elements
+ *    Binary Software License offer along with the source. This offer
+ *    allows you to obtain the right to redistribute the software in
+ *    binary (compiled) form. If you have not received it, contact
+ *    Picture Elements, Inc., 777 Panoramic Way, Berkeley, CA 94704.
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: StringHeap.cc,v 1.2 2002/08/12 01:34:58 steve Exp $"
+#endif
+
+# include  "StringHeap.h"
+#ifdef HAVE_MALLOC_H
+# include  <malloc.h>
+#endif
+# include  <stdlib.h>
+# include  <string.h>
+# include  <assert.h>
+
+StringHeap::StringHeap()
+{
+      cell_base_ = 0;
+      cell_ptr_ = HEAPCELL;
+}
+
+StringHeap::~StringHeap()
+{
+	// This is a planned memory leak. The string heap is indended
+	// to hold permanently-allocated strings.
+}
+
+const char* StringHeap::add(const char*text)
+{
+      unsigned len = strlen(text);
+      assert((len+1) <= HEAPCELL);
+
+      unsigned rem = HEAPCELL - cell_ptr_;
+      if (rem < (len+1)) {
+	    cell_base_ = (char*)malloc(HEAPCELL);
+	    cell_ptr_ = 0;
+      }
+
+      char*res = cell_base_ + cell_ptr_;
+      memcpy(res, text, len);
+      cell_ptr_ += len;
+      cell_base_[cell_ptr_++] = 0;
+
+      return res;
+}
+
+/*
+ * $Log: StringHeap.cc,v $
+ * Revision 1.2  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.1  2002/08/04 19:13:16  steve
+ *  dll uses StringHeap for named items.
+ *
+ */
+

StringHeap.h

@@ -0,0 +1,53 @@
+#ifndef __StringHeap_H
+#define __StringHeap_H
+/*
+ * Copyright (c) 2002 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: StringHeap.h,v 1.2 2002/08/12 01:34:58 steve Exp $"
+#endif
+
+class StringHeap {
+
+    public:
+      StringHeap();
+      ~StringHeap();
+
+      const char*add(const char*);
+
+    private:
+      enum { HEAPCELL = 0x10000 };
+
+      char*cell_base_;
+      unsigned cell_ptr_;
+
+    private: // not implemented
+      StringHeap(const StringHeap&);
+      StringHeap& operator= (const StringHeap&);
+};
+
+/*
+ * $Log: StringHeap.h,v $
+ * Revision 1.2  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.1  2002/08/04 19:13:16  steve
+ *  dll uses StringHeap for named items.
+ *
+ */
+#endif

acc_user.h

@@ -18,8 +18,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: acc_user.h,v 1.3 2002/06/02 19:03:29 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: acc_user.h,v 1.6 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 /*
@@ -48,22 +48,103 @@ EXTERN_C_START
  */
 typedef struct __vpiHandle *handle;
 
+/* OBJECT TYPES */
+#define accScope   21
+#define accScalar  300
+#define accVector  302
+
+/* type VALUES FOR t_setval_delay STRUCTURE */
+#define accNoDelay  0
+#define accInertialDelay 1
+#define accTransportDelay 2
+#define accPureTransportDelay 3
+#define accForceFlag 4
+#define accReleaseFlag 5
+
+/* type VALUES FOR t_setval_value STRUCTURE */
+#define accBinStrVal 1
+#define accOctStrVal 2
+#define accDecStrVal 3
+#define accHexStrVal 4
+#define accScalarVal 5
+#define accIntVal 6
+#define accRealVal 7
+#define accStringVal 8
+#define accVectorVal 9
+
+/* type VALUES FOR t_acc_time STRUCTURE */
+#define accTime 1
+#define accSimTime 2
+#define accRealTime 3
+
+
+typedef struct t_acc_time {
+      int type;
+      int low, high;
+      double real;
+} s_acc_time, *p_acc_time;
+
+typedef struct t_setval_delay {
+      s_acc_time time;
+      int model;
+} s_setval_delay, *p_setval_delay;
+
+typedef struct t_acc_vecval {
+      int aval;
+      int bval;
+} s_acc_vecval, *p_acc_vecval;
+
+typedef struct t_setval_value {
+      int format;
+      union {
+	    char*str;
+	    int scalar;
+	    int integer;
+	    double real;
+	    p_acc_vecval vector;
+      } value;
+} s_setval_value, *p_setval_value, s_acc_value, *p_acc_value;
+
 extern int acc_error_flag;
 
 extern int acc_initialize(void);
 
 extern void acc_close(void);
 
+extern int   acc_fetch_argc(void);
+extern char**acc_fetch_argv(void);
+
+extern char* acc_fetch_fullname(handle obj);
+
+extern int   acc_fetch_tfarg_int(int n);
+extern char* acc_fetch_tfarg_str(int n);
+
 extern handle acc_handle_tfarg(int n);
 
-extern handle add_next_topmod(handle prev_topmod);
+extern handle acc_next_topmod(handle prev_topmod);
+
+extern int acc_object_of_type(handle object, int type);
 
 extern char*acc_product_version(void);
 
+extern int acc_set_value(handle obj, p_setval_value value,
+			 p_setval_delay delay);
+
+extern char* acc_version(void);
+
 EXTERN_C_END
 
 /*
  * $Log: acc_user.h,v $
+ * Revision 1.6  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.5  2002/06/11 15:19:12  steve
+ *  Add acc_fetch_argc/argv/version (mruff)
+ *
+ * Revision 1.4  2002/06/07 02:58:58  steve
+ *  Add a bunch of acc/tf functions. (mruff)
+ *
  * Revision 1.3  2002/06/02 19:03:29  steve
  *  Add acc_handle_tfarg and acc_next_topmode
  *

async.cc

@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2002 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: async.cc,v 1.4 2002/08/18 22:07:16 steve Exp $"
+#endif
+
+# include "config.h"
+
+# include  "functor.h"
+# include  "netlist.h"
+# include  <assert.h>
+
+bool NetAssign::is_asynchronous()
+{
+      return true;
+}
+
+bool NetCondit::is_asynchronous()
+{
+      return false;
+}
+
+bool NetEvWait::is_asynchronous()
+{
+	/* The "sense" set contains the set of Nexa that are in the
+	   sensitivity list. We also presume here that the list is
+	   only LEVEL sensitive. */
+      NexusSet*sense = new NexusSet;
+      for (unsigned idx = 0 ;  idx < nevents_ ;  idx += 1) {
+	    NexusSet*tmp = event(idx)->nex_async_();
+	    if (tmp == 0) {
+		  delete sense;
+		  return false;
+	    }
+
+	    sense->add(*tmp);
+	    delete tmp;
+      }
+
+      NexusSet*inputs = statement_->nex_input();
+
+      if (! sense->contains(*inputs)) {
+	    delete sense;
+	    delete inputs;
+	    return false;
+      }
+
+      delete sense;
+      delete inputs;
+      return true;
+}
+
+bool NetProc::is_asynchronous()
+{
+      return false;
+}
+
+bool NetProcTop::is_asynchronous()
+{
+      if (type_ == NetProcTop::KINITIAL)
+	    return false;
+
+      return statement_->is_asynchronous();
+}
+
+/*
+ * $Log: async.cc,v $
+ * Revision 1.4  2002/08/18 22:07:16  steve
+ *  Detect temporaries in sequential block synthesis.
+ *
+ * Revision 1.3  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.2  2002/07/04 00:24:16  steve
+ *  initial statements are not asynchronous.
+ *
+ * Revision 1.1  2002/06/30 02:21:31  steve
+ *  Add structure for asynchronous logic synthesis.
+ *
+ */
+

attributes.txt

@@ -0,0 +1,49 @@
+
+ATTRIBUTES TO CONTROL SYNTHESIS
+
+The following is a summary of Verilog attributes that Icarus Verilog
+understands within Verilog source files to control synthesis
+behavior. This section documents generic synthesis attributes. For
+target specific attributes, see target specific documentation.
+
+These attributes only effect the behavior of the synthesizer. For
+example, the ivl_combinational will not generate an error message
+if the Verilog is being compiled for simulation. (It may generate a
+warning.)
+
+
+* Attributes for "always" and "initial" statements
+
+(* ivl_combinational *)
+
+    This attribute tells the compiler that the statement models
+    combinational logic. If the compiler finds that it cannot make
+    combinational logic out of a marked always statement, it will
+    report an error.
+
+    This attribute can be used to prevent accidentally inferring
+    latches or flip-flops where the user intended combinational
+    logic.
+
+(* ivl_synthesis_on *)
+
+    This attribute tells the compiler that the marked always statement
+    is synthesizeable. The compiler will attempt to synthesize the
+    code in the marked "always" statement. If it cannot in any way
+    synthesize it, then it will report an error.
+
+(* ivl_synthesis_off *)
+
+    If this value is attached to an "always" statement, then the
+    compiler will *not* synthesize the "always" statment. This can be
+    used, for example, to mark embedded test bench code.
+
+
+* Attributes for signals (wire/reg/integer/tri/etc.)
+
+[ none defined yet ]
+
+
+* Other Attributes
+
+[ none defined yet ]

autoconf.sh

@@ -12,7 +12,7 @@ autoconf
 for dir in vpip vvp tgt-vvp tgt-fpga libveriuser
 do
     echo "Autoconf in $dir..."
-    ( cd $dir ; autoconf )
+    ( cd ./$dir ; autoconf )
 done
 
 echo "Precompiling lexor_keyword.gperf"

compiler.h

@@ -18,8 +18,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: compiler.h,v 1.12 2002/05/28 20:40:37 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: compiler.h,v 1.13 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include  <list>
@@ -95,6 +95,9 @@ extern char*ivlpp_string;
 
 /*
  * $Log: compiler.h,v $
+ * Revision 1.13  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.12  2002/05/28 20:40:37  steve
  *  ivl indexes the search path for libraries, and
  *  supports case insensitive module-to-file lookup.

config.h.in

@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: config.h.in,v 1.4 2002/02/16 03:18:53 steve Exp $"
+#ident "$Id: config.h.in,v 1.5 2002/08/11 23:39:33 steve Exp $"
 #endif
 
 #if defined(__cplusplus)
@@ -44,10 +44,11 @@
 # undef HAVE_LIBREADLINE
 # undef HAVE_SYS_WAIT_H
 
-# undef ENABLE_VVM
-
 /*
  * $Log: config.h.in,v $
+ * Revision 1.5  2002/08/11 23:39:33  steve
+ *  Remove VVM option.
+ *
  * Revision 1.4  2002/02/16 03:18:53  steve
  *  Make vvm optional, normally off.
  *

configure.in

@@ -2,16 +2,6 @@ dnl Process this file with autoconf to produce a configure script.
 AC_INIT(netlist.h)
 AC_CONFIG_HEADER(config.h)
 
-AC_ARG_ENABLE(vvm, vvm target -- the obsolete vvm code generator,
-	AC_DEFINE(ENABLE_VVM))
-if test "${enable_vvm+set}" = set
-then
-    ENABLE_VVM=yes
-else
-    ENABLE_VVM=no
-fi
-AC_SUBST(ENABLE_VVM)
-
 dnl Checks for programs.
 AC_PROG_CC
 AC_PROG_CXX
@@ -56,7 +46,8 @@ do_times=no
 AC_MSG_RESULT($do_times)
 
 AC_CHECK_HEADER(ipal.h, HAVE_IPAL=yes, HAVE_IPAL=)
-AC_ARG_WITH(ipal,enable PAL target,
+AC_ARG_WITH(ipal,
+    [  --with-ipal             enable PAL target],
 if test "$with_ipal" = no; then
        echo Disabling ipal support
        HAVE_IPAL=
@@ -84,66 +75,6 @@ AC_LANG_C
 AC_CANONICAL_HOST
 # $host
 
-
-#######################
-## test for underscores. The vpi module loader in vvm needs to know this
-## in order to know the name of the start symbol for the .vpi module.
-#######################
-
-AC_CYGWIN
-AC_EXEEXT
-AC_MINGW32
-
-
-WIN32=no
-AC_MSG_CHECKING("Checking for windows")
-if test "$CYGWIN" = "yes" -o "$MINGW32" = "yes"
-then
-    WIN32=yes
-fi
-AC_SUBST(WIN32)
-AC_MSG_RESULT($WIN32)
-AC_SUBST(EXEEXT)
-
-
-AC_MSG_CHECKING("for leading and/or trailing underscores")
-cat << EOF > underscore.c
-       void underscore(void){}
-EOF
-$CC -shared -c underscore.c > /dev/null 2>&1
-
-CC_LEADING_UNDERSCORE=no
-CC_TRAILING_UNDERSCORE=no
-
-output=`nm underscore.o|grep _underscore 2>&1`
-if test ! -z "$output" -a -z "$CYGWIN" -a -z "$MINGW32"; then
-  CC_LEADING_UNDERSCORE=yes
-  AC_DEFINE(NEED_LU)
-fi
-
-
-
-output=`nm underscore.o|grep underscore_ 2>&1`
-if test ! -z "$output"; then
-  CC_TRAILING_UNDERSCORE=yes
-  AC_DEFINE(NEED_TU)
-fi
-
-if test "$CC_LEADING_UNDERSCORE" = yes; then
-  AC_DEFINE(WLU)
-fi
-if test "$CC_TRAILING_UNDERSCORE" = yes; then
-  AC_DEFINE(WTU)
-fi
-
-rm underscore.c underscore.o
-
-AC_MSG_RESULT("$CC_LEADING_UNDERSCORE $CC_TRAILING_UNDERSCORE")
-
-#######################
-## end of test for underscores
-#######################
-
 # The -fPIC flag is used to tell the compiler to make position
 # independent code. It is needed when making shared objects.
 
@@ -241,10 +172,89 @@ case "${host}" in
 esac
 
 AC_SUBST(shared)
-
 AC_MSG_RESULT($shared)
 
+#######################
+## test for underscores. The vpi module loader needs to know this
+## in order to know the name of the start symbol for the .vpi module.
+#######################
 
-AC_CONFIG_SUBDIRS(vpip vvp tgt-vvp tgt-fpga libveriuser)
+AC_CYGWIN
+AC_EXEEXT
+AC_MINGW32
 
-AC_OUTPUT(Makefile vpi/Makefile ivlpp/Makefile vvm/Makefile driver/Makefile tgt-null/Makefile tgt-stub/Makefile tgt-verilog/Makefile tgt-pal/Makefile)
+
+WIN32=no
+AC_MSG_CHECKING("Checking for windows")
+if test "$CYGWIN" = "yes" -o "$MINGW32" = "yes"
+then
+    WIN32=yes
+fi
+
+AC_SUBST(MINGW32)
+AC_SUBST(WIN32)
+AC_MSG_RESULT($WIN32)
+AC_SUBST(EXEEXT)
+
+
+AC_MSG_CHECKING("for leading and/or trailing underscores")
+cat << EOF > underscore.c
+       void underscore(void){}
+EOF
+
+$CC $shared -c underscore.c > /dev/null 2>&1
+
+CC_LEADING_UNDERSCORE=no
+CC_TRAILING_UNDERSCORE=no
+
+output=`nm underscore.o|grep _underscore 2>&1`
+if test ! -z "$output" -a "$CYGWIN" != "yes" -a "$MINGW32" != "yes"; then
+  CC_LEADING_UNDERSCORE=yes
+  AC_DEFINE(NEED_LU)
+fi
+
+output=`nm underscore.o|grep underscore_ 2>&1`
+if test ! -z "$output"; then
+  CC_TRAILING_UNDERSCORE=yes
+  AC_DEFINE(NEED_TU)
+fi
+
+if test "$CC_LEADING_UNDERSCORE" = yes; then
+  AC_DEFINE(WLU)
+fi
+if test "$CC_TRAILING_UNDERSCORE" = yes; then
+  AC_DEFINE(WTU)
+fi
+
+rm underscore.c underscore.o
+
+AC_MSG_RESULT("$CC_LEADING_UNDERSCORE $CC_TRAILING_UNDERSCORE")
+
+#######################
+## end of test for underscores
+#######################
+
+AC_MSG_CHECKING("for ident support in C compiler")
+ident_support='-DHAVE_CVS_IDENT=1'
+case "${host}" in
+
+     *-*-cygwin*)
+	ident_support=
+	;;
+
+     *-*-darwin*)
+	ident_support=
+	;;
+
+     *-*-machten*)
+	ident_support=
+	;;
+esac
+
+AC_SUBST(ident_support)
+AC_MSG_RESULT($ident_support)
+
+
+AC_CONFIG_SUBDIRS(vvp tgt-vvp tgt-fpga libveriuser)
+
+AC_OUTPUT(Makefile vpi/Makefile ivlpp/Makefile driver/Makefile driver-vpi/Makefile tgt-null/Makefile tgt-stub/Makefile tgt-verilog/Makefile tgt-pal/Makefile)

cprop.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: cprop.cc,v 1.35 2002/05/26 01:39:02 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: cprop.cc,v 1.39 2002/08/20 04:12:22 steve Exp $"
 #endif
 
 # include "config.h"
@@ -64,8 +64,8 @@ void cprop_functor::lpm_add_sub(Design*des, NetAddSub*obj)
 	// result. Don't reduce the adder smaller then a 1-bit
 	// adder. These will be eliminated later.
       while ((obj->width() > 1)
-	  && link_drivers_constant(obj->pin_DataA(0))
-	  && (driven_value(obj->pin_DataA(0)) == verinum::V0)) {
+	     && obj->pin_DataA(0).nexus()->drivers_constant()
+	     && (obj->pin_DataA(0).nexus()->driven_value() == verinum::V0)) {
 
 	    NetAddSub*tmp = 0;
 	    tmp = new NetAddSub(obj->scope(), obj->name(), obj->width()-1);
@@ -89,8 +89,8 @@ void cprop_functor::lpm_add_sub(Design*des, NetAddSub*obj)
 
 	// Now do the same thing on the B side.
       while ((obj->width() > 1)
-	  && link_drivers_constant(obj->pin_DataB(0))
-	  && (driven_value(obj->pin_DataB(0)) == verinum::V0)) {
+	     && obj->pin_DataB(0).nexus()->drivers_constant()
+	     && (obj->pin_DataB(0).nexus()->driven_value() == verinum::V0)) {
 
 	    NetAddSub*tmp = 0;
 	    tmp = new NetAddSub(obj->scope(), obj->name(), obj->width()-1);
@@ -160,12 +160,12 @@ void cprop_functor::lpm_compare_eq_(Design*des, NetCompare*obj)
 	   be completely eliminated and replaced with a constant 0. */
 
       for (unsigned idx = 0 ;  idx < obj->width() ;  idx += 1) {
-	    if (! link_drivers_constant(obj->pin_DataA(idx)))
+	    if (! obj->pin_DataA(idx).nexus()->drivers_constant())
 		  continue;
-	    if (! link_drivers_constant(obj->pin_DataB(idx)))
+	    if (! obj->pin_DataB(idx).nexus()->drivers_constant())
 		  continue;
-	    if (driven_value(obj->pin_DataA(idx)) ==
-		driven_value(obj->pin_DataB(idx)))
+	    if (obj->pin_DataA(idx).nexus()->driven_value() ==
+		obj->pin_DataB(idx).nexus()->driven_value())
 		  continue;
 
 	    NetConst*zero = new NetConst(scope, obj->name(), verinum::V0);
@@ -181,11 +181,11 @@ void cprop_functor::lpm_compare_eq_(Design*des, NetCompare*obj)
 
       unsigned top = obj->width();
       for (unsigned idx = 0 ;  idx < top ; ) {
-	    if (! link_drivers_constant(obj->pin_DataA(idx))) {
+	    if (! obj->pin_DataA(idx).nexus()->drivers_constant()) {
 		  idx += 1;
 		  continue;
 	    }
-	    if (! link_drivers_constant(obj->pin_DataB(idx))) {
+	    if (! obj->pin_DataB(idx).nexus()->drivers_constant()) {
 		  idx += 1;
 		  continue;
 	    }
@@ -310,12 +310,12 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 		     on the output of an AND gate. */
 
 		while (idx < top) {
-		      if (! link_drivers_constant(obj->pin(idx))) {
+		      if (! obj->pin(idx).nexus()->drivers_constant()) {
 			    idx += 1;
 			    continue;
 		      }
 
-		      if (driven_value(obj->pin(idx)) == verinum::V1) {
+		      if (obj->pin(idx).nexus()->driven_value()==verinum::V1) {
 			    obj->pin(idx).unlink();
 			    top -= 1;
 			    if (idx < top) {
@@ -326,7 +326,7 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 			    continue;
 		      }
 
-		      if (driven_value(obj->pin(idx)) != verinum::V0) {
+		      if (obj->pin(idx).nexus()->driven_value() != verinum::V0) {
 			    idx += 1;
 			    xs += 1;
 			    continue;
@@ -348,6 +348,10 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 			    assert(0);
 		      }
 
+		      tmp->rise_time(obj->rise_time());
+		      tmp->fall_time(obj->fall_time());
+		      tmp->decay_time(obj->decay_time());
+
 		      des->add_node(tmp);
 		      tmp->pin(0).drive0(obj->pin(0).drive0());
 		      tmp->pin(0).drive1(obj->pin(0).drive1());
@@ -373,6 +377,10 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 			    assert(0);
 		      }
 
+		      tmp->rise_time(obj->rise_time());
+		      tmp->fall_time(obj->fall_time());
+		      tmp->decay_time(obj->decay_time());
+
 		      des->add_node(tmp);
 		      tmp->pin(0).drive0(obj->pin(0).drive0());
 		      tmp->pin(0).drive1(obj->pin(0).drive1());
@@ -416,6 +424,11 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 			  default:
 			    assert(0);
 		      }
+
+		      tmp->rise_time(obj->rise_time());
+		      tmp->fall_time(obj->fall_time());
+		      tmp->decay_time(obj->decay_time());
+
 		      des->add_node(tmp);
 		      tmp->pin(0).drive0(obj->pin(0).drive0());
 		      tmp->pin(0).drive1(obj->pin(0).drive1());
@@ -427,12 +440,16 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 		}
 
 		  /* Finally, this cleans up the gate by creating a
-		     new [N]OR gate that has the right number of
+		     new [N]AND gate that has the right number of
 		     inputs, connected in the right place. */
 		if (top < obj->pin_count()) {
 		      NetLogic*tmp = new NetLogic(scope,
 						  obj->name(), top,
 						  obj->type());
+		      tmp->rise_time(obj->rise_time());
+		      tmp->fall_time(obj->fall_time());
+		      tmp->decay_time(obj->decay_time());
+
 		      des->add_node(tmp);
 		      tmp->pin(0).drive0(obj->pin(0).drive0());
 		      tmp->pin(0).drive1(obj->pin(0).drive1());
@@ -457,12 +474,12 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 		     on the output of an OR gate. */
 
 		while (idx < top) {
-		      if (! link_drivers_constant(obj->pin(idx))) {
+		      if (! obj->pin(idx).nexus()->drivers_constant()) {
 			    idx += 1;
 			    continue;
 		      }
 
-		      if (driven_value(obj->pin(idx)) == verinum::V0) {
+		      if (obj->pin(idx).nexus()->driven_value() == verinum::V0) {
 			    obj->pin(idx).unlink();
 			    top -= 1;
 			    if (idx < top) {
@@ -473,7 +490,7 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 			    continue;
 		      }
 
-		      if (driven_value(obj->pin(idx)) != verinum::V1) {
+		      if (obj->pin(idx).nexus()->driven_value() != verinum::V1) {
 			    idx += 1;
 			    continue;
 		      }
@@ -494,6 +511,10 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 			    assert(0);
 		      }
 
+		      tmp->rise_time(obj->rise_time());
+		      tmp->fall_time(obj->fall_time());
+		      tmp->decay_time(obj->decay_time());
+
 		      des->add_node(tmp);
 		      tmp->pin(0).drive0(obj->pin(0).drive0());
 		      tmp->pin(0).drive1(obj->pin(0).drive1());
@@ -519,6 +540,10 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 			    assert(0);
 		      }
 
+		      tmp->rise_time(obj->rise_time());
+		      tmp->fall_time(obj->fall_time());
+		      tmp->decay_time(obj->decay_time());
+
 		      des->add_node(tmp);
 		      tmp->pin(0).drive0(obj->pin(0).drive0());
 		      tmp->pin(0).drive1(obj->pin(0).drive1());
@@ -547,6 +572,10 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 			  default:
 			    assert(0);
 		      }
+		      tmp->rise_time(obj->rise_time());
+		      tmp->fall_time(obj->fall_time());
+		      tmp->decay_time(obj->decay_time());
+
 		      des->add_node(tmp);
 		      tmp->pin(0).drive0(obj->pin(0).drive0());
 		      tmp->pin(0).drive1(obj->pin(0).drive1());
@@ -564,6 +593,10 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 		      NetLogic*tmp = new NetLogic(scope,
 						  obj->name(), top,
 						  obj->type());
+		      tmp->rise_time(obj->rise_time());
+		      tmp->fall_time(obj->fall_time());
+		      tmp->decay_time(obj->decay_time());
+
 		      des->add_node(tmp);
 		      tmp->pin(0).drive0(obj->pin(0).drive0());
 		      tmp->pin(0).drive1(obj->pin(0).drive1());
@@ -588,12 +621,12 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 		     last input to this position. It's like bubbling
 		     all the 0 inputs to the end. */
 		while (idx < top) {
-		      if (! link_drivers_constant(obj->pin(idx))) {
+		      if (! obj->pin(idx).nexus()->drivers_constant()) {
 			    idx += 1;
 			    continue;
 		      }
 
-		      if (driven_value(obj->pin(idx)) == verinum::V0) {
+		      if (obj->pin(idx).nexus()->driven_value() == verinum::V0) {
 			    obj->pin(idx).unlink();
 			    top -= 1;
 			    if (idx < top) {
@@ -618,12 +651,12 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 		unsigned one = 0, ones = 0;
 		idx = 1;
 		while (idx < top) {
-		      if (! link_drivers_constant(obj->pin(idx))) {
+		      if (! obj->pin(idx).nexus()->drivers_constant()) {
 			    idx += 1;
 			    continue;
 		      }
 
-		      if (driven_value(obj->pin(idx)) == verinum::V1) {
+		      if (obj->pin(idx).nexus()->driven_value() == verinum::V1) {
 			    if (one == 0) {
 				  one = idx;
 				  ones += 1;
@@ -666,6 +699,10 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 			    : verinum::V0;
 		      NetConst*tmp = new NetConst(scope, obj->name(), out);
 
+		      tmp->rise_time(obj->rise_time());
+		      tmp->fall_time(obj->fall_time());
+		      tmp->decay_time(obj->decay_time());
+
 		      des->add_node(tmp);
 		      tmp->pin(0).drive0(obj->pin(0).drive0());
 		      tmp->pin(0).drive1(obj->pin(0).drive1());
@@ -682,9 +719,9 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 
 		if ((top == 3) && (ones == 1)) {
 		      unsigned save;
-		      if (! link_drivers_constant(obj->pin(1)))
+		      if (! obj->pin(1).nexus()->drivers_constant())
 			    save = 1;
-		      else if (driven_value(obj->pin(1)) != verinum::V1)
+		      else if (obj->pin(1).nexus()->driven_value() != verinum::V1)
 			    save = 1;
 		      else
 			    save = 2;
@@ -700,6 +737,10 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 					       obj->name(), 2,
 					       NetLogic::BUF);
 
+		      tmp->rise_time(obj->rise_time());
+		      tmp->fall_time(obj->fall_time());
+		      tmp->decay_time(obj->decay_time());
+
 		      des->add_node(tmp);
 		      tmp->pin(0).drive0(obj->pin(0).drive0());
 		      tmp->pin(0).drive1(obj->pin(0).drive1());
@@ -725,6 +766,10 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 					       obj->name(), 2,
 					       NetLogic::NOT);
 
+		      tmp->rise_time(obj->rise_time());
+		      tmp->fall_time(obj->fall_time());
+		      tmp->decay_time(obj->decay_time());
+
 		      des->add_node(tmp);
 		      tmp->pin(0).drive0(obj->pin(0).drive0());
 		      tmp->pin(0).drive1(obj->pin(0).drive1());
@@ -777,12 +822,12 @@ void cprop_functor::lpm_mux(Design*des, NetMux*obj)
 	   connected to the select input. */
       bool flag = true;
       for (unsigned idx = 0 ;  idx < obj->width() ;  idx += 1) {
-	    if (! link_drivers_constant(obj->pin_Data(idx, 0))) {
+	    if (! obj->pin_Data(idx, 0).nexus()->drivers_constant()) {
 		  flag = false;
 		  break;
 	    }
 
-	    if (driven_value(obj->pin_Data(idx, 0)) != verinum::Vz) {
+	    if (obj->pin_Data(idx, 0).nexus()->driven_value() != verinum::Vz) {
 		  flag = false;
 		  break;
 	    }
@@ -809,12 +854,12 @@ void cprop_functor::lpm_mux(Design*des, NetMux*obj)
 	   NetMux with an array of BUFIF0 devices. */
       flag = true;
       for (unsigned idx = 0 ;  idx < obj->width() ;  idx += 1) {
-	    if (! link_drivers_constant(obj->pin_Data(idx, 1))) {
+	    if (! obj->pin_Data(idx, 1).nexus()->drivers_constant()) {
 		  flag = false;
 		  break;
 	    }
 
-	    if (driven_value(obj->pin_Data(idx, 1)) != verinum::Vz) {
+	    if (obj->pin_Data(idx, 1).nexus()->driven_value() != verinum::Vz) {
 		  flag = false;
 		  break;
 	    }
@@ -949,6 +994,19 @@ void cprop(Design*des)
 
 /*
  * $Log: cprop.cc,v $
+ * Revision 1.39  2002/08/20 04:12:22  steve
+ *  Copy gate delays when doing gate delay substitutions.
+ *
+ * Revision 1.38  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.37  2002/06/25 01:33:22  steve
+ *  Cache calculated driven value.
+ *
+ * Revision 1.36  2002/06/24 01:49:38  steve
+ *  Make link_drive_constant cache its results in
+ *  the Nexus, to improve cprop performance.
+ *
  * Revision 1.35  2002/05/26 01:39:02  steve
  *  Carry Verilog 2001 attributes with processes,
  *  all the way through to the ivl_target API.

design_dump.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: design_dump.cc,v 1.124 2002/05/26 01:39:02 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: design_dump.cc,v 1.135 2002/10/23 01:47:17 steve Exp $"
 #endif
 
 # include "config.h"
@@ -117,6 +117,13 @@ void NetNet::dump_net(ostream&o, unsigned ind) const
       dump_obj_attr(o, ind+4);
 }
 
+void NetSubnet::dump_net(ostream&o, unsigned ind) const
+{
+      o << setw(ind) << "" << "** " << name() << " is a NetSubnet **"
+	<< endl;
+      NetNet::dump_net(o, ind);
+}
+
 void NetMemory::dump(ostream&o, unsigned ind) const
 {
       o << setw(ind) << ""  << name_ << "[" << width_ << "] " <<
@@ -264,7 +271,8 @@ void NetConst::dump_node(ostream&o, unsigned ind) const
 void NetFF::dump_node(ostream&o, unsigned ind) const
 {
       o << setw(ind) << "" << "LPM_FF: " << name()
-	<< " scope=" << (scope()? scope()->name() : "") << endl;
+	<< " scope=" << (scope()? scope()->name() : "")
+	<< " aset_value=" << aset_value_ << endl;
 
       dump_node_pins(o, ind+4);
       dump_obj_attr(o, ind+4);
@@ -431,6 +439,14 @@ void NetAssign_::dump_lval(ostream&o) const
 	    } else {
 		  o << "[" << (loff_+lwid_-1) << ":" << loff_ << "]";
 	    }
+      } else if (mem_) {
+	    // Is there an obvious way to flag memories in the dump
+	    // as different from the _real_ bit mux case?
+	    // o << "**memory**";
+	    o << mem_->name() << "[";
+	    if (bmux_) o << *bmux_;
+	      else     o << "**oops**";
+	    o << "]";
       } else {
 	    o << "";
       }
@@ -477,30 +493,13 @@ void NetAssignNB::dump(ostream&o, unsigned ind) const
 
 }
 
-void NetAssignMem::dump(ostream&o, unsigned ind) const
-{
-      o << setw(ind) << "";
-      o << "/* " << get_line() << " */" << endl;
-      o << setw(ind) << "";
-      o << memory()->name() << "[" << *index() << "] = ";
-      rval()->dump(o);
-      o << ";" << endl;
-}
-
-void NetAssignMemNB::dump(ostream&o, unsigned ind) const
-{
-      o << setw(ind) << "";
-      o << "/* " << get_line() << " */" << endl;
-      o << setw(ind) << "";
-      o << memory()->name() << "[" << *index() << "] <= ";
-      rval()->dump(o);
-      o << ";" << endl;
-}
-
 /* Dump a block statement */
 void NetBlock::dump(ostream&o, unsigned ind) const
 {
-      o << setw(ind) << "" << type_ << endl;
+      o << setw(ind) << "" << type_;
+      if (subscope_)
+	    o << " : " << subscope_->name();
+      o << endl;
 
       if (last_) {
 	    const NetProc*cur = last_;
@@ -660,8 +659,12 @@ void NetPDelay::dump(ostream&o, unsigned ind) const
 
 void NetRelease::dump(ostream&o, unsigned ind) const
 {
-      o << setw(ind) << "" << "release " << lval_->name() << "; "
-	<< "/* " << get_line() << " */" << endl;
+      if (lval_)
+	    o << setw(ind) << "" << "release " << lval_->name() << "; "
+	      << "/* " << get_line() << " */" << endl;
+      else
+	    o << setw(ind) << "" << "release (null); "
+	      << "/* " << get_line() << " */" << endl;
 }
 
 void NetRepeat::dump(ostream&o, unsigned ind) const
@@ -697,17 +700,26 @@ void NetScope::dump(ostream&o) const
 
 	/* Dump the parameters for this scope. */
       {
-	    map<string,NetExpr*>::const_iterator pp;
+	    map<string,param_expr_t>::const_iterator pp;
 	    for (pp = parameters_.begin()
 		       ; pp != parameters_.end() ;  pp ++) {
-		  o << "    parameter " << (*pp).first << " = "  <<
-			*(*pp).second << ";" << endl;
+		  o << "    parameter ";
+
+		  if ((*pp).second.signed_flag)
+			o << "signed ";
+
+		  if ((*pp).second.msb)
+			o << "[" << *(*pp).second.msb
+			  << ":" << *(*pp).second.lsb << "] ";
+
+		  o << (*pp).first << " = "  <<
+			*(*pp).second.expr << ";" << endl;
 	    }
 
 	    for (pp = localparams_.begin()
 		       ; pp != localparams_.end() ;  pp ++) {
 		  o << "    localparam " << (*pp).first << " = "  <<
-			*(*pp).second << ";" << endl;
+			*(*pp).second.expr << ";" << endl;
 	    }
       }
 
@@ -855,8 +867,12 @@ void NetEBinary::dump(ostream&o) const
 
 void NetEConcat::dump(ostream&o) const
 {
-      if (repeat_)
-	    o << *repeat_;
+      if (repeat_calculated_) {
+	    if (repeat_value_ != 1)
+		  o << repeat_value_;
+      } else if (repeat_) {
+	    o << "<" << *repeat_ << ">";
+      }
 
       if (parms_[0])
 	    o << "{" << *parms_[0];
@@ -919,7 +935,10 @@ void NetEMemory::dump(ostream&o) const
 
 void NetEParam::dump(ostream&o) const
 {
-      o << "<" << scope_->name() << "." << name_ << ">";
+      if (scope_ != 0)
+	    o << "<" << scope_->name() << "." << name_ << ">";
+      else
+	    o << "<" << name_ << ">";
 }
 
 void NetETernary::dump(ostream&o) const
@@ -985,6 +1004,48 @@ void Design::dump(ostream&o) const
 
 /*
  * $Log: design_dump.cc,v $
+ * Revision 1.135  2002/10/23 01:47:17  steve
+ *  Fix synth2 handling of aset/aclr signals where
+ *  flip-flops are split by begin-end blocks.
+ *
+ * Revision 1.134  2002/10/19 22:59:49  steve
+ *  Redo the parameter vector support to allow
+ *  parameter names in range expressions.
+ *
+ * Revision 1.133  2002/08/19 00:06:11  steve
+ *  Allow release to handle removal of target net.
+ *
+ * Revision 1.132  2002/08/13 05:35:00  steve
+ *  Do not elide named blocks.
+ *
+ * Revision 1.131  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.130  2002/08/04 18:28:14  steve
+ *  Do not use hierarchical names of memories to
+ *  generate vvp labels. -tdll target does not
+ *  used hierarchical name string to look up the
+ *  memory objects in the design.
+ *
+ * Revision 1.129  2002/06/19 04:20:03  steve
+ *  Remove NetTmp and add NetSubnet class.
+ *
+ * Revision 1.128  2002/06/14 21:38:41  steve
+ *  Fix expression width for repeat concatenations.
+ *
+ * Revision 1.127  2002/06/08 23:42:46  steve
+ *  Add NetRamDq synthsesis from memory l-values.
+ *
+ * Revision 1.126  2002/06/05 03:44:25  steve
+ *  Add support for memory words in l-value of
+ *  non-blocking assignments, and remove the special
+ *  NetAssignMem_ and NetAssignMemNB classes.
+ *
+ * Revision 1.125  2002/06/04 05:38:44  steve
+ *  Add support for memory words in l-value of
+ *  blocking assignments, and remove the special
+ *  NetAssignMem class.
+ *
  * Revision 1.124  2002/05/26 01:39:02  steve
  *  Carry Verilog 2001 attributes with processes,
  *  all the way through to the ivl_target API.

dosify.c

@@ -15,9 +15,10 @@
  *    You should have received a copy of the GNU General Public License
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
- *
- * $Id: dosify.c,v 1.1 2001/08/03 17:06:47 steve Exp $
  */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: dosify.c,v 1.3 2002/08/12 01:34:58 steve Exp $"
+#endif
 
 /*
  * This is a simple program to make a dosified copy of the
@@ -68,6 +69,12 @@ int main(int argc, char*argv[])
 
 /*
  * $Log: dosify.c,v $
+ * Revision 1.3  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.2  2002/08/11 23:47:04  steve
+ *  Add missing Log and Ident strings.
+ *
  * Revision 1.1  2001/08/03 17:06:47  steve
  *  Add install of examples for Windows.
  *

driver-vpi/.cvsignore

@@ -0,0 +1,2 @@
+Makefile
+iverilog-vpi.exe

driver-vpi/Makefile.in

@@ -0,0 +1,82 @@
+#
+#    This source code is free software; you can redistribute it
+#    and/or modify it in source code form under the terms of the GNU
+#    Library General Public License as published by the Free Software
+#    Foundation; either version 2 of the License, or (at your option)
+#    any later version.
+#
+#    This program is distributed in the hope that it will be useful,
+#    but WITHOUT ANY WARRANTY; without even the implied warranty of
+#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#    GNU Library General Public License for more details.
+#
+#    You should have received a copy of the GNU Library General Public
+#    License along with this program; if not, write to the Free
+#    Software Foundation, Inc.,
+#    59 Temple Place - Suite 330
+#    Boston, MA 02111-1307, USA
+#
+#ident "$Id: Makefile.in,v 1.5 2002/12/08 03:06:30 steve Exp $"
+#
+#
+SHELL = /bin/sh
+
+VERSION = 0.7
+
+prefix = @prefix@
+exec_prefix = @exec_prefix@
+srcdir = @srcdir@
+
+VPATH = $(srcdir)
+
+bindir = $(exec_prefix)/bin
+libdir = $(exec_prefix)/lib
+includedir = $(prefix)/include
+mandir = @mandir@
+
+dllib=@DLLIB@
+
+CC = @CC@
+CXX = @CXX@
+INSTALL = @INSTALL@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_DATA = @INSTALL_DATA@
+
+CPPFLAGS = @CPPFLAGS@ @DEFS@
+CFLAGS = @CFLAGS@ -I. -I$(srcdir)/.. -DVERSION='"$(VERSION)"'
+CXXFLAGS = @CXXFLAGS@ -I. -I$(srcdir)/..
+LDFLAGS = @LDFLAGS@
+
+all: iverilog-vpi@EXEEXT@
+
+clean:
+	rm -f *.o
+	rm -f iverilog-vpi@EXEEXT@
+
+distclean: clean
+	rm -f Makefile
+
+O = main.o res.o
+
+iverilog-vpi@EXEEXT@: $O
+	$(CC) $(LDFLAGS) $O -o iverilog-vpi@EXEEXT@ @EXTRALIBS@
+
+
+main.o: main.c
+	$(CC) $(CFLAGS) -c $(srcdir)/main.c
+
+# Windows specific...
+res.o: res.rc
+	windres -i res.rc -o res.o
+#
+
+install: all installdirs $(bindir)/iverilog-vpi@EXEEXT@
+
+$(bindir)/iverilog-vpi@EXEEXT@: ./iverilog-vpi@EXEEXT@
+	$(INSTALL_PROGRAM) ./iverilog-vpi@EXEEXT@ $(bindir)/iverilog-vpi@EXEEXT@
+
+installdirs: ../mkinstalldirs
+	$(srcdir)/../mkinstalldirs $(bindir)
+
+uninstall:
+	rm -f $(bindir)/iverilog-vpi@EXEEXT@

driver-vpi/main.c

@@ -0,0 +1,565 @@
+/*
+ * Copyright (c) 2002 Gus Baldauf (gus@picturel.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+/*
+ *	iverilog-vpi.c
+ *
+ *	this program provides the functionality of iverilog-vpi.sh under Win32
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#include <windows.h>
+
+/* Macros used for compiling and linking */
+
+#define IVERILOG_VPI_CC        "gcc"				/* no .exe extension  */
+#define IVERILOG_VPI_CXX       "gcc"				/* no .exe extension  */
+#define IVERILOG_VPI_CFLAGS    "-O"					/* -I appended  later */
+#define IVERILOG_VPI_LD        "gcc"				/* no .exe extension  */
+#define IVERILOG_VPI_LDFLAGS   "-shared -Wl,--enable-auto-image-base"
+#define IVERILOG_VPI_LDLIBS    "-lveriuser -lvpi"	/* -L prepended later */
+
+/* pointers to global strings */
+
+static struct global_strings {
+	char *pCCSRC;		/* list of C source files */
+	char *pCXSRC;		/* list of C++ source files */
+	char *pOBJ;			/* list of object files */
+	char *pLIB;			/* list of library files */
+	char *pOUT;			/* output file name (.vpi extension), if 0 length then no source files specified */
+	char *pMINGW;		/* path to MinGW directory */
+	char *pIVL;			/* path to IVL directory */
+	char *pCFLAGS;		/* CFLAGS option */
+	char *pLDLIBS;		/* LDLIBS option */
+	char *pNewPath;		/* new PATH environment variable setting */
+} gstr;
+
+
+static void deInitDynString(char *str)
+{
+	free(str);
+}
+
+/* when finished, free allocated memory and return error code */
+
+static void myExit(int exitVal)
+{
+	deInitDynString(gstr.pCCSRC);
+	deInitDynString(gstr.pCXSRC);
+	deInitDynString(gstr.pOBJ);
+	deInitDynString(gstr.pLIB);
+	deInitDynString(gstr.pOUT);
+	deInitDynString(gstr.pMINGW);
+	deInitDynString(gstr.pIVL);
+	deInitDynString(gstr.pCFLAGS);
+	deInitDynString(gstr.pLDLIBS);
+	deInitDynString(gstr.pNewPath);
+
+	exit(exitVal);
+}
+
+/* display usage summary and exit */
+
+static void usage()
+{
+	fprintf(stderr,"usage: iverilog-vpi [--name=name] [-llibrary] [-mingw=dir] [-ivl=dir] sourcefile...\n");
+	fprintf(stderr,"   or  iverilog-vpi -mingw=dir\n");
+	fprintf(stderr,"   or  iverilog-vpi -ivl=dir\n");
+	myExit(1);
+}
+
+static void initDynString(char **str)
+{
+	*str = (char *) malloc(1);
+
+	if (!*str) {
+		fprintf(stderr,"error: out of memory\n");
+		myExit(4);
+	}
+
+	*str[0] = 0;
+}
+
+/* initialize dynamic memory buffers */
+
+static void init()
+{
+	initDynString(&gstr.pCCSRC);
+	initDynString(&gstr.pCXSRC);
+	initDynString(&gstr.pOBJ);
+	initDynString(&gstr.pLIB);
+	initDynString(&gstr.pOUT);
+	initDynString(&gstr.pMINGW);
+	initDynString(&gstr.pIVL);
+	initDynString(&gstr.pCFLAGS);
+	initDynString(&gstr.pLDLIBS);
+	initDynString(&gstr.pNewPath);
+}
+
+/* return true if "str" is terminated with with "end", case insensitive */
+
+static int endsIn (char *end, char *str)
+{
+	char *ext;
+
+	if (strlen(end) >= strlen(str))
+		return 0;
+
+	ext = str + (strlen(str) - strlen(end));
+
+	return stricmp(end,ext) ? 0 : 1;
+}
+
+/* return true if "str" begins with "prefix", case insensitive */
+
+static int startsWith (char *prefix, char *str)
+{
+	if (strlen(prefix) >= strlen(str))
+		return 0;
+
+	return strnicmp(prefix,str,strlen(prefix)) ? 0 : 1;
+}
+
+/* append "app" to "ptr", allocating memory as needed    */
+/*   if count is zero, then copy all characters of "app" */
+
+static void appendn (char **ptr, char *app, int count)
+{
+	*ptr = (char *) realloc(*ptr,strlen(*ptr)+(count?count:strlen(app))+1);
+
+	if (*ptr == NULL) {
+		fprintf(stderr,"error: out of memory\n");
+		myExit(4);
+	}
+
+	if (count)
+		strncat(*ptr,app,count);
+	else
+		strcat(*ptr,app);
+}
+
+/* append "app" to "ptr", allocating memory as needed    */
+
+static void append (char **ptr, char *app)
+{
+	appendn(ptr,app,0);
+}
+
+/* if the string does not end with a backslash, add one */
+
+static void appendBackSlash(char **str)
+{
+	if ((*str)[strlen(*str)-1] != '\\')
+		append(str,"\\");
+}
+
+/* copy count characters of "str" to "ptr", allocating memory as needed */
+/*   if count is zero, then copy all characters of "str"                */
+
+static void assignn (char **ptr, char *str, int count)
+{
+	*ptr = (char *) realloc(*ptr,(count?count:strlen(str))+1);
+
+	if (*ptr == NULL) {
+		fprintf(stderr,"error: out of memory\n");
+		myExit(4);
+	}
+
+	if (count) {
+		strncpy(*ptr,str,count);
+		(*ptr)[count] = 0;
+	}
+	else
+		strcpy(*ptr,str);
+}
+
+/* copy count characters of "str" to "ptr", allocating memory as needed */
+
+static void assign (char **ptr, char *str)
+{
+	assignn(ptr,str,0);
+}
+
+/* get a copy of a Icarus Verilog registry string key */
+
+static int GetRegistryKey(char *key, char **value)
+{
+	long lrv;
+	HKEY hkKey;
+	char *regKeyBuffer;
+	DWORD regKeyType, regKeySize;
+
+	lrv = RegOpenKeyEx(HKEY_LOCAL_MACHINE,"Software\\Icarus Verilog",0,KEY_QUERY_VALUE,&hkKey);
+	if (lrv != ERROR_SUCCESS)
+		return 0;
+
+	lrv = RegQueryValueEx(hkKey,key,NULL,&regKeyType,NULL,&regKeySize);
+	if ((lrv != ERROR_SUCCESS) || (regKeyType != REG_SZ) || (!regKeySize)) {
+		lrv = RegCloseKey(hkKey);
+		return 0;
+	}
+
+	regKeyBuffer = (char *) malloc(regKeySize+1);
+	if (!regKeyBuffer) {
+		lrv = RegCloseKey(hkKey);
+		fprintf(stderr,"error: out of memory\n");
+		myExit(4);
+	}
+	regKeyBuffer[regKeySize] = 0;		/* makes sure there is a trailing NULL */
+
+	lrv = RegQueryValueEx(hkKey,key,NULL,&regKeyType,regKeyBuffer,&regKeySize);
+	if ((lrv != ERROR_SUCCESS) || (regKeyType != REG_SZ) || (!regKeySize)) {
+		lrv = RegCloseKey(hkKey);
+		free(regKeyBuffer);
+		return 0;
+	}
+
+	RegCloseKey(hkKey);
+
+	assign(value,regKeyBuffer);
+	free(regKeyBuffer);
+
+	return 1;
+}
+
+/* store a copy of a Icarus Verilog registry string key */
+
+static void SetRegistryKey(char *key, char *value)
+{
+	HKEY hkKey;
+	DWORD res;
+
+	if (RegCreateKeyEx(
+		HKEY_LOCAL_MACHINE,
+		"Software\\Icarus Verilog",
+		0,
+		"",
+		REG_OPTION_NON_VOLATILE,
+		KEY_ALL_ACCESS,NULL,
+		&hkKey,
+		&res) != ERROR_SUCCESS)
+			return;
+
+	RegSetValueEx(hkKey,key,0,REG_SZ,value,strlen(value)+1);
+	RegCloseKey(hkKey);
+
+	printf("info:  storing %s in Windows' registry entry\n",value);
+	printf("       HKEY_LOCAL_MACHINE\\Software\\Icarus Verilog\\%s\n",key);
+}
+
+/* parse the command line, assign results to global variable strings */
+
+static int parse(int argc, char *argv[])
+{
+	int idx, srcFileCnt=0;
+
+	char dot_c_ext[]    = ".c";
+	char dot_cc_ext[]   = ".cc";
+	char dot_o_ext[]    = ".o";
+	char name_option[]  = "--name=";
+	char lib_option[]   = "-l";
+	char mingw_option[] = "-mingw=";
+	char ivl_option[]   = "-ivl=";
+
+	if (argc == 1)
+		return 0;
+
+	for (idx=1; idx<argc; ++idx) {
+		if (endsIn(dot_c_ext,argv[idx])) {				/* check for C source files */
+			++srcFileCnt;
+			append(&gstr.pCCSRC,argv[idx]);
+			append(&gstr.pCCSRC," ");
+			if (!*gstr.pOUT)
+			   assignn(&gstr.pOUT,argv[idx],strlen(argv[idx])-strlen(dot_c_ext));
+		}
+		else if (endsIn(dot_cc_ext,argv[idx])) {		/* check for C++ source files */
+			++srcFileCnt;
+			append(&gstr.pCXSRC,argv[idx]);
+			append(&gstr.pCXSRC," ");
+			if (!*gstr.pOUT)
+			   assignn(&gstr.pOUT,argv[idx],strlen(argv[idx])-strlen(dot_cc_ext));
+		}
+		else if (endsIn(dot_o_ext,argv[idx])) {			/* check for compiled object files */
+			++srcFileCnt;
+			append(&gstr.pOBJ,argv[idx]);
+			append(&gstr.pOBJ," ");
+			if (!*gstr.pOUT)
+			   assignn(&gstr.pOUT,argv[idx],strlen(argv[idx])-strlen(dot_o_ext));
+		}
+		else if (startsWith(name_option,argv[idx])) {	/* check for --name option */
+			assignn(&gstr.pOUT,argv[idx]+sizeof(name_option)-1,strlen(argv[idx])-(sizeof(name_option)-1));
+		}
+		else if (startsWith(lib_option,argv[idx])) {	/* check for -l option */
+			append(&gstr.pLIB,argv[idx]);
+			append(&gstr.pLIB," ");
+		}
+		else if (startsWith(mingw_option,argv[idx]))	/* check for -mingw option */
+			assignn(&gstr.pMINGW,argv[idx]+sizeof(mingw_option)-1,strlen(argv[idx])-(sizeof(mingw_option)-1));
+		else if (startsWith(ivl_option,argv[idx]))		/* check for -ivl   option */
+			assignn(&gstr.pIVL,argv[idx]+sizeof(ivl_option)-1,strlen(argv[idx])-(sizeof(ivl_option)-1));
+		else
+			return 0;	/* different from iverilog-vpi.sh, we don't ignore accept arguments */
+	}
+
+	if (0 == srcFileCnt)
+		assign(&gstr.pOUT,"");				/* in case they used --name with no source files */
+
+	if (!*gstr.pOUT) {						/* normally it's an error if there are no *.c,*.cc,*.o files */
+		if (!*gstr.pMINGW && !*gstr.pIVL)	/* unless they are just setting the IVL or MinGW registry entries */
+			usage();
+	}
+	else {
+		append(&gstr.pOUT,".vpi");			/* the result file should have a .vpi extension */
+		append(&gstr.pOUT," ");
+	}
+
+	return 1;
+}
+
+/* do minimal check that the MinGW root directory looks valid */
+
+static void checkMingwDir(char *root)
+{
+	int irv;
+	struct _stat stat_buf;
+
+	char *path;
+	initDynString(&path);
+	assign(&path,gstr.pMINGW);
+	appendBackSlash(&path);
+	append(&path,"bin\\" IVERILOG_VPI_CC ".exe");
+
+	irv = _stat(path,&stat_buf);
+	deInitDynString(path);
+
+	if (irv) {
+		fprintf(stderr,"error: %s does not appear to be the valid root directory\n",root);
+		fprintf(stderr,"       of MinGW.  Use the -mingw option of iverilog-vpi.exe to\n");
+		fprintf(stderr,"       point to the MinGW root directory.  For a Windows command\n");
+		fprintf(stderr,"       shell the option would be something like -mingw=c:\\mingw\n");
+		fprintf(stderr,"       For a Cygwin shell the option would be something like\n");
+		fprintf(stderr,"       -mingw=c:\\\\mingw\n");
+		myExit(5);
+	}
+}
+
+/* do minimal check that the Icarus Verilog root directory looks valid */
+
+static void checkIvlDir(char *root)
+{
+	int irv;
+	struct _stat stat_buf;
+
+	char *path;
+	initDynString(&path);
+	assign(&path,gstr.pIVL);
+	appendBackSlash(&path);
+	append(&path,"bin\\vvp.exe");
+
+	irv = _stat(path,&stat_buf);
+	deInitDynString(path);
+
+	if (irv) {
+		fprintf(stderr,"error: %s does not appear to be the valid root directory of\n",root);
+		fprintf(stderr,"       Icarus Verilog.  Use the -ivl option of iverilog-vpi.exe to\n");
+		fprintf(stderr,"       point to the Icarus Verilog root directory.  For a Windows\n");
+		fprintf(stderr,"       command shell the option would be something like -ivl=c:\\iverilog\n");
+		fprintf(stderr,"       For a Cygwin shell the option would be something like\n");
+		fprintf(stderr,"       -ivl=c:\\\\iverilog\n");
+		myExit(6);
+	}
+}
+
+/* see if we can find mingw root */
+
+#define IVL_REGKEY_MINGW "MingwDir"
+
+static void setup_mingw_environment()
+{
+	char *pOldPATH = getenv("PATH");		/* get current path */
+	
+	if (*gstr.pMINGW) {
+		checkMingwDir(gstr.pMINGW);
+		SetRegistryKey(IVL_REGKEY_MINGW,gstr.pMINGW);
+	}
+	else
+		if (!GetRegistryKey(IVL_REGKEY_MINGW,&gstr.pMINGW)) {
+			fprintf(stderr,"error: can not locate the MinGW root directory, use the -mingw option of\n");
+			fprintf(stderr,"       iverilog-vpi.exe to point to the MinGW root directory.  For\n");
+			fprintf(stderr,"       a Windows command shell the option would be something like\n");
+			fprintf(stderr,"       -mingw=c:\\mingw  For a Cygwin shell the option would be\n");
+			fprintf(stderr,"       something like -mingw=c:\\\\mingw\n");
+			myExit(5);
+		}
+
+	assign(&gstr.pNewPath,"PATH=");			/* create new path */
+	append(&gstr.pNewPath,gstr.pMINGW);
+	appendBackSlash(&gstr.pNewPath);
+	append(&gstr.pNewPath,"bin;");
+	append(&gstr.pNewPath,pOldPATH);
+
+	_putenv(gstr.pNewPath);					/* place new path in environment variable */
+}
+
+/* see if we can find iverilog root */
+
+#define IVL_REGKEY_IVL   "InstallDir"
+
+static void setup_ivl_environment()
+{
+	if (*gstr.pIVL) {
+		checkIvlDir(gstr.pIVL);
+		SetRegistryKey(IVL_REGKEY_IVL,gstr.pIVL);
+	}
+	else
+		if (!GetRegistryKey(IVL_REGKEY_IVL,&gstr.pIVL)) {
+			fprintf(stderr,"error: can not locate the Icarus Verilog root directory, use the -ivl option\n");
+			fprintf(stderr,"       of iverilog-vpi.exe to point to the Icarus Verilog root directory.\n");
+			fprintf(stderr,"       For a Windows command shell the option would be something like\n");
+			fprintf(stderr,"       -ivl=c:\\iverilog  For a Cygwin shell the option would be something\n");
+			fprintf(stderr,"       like -ivl=c:\\\\iverilog\n");
+			myExit(6);
+		}
+
+	/* build up the CFLAGS option string */
+
+	assign(&gstr.pCFLAGS,IVERILOG_VPI_CFLAGS);
+	append(&gstr.pCFLAGS," -I");
+	append(&gstr.pCFLAGS,gstr.pIVL);
+	appendBackSlash(&gstr.pCFLAGS);
+	append(&gstr.pCFLAGS,"include");
+
+	/* build up the LDFLAGS option string */
+
+	assign(&gstr.pLDLIBS,"-L");
+	append(&gstr.pLDLIBS,gstr.pIVL);
+	appendBackSlash(&gstr.pLDLIBS);
+	append(&gstr.pLDLIBS,"lib ");
+	append(&gstr.pLDLIBS,IVERILOG_VPI_LDLIBS);
+}
+
+/* compile source modules */
+
+static void compile(char *pSource, char **pObject, char *ext, int *compile_errors, char *compiler)
+{
+	char *ptr1 = pSource;
+	char *ptr2 = strchr(pSource,' ');
+	char *buf=0,*src=0,*obj=0;
+
+	while (ptr2) {
+		int len = ptr2 - ptr1;
+		assignn(&src,ptr1,len);
+
+		assignn(&obj,ptr1,len-strlen(ext));		/* strip off the extension */
+		append (&obj,".o");
+
+		assign (&buf,compiler);
+		append (&buf," -c -o ");
+		append (&buf,obj);
+		append (&buf," ");
+		append (&buf,gstr.pCFLAGS);
+		append (&buf," ");
+		append (&buf,src);
+
+		append (pObject,obj);
+		append (pObject," ");
+
+		printf("%s\n",buf);
+
+		if (system(buf))
+			++*compile_errors;
+
+		ptr1 = ptr2 + 1;					/* advance to next token */
+		ptr2 = strchr(ptr1,' ');
+	}
+
+	free(buf);
+	free(src);
+	free(obj);
+}
+
+/* using the global strings, compile and link */
+
+static void compile_and_link()
+{
+	char *buf=0;
+	int iRet, compile_errors = 0;
+
+	/* print out the mingw and ivl directories to help the user debug problems */
+
+	printf("info:  %s will be used as the MinGW root directory.\n",gstr.pMINGW);
+	checkMingwDir(gstr.pMINGW);
+
+	printf("info:  %s will be used as the Icarus Verilog root directory.\n",gstr.pIVL);
+	checkIvlDir(gstr.pIVL);
+
+	/* compile */
+
+	compile(gstr.pCCSRC,&gstr.pOBJ,".c" ,&compile_errors,IVERILOG_VPI_CC );		/* compile the C   source files */
+	compile(gstr.pCXSRC,&gstr.pOBJ,".cc",&compile_errors,IVERILOG_VPI_CXX);		/* compile the C++ source files */
+
+	if (compile_errors) {
+		fprintf(stderr,"iverilog-vpi: Some %d files failed to compile.\n",compile_errors);
+		myExit(2);
+	}
+
+	/* link */
+
+	assign(&buf,IVERILOG_VPI_LD);
+	append(&buf," -o ");
+	append(&buf,gstr.pOUT);				/* has a trailing space */
+	append(&buf,IVERILOG_VPI_LDFLAGS);
+	append(&buf," ");
+	append(&buf,gstr.pOBJ)				/* has a trailing space */;
+	append(&buf,gstr.pLIB);				/* has a trailing space */
+	append(&buf,gstr.pLDLIBS);
+
+	printf("%s\n",buf);
+
+	iRet = system(buf);
+
+	free(buf);
+
+	if (iRet)
+		myExit(3);
+}
+
+/* program execution starts here */
+
+int main(int argc, char *argv[])
+{
+	init();
+
+	if (!parse(argc,argv))
+		usage();
+
+	setup_mingw_environment();
+	setup_ivl_environment();
+
+	if (*gstr.pOUT)				/* are there any *.c,*.cc,*.o files specified */
+		compile_and_link();
+
+	myExit(0);
+}

driver-vpi/res.rc

@@ -0,0 +1,38 @@
+
+// LANGUAGE ENGLISH
+LANGUAGE 9, 4
+
+
+/////////////////////////////////////////////////////////////////////////////
+//
+// Version
+//
+
+1 VERSIONINFO
+ FILEVERSION 2002,11,13,0
+ PRODUCTVERSION 0,7,0,0
+ FILEFLAGSMASK 0x3fL
+ FILEFLAGS 0x2L
+ FILEOS 0x40004L
+ FILETYPE 0x2L
+ FILESUBTYPE 0x0L
+BEGIN
+    BLOCK "StringFileInfo"
+    BEGIN
+        BLOCK "040904b0"
+        BEGIN
+            VALUE "CompanyName", "Icarus Verilog\0"
+            VALUE "FileDescription", "Icarus Veriog VPI Tool\0"
+            VALUE "FileVersion", "2002, 11, 13, 0\0"
+            VALUE "InternalName", "iverilog-vpi\0"
+            VALUE "LegalCopyright", "Copyright 2002 Gus Baldauf\0"
+            VALUE "OriginalFilename", "iverilog-vpi.exe\0"
+            VALUE "ProductName", "Icarus Verilog\0"
+            VALUE "ProductVersion", "0, 7, 0, 0\0"
+        END
+    END
+    BLOCK "VarFileInfo"
+    BEGIN
+        VALUE "Translation", 0x409, 1200
+    END
+END

driver/.cvsignore

@@ -10,3 +10,6 @@ cfparse.output
 cflexor.c
 foo.*
 iverilog
+iverilog.ps
+iverilog.pdf
+tmp.pdf

driver/Makefile.in

@@ -3,9 +3,7 @@
 #    and/or modify it in source code form under the terms of the GNU
 #    Library General Public License as published by the Free Software
 #    Foundation; either version 2 of the License, or (at your option)
-#    any later version. In order to redistribute the software in
-#    binary form, you will need a Picture Elements Binary Software
-#    License.
+#    any later version.
 #
 #    This program is distributed in the hope that it will be useful,
 #    but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -18,12 +16,12 @@
 #    59 Temple Place - Suite 330
 #    Boston, MA 02111-1307, USA
 #
-#ident "$Id: Makefile.in,v 1.12 2002/05/24 01:13:00 steve Exp $"
+#ident "$Id: Makefile.in,v 1.16 2002/12/08 03:06:30 steve Exp $"
 #
 #
 SHELL = /bin/sh
 
-VERSION = 0.6
+VERSION = 0.7
 
 prefix = @prefix@
 exec_prefix = @exec_prefix@
@@ -37,7 +35,6 @@ includedir = $(prefix)/include
 mandir = @mandir@
 
 dllib=@DLLIB@
-rdynamic=@rdynamic@
 
 CC = @CC@
 CXX = @CXX@
@@ -56,7 +53,7 @@ clean:
 	rm -f *.o lexor.c parse.c parse.h parse.output
 	rm -f cflexor.c cfparse.c cfparse.h cfparse.output
 
-O = main.o build_string.o lexor.o parse.o cflexor.o cfparse.o
+O = main.o build_string.o lexor.o parse.o substit.o cflexor.o cfparse.o
 
 iverilog@EXEEXT@: $O
 	$(CC) $(LDFLAGS) $O -o iverilog@EXEEXT@ @EXTRALIBS@
@@ -75,7 +72,7 @@ cfparse.h cfparse.c: cfparse.y
 
 
 main.o: main.c globals.h
-	$(CC) $(CFLAGS) -c -DCXX='"@CXX@"' -DIVL_ROOT='"@libdir@/ivl"'  -DIVL_INC='"@includedir@"' -DIVL_LIB='"@libdir@"' -DRDYNAMIC=\"$(rdynamic)\" -DDLLIB='"@DLLIB@"' -DEXEEXT='"@EXEEXT@"' $(srcdir)/main.c
+	$(CC) $(CFLAGS) -c -DCXX='"@CXX@"' -DIVL_ROOT='"@libdir@/ivl"'  -DIVL_INC='"@includedir@"' -DIVL_LIB='"@libdir@"' -DDLLIB='"@DLLIB@"' $(srcdir)/main.c
 
 build_string.o: build_string.c globals.h
 lexor.o: lexor.c parse.h globals.h

driver/build_string.c

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: build_string.c,v 1.10 2002/05/28 02:25:03 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: build_string.c,v 1.11 2002/08/12 01:35:01 steve Exp $"
 #endif
 
 # include "config.h"
@@ -165,6 +165,9 @@ int build_string(char*output, size_t olen, const char*pattern)
 
 /*
  * $Log: build_string.c,v $
+ * Revision 1.11  2002/08/12 01:35:01  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.10  2002/05/28 02:25:03  steve
  *  Pass library paths through -Cfile instead of command line.
  *

driver/cfparse.y

@@ -18,7 +18,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: cfparse.y,v 1.7 2002/05/28 20:40:37 steve Exp $"
+#ident "$Id: cfparse.y,v 1.8 2002/06/23 20:10:51 steve Exp $"
 #endif
 
 
@@ -78,9 +78,11 @@ item
      of a source file. Add the file to the file list. */
 
 	: TOK_STRING
-		{ translate_file_name($1);
-		  process_file_name($1);
+		{ char*tmp = substitutions($1);
+		  translate_file_name(tmp);
+		  process_file_name(tmp);
 		  free($1);
+		  free(tmp);
 		}
 
   /* The -a flag is completely ignored. */
@@ -91,11 +93,13 @@ item
      as an ordinary source file. */
 
         | TOK_Dv TOK_STRING
-		{ translate_file_name($2);
-		  process_file_name($2);
+		{ char*tmp = substitutions($2);
+		  translate_file_name(tmp);
+		  process_file_name(tmp);
 		  fprintf(stderr, "%s:%u: Ignoring -v in front of %s\n",
 			  @1.text, @1.first_line, $2);
 		  free($2);
+		  free(tmp);
 		}
 
   /* This rule matches "-y <path>" sequences. This does the same thing
@@ -103,18 +107,24 @@ item
      directory list. */
 
         | TOK_Dy TOK_STRING
-		{ process_library_switch($2);
+		{ char*tmp = substitutions($2);
+		  process_library_switch(tmp);
 		  free($2);
+		  free(tmp);
 		}
 
         | TOK_LIBDIR TOK_PLUSARG
-		{ process_library_switch($2);
+		{ char*tmp = substitutions($2);
+		  process_library_switch(tmp);
 		  free($2);
+		  free(tmp);
 		}
 
         | TOK_LIBDIR_NOCASE TOK_PLUSARG
-		{ process_library_nocase_switch($2);
+		{ char*tmp = substitutions($2);
+		  process_library_nocase_switch(tmp);
 		  free($2);
+		  free(tmp);
 		}
 
 	| TOK_DEFINE TOK_PLUSARG
@@ -161,8 +171,10 @@ inc_args
 	;
 
 inc_arg : TOK_PLUSARG
-		{ process_include_dir($1);
+		{ char*tmp = substitutions($1);
+		  process_include_dir(tmp);
 		  free($1);
+		  free(tmp);
 		}
 	;
 

driver/cfparse_misc.h

@@ -19,8 +19,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT)
-#ident "$Id: cfparse_misc.h,v 1.3 2002/01/02 02:39:34 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: cfparse_misc.h,v 1.4 2002/08/12 01:35:01 steve Exp $"
 #endif
 
 /*
@@ -40,6 +40,9 @@ extern YYLTYPE yylloc;
 
 /*
  * $Log: cfparse_misc.h,v $
+ * Revision 1.4  2002/08/12 01:35:01  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.3  2002/01/02 02:39:34  steve
  *  Use my own cfltype to defend against bison 1.30.
  *

driver/globals.h

@@ -18,8 +18,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: globals.h,v 1.14 2002/05/28 20:40:37 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: globals.h,v 1.16 2002/08/12 01:35:01 steve Exp $"
 #endif
 
 # include  <stddef.h>
@@ -60,6 +60,9 @@ extern const char*targ;
   /* This is the language generation flag. */
 extern const char*generation;
 
+  /* Perform variable substitutions on the string. */
+extern char* substitutions(const char*str);
+
   /* Add the name to the list of source files. */
 extern void process_file_name(const char*name);
 
@@ -89,6 +92,12 @@ extern int build_string(char*out, size_t olen, const char*pattern);
 
 /*
  * $Log: globals.h,v $
+ * Revision 1.16  2002/08/12 01:35:01  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.15  2002/06/23 20:10:51  steve
+ *  Variable substitution in command files.
+ *
  * Revision 1.14  2002/05/28 20:40:37  steve
  *  ivl indexes the search path for libraries, and
  *  supports case insensitive module-to-file lookup.

driver/iverilog.man

@@ -1,4 +1,4 @@
-.TH iverilog 1 "$Date: 2002/05/28 20:46:51 $" Version "$Date: 2002/05/28 20:46:51 $"
+.TH iverilog 1 "$Date: 2002/06/23 20:10:51 $" Version "$Date: 2002/06/23 20:10:51 $"
 .SH NAME
 iverilog - Icarus Verilog compiler
 
@@ -187,7 +187,7 @@ mostly by EDIF format output.
 .SH "WARNING TYPES"
 These are the types of warnings that can be selected by the \fB-W\fP
 switch. All the warning types (other then \fBall\fP) can also be
-prefixed with \fBno-\fP to turn of that warning. This is most useful
+prefixed with \fBno-\fP to turn off that warning. This is most useful
 after a \fB-Wall\fP argument to suppress isolated warning types.
 
 .TP 8
@@ -217,7 +217,8 @@ well as # comments, if the # starts the line.
 .TP 8
 .I "file name"
 A simple file name or file path is taken to be the name of a Verilog
-source file. The path starts with the first non-white-space character.
+source file. The path starts with the first non-white-space
+character. Variables are substitued in file names.
 
 .TP 8
 .B -y\ \fIlibdir\fP
@@ -225,6 +226,8 @@ A \fB-y\fP token prefixes a library directory in the command file,
 exactly like it does on the command line. The parameter to the \fB-y\fP
 flag may be on the same line or the next non-comment line.
 
+Variables in the \fIlibdir\fP are substituted.
+
 .TP 8
 .B +incdir+\fIincludedir\fP
 The \fB+incdir+\fP token in command files gives directories to search
@@ -233,6 +236,8 @@ command line. The difference is that multiple \fI+includedir\fP
 directories are valid parameters to a single \fB+incdir+\fP token,
 although you may also have multiple \fB+incdir+\fP lines.
 
+Variables in the \fIincludedir\fP are substituted.
+
 .TP 8
 .B +libext+\fIext\fP
 The \fB+libext\fP token in command files fives file extensions to try
@@ -268,6 +273,18 @@ become munged.
 .B +tolower-filename\fP
 This is similar to the \fB+toupper-filename\fP hack described above.
 
+.SH "VARIABLES IN COMMAND FILES"
+
+In certain cases, iverilog supports variables in command files. These
+are strings of the form "$(\fIvarname\fP)", where \fIvarname\fP is the
+name of the environment variable to read. The entire string is
+replaced with the contents of that variable. Variables are only
+substitued in contexts that explicitly support them, including file
+and directory strings.
+
+Variable values come from the operating system environment, and not
+from preprocessor defines elsewhere in the file or the command line.
+
 .SH EXAMPLES 
 These examples assume that you have a Verilog source file called hello.v in
 the current directory
@@ -299,7 +316,7 @@ vvp(1),
 
 .SH COPYRIGHT
 .nf
-Copyright \(co  2000 Stephen Williams
+Copyright \(co  2002 Stephen Williams
 
 This document can be freely redistributed according to the terms of the 
 GNU General Public License version 2.0

driver/main.c

@@ -16,7 +16,7 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#ident "$Id: main.c,v 1.41 2002/05/28 20:40:37 steve Exp $"
+#ident "$Id: main.c,v 1.49 2002/12/04 03:26:59 steve Exp $"
 
 # include "config.h"
 
@@ -44,6 +44,7 @@ const char HELP[] =
 
 #ifdef __MINGW32__
 #include <windows.h>
+#include <libiberty.h>
 #endif
 
 #if HAVE_GETOPT_H
@@ -68,10 +69,6 @@ extern const char*optarg;
 # define IVL_ROOT "."
 #endif
 
-#ifndef RDYNAMIC
-# define RDYNAMIC "-rdynamic"
-#endif
-
 # include  "globals.h"
 
 #ifdef __MINGW32__
@@ -84,7 +81,7 @@ extern void cfreset(FILE*fd, const char*path);
 
 const char*base = 0;
 const char*mtm  = 0;
-const char*opath = "a.out" EXEEXT;
+const char*opath = "a.out";
 const char*npath = 0;
 const char*targ  = "vvp";
 const char*depfile = 0;
@@ -122,6 +119,72 @@ char tmp[MAXSIZE];
 
 static char ivl_root[MAXSIZE];
 
+#ifdef __MINGW32__
+# include  <io.h>
+# include  <fcntl.h>
+static FILE*fopen_safe(const char*path)
+{
+      FILE*file = 0;
+      int fd;
+
+      fd = _open(path, _O_WRONLY|_O_CREAT|_O_EXCL, 0700);
+      if (fd != -1)
+	    file = _fdopen(fd, "w");
+
+       return file;
+}
+#else
+# include  <fcntl.h>
+static FILE*fopen_safe(const char*path)
+{
+      FILE*file = 0;
+      int fd;
+
+      fd = open(path, O_WRONLY|O_CREAT|O_EXCL, 0700);
+      if (fd != -1)
+	    file = fdopen(fd, "w");
+
+       return file;
+}
+#endif
+
+static const char*my_tempfile(const char*str, FILE**fout)
+{
+      FILE*file;
+      int retry;
+
+      static char pathbuf[8192];
+
+      const char*tmpdir = getenv("TMP");
+      if (tmpdir == 0)
+	    tmpdir = getenv("TMPDIR");
+      if (tmpdir == 0)
+	    tmpdir = getenv("TEMP");
+#ifdef __MINGW32__
+      if (tmpdir == 0)
+	    tmpdir = "C:\\TEMP";
+#else
+      if (tmpdir == 0)
+	    tmpdir = "/tmp";
+#endif
+
+      assert(tmpdir);
+      assert((strlen(tmpdir) + strlen(str)) < sizeof pathbuf - 10);
+
+      srand(getpid());
+      retry = 100;
+      file = NULL;
+      while ((retry > 0) && (file == NULL)) {
+	    unsigned code = rand();
+	    sprintf(pathbuf, "%s%c%s%04x", tmpdir, sep, str, code);
+	    file = fopen_safe(pathbuf);
+	    retry -= 1;
+      }
+
+      *fout = file;
+      return pathbuf;
+}
+
 /*
  * This is the default target type. It looks up the bits that are
  * needed to run the command from the configuration file (which is
@@ -179,97 +242,6 @@ static int t_default(char*cmd, unsigned ncmd)
       return 0;
 }
 
-/*
- * This function handles the vvm target. After preprocessing, run the
- * ivl translator to get C++, then run g++ to make an executable
- * program out of that.
- */
-static int t_vvm(char*cmd, unsigned ncmd)
-{
-      int rc;
-
-      const char*pattern = lookup_pattern("<ivl>");
-      if (pattern == 0) {
-	    fprintf(stderr, "No such target: %s\n", targ);
-	    return -1;
-      }
-
-      tmp[0] = ' ';
-      tmp[1] = '|';
-      tmp[2] = ' ';
-      rc = build_string(tmp+3, sizeof tmp - 3, pattern);
-      cmd = realloc(cmd, ncmd+3+rc+1);
-
-#ifdef __MINGW32__
-      {
-	char *t;
-	for (t = tmp; *t; t++)
-	  {
-	    if (*t == '/') *t = '\\';
-	  }
-      }
-#endif
-
-
-      strcpy(cmd+ncmd, tmp);
-
-
-      if (verbose_flag)
-	    printf("translate: %s\n", cmd);
-
-      rc = system(cmd);
-      remove(source_path);
-      if (rc != 0) {
-	    if (WIFEXITED(rc)) {
-		  fprintf(stderr, "errors translating Verilog program.\n");
-		  return WEXITSTATUS(rc);
-	    } else {
-		  fprintf(stderr, "Command signaled: %s\n", cmd);
-		  return -1;
-	    }
-      }
-
-#if defined(__MINGW32__)
-	/* In the Windows world, the path to headers and libraries
-	   for vvm is relative the ivl_root, which is in something like:
-
-	       d:\iverilog\lib\ivl    <-- ivl_root
-	       d:\iverilog\include    <-- vvm headers
-	       d:\iverilog\lib        <-- vvm libraries
-
-	   So we make up all the ugly references that are the g++
-	   command line to compile a .cc file generated by vvm. */
-      sprintf(tmp, "%s " RDYNAMIC " -s -fno-exceptions -o %s "
-	      "-I%s\\..\\..\\include -L%s\\.. %s.cc -lvvm -lvpip %s",
-	      CXX, opath, ivl_root, ivl_root, opath, DLLIB);
-#else
-	/* In the UNIX universe, life is easy. The configure script
-	   has figured everything out and wrote it into the Makefile,
-	   which passes it on as the IVL_INC and IVL_LIB defines. */
-      sprintf(tmp, "%s " RDYNAMIC " -s -fno-exceptions -o %s -I%s "
-	      "-L%s %s.cc -lvvm -lvpip %s", CXX, opath, IVL_INC, 
-	      IVL_LIB, opath, DLLIB);
-#endif
-      if (verbose_flag)
-	    printf("compile: %s\n", tmp);
-
-      rc = system(tmp);
-      if (rc != 0) {
-	    if (WIFEXITED(rc)) {
-		  fprintf(stderr, "errors compiling translated program.\n");
-		  return WEXITSTATUS(rc);
-	    } else {
-		  fprintf(stderr, "Command signaled: %s\n", tmp);
-		  return -1;
-	    }
-      }
-
-      sprintf(tmp, "%s.cc", opath);
-      unlink(tmp);
-
-      return 0;
-}
-
 
 static void process_warning_switch(const char*name)
 {
@@ -414,6 +386,7 @@ int main(int argc, char **argv)
 
 	base = ivl_root;
       }
+
 #else
         /* In a UNIX environment, the IVL_ROOT from the Makefile is
 	   dependable. It points to the $prefix/lib/ivl directory,
@@ -424,9 +397,7 @@ int main(int argc, char **argv)
 
 	/* Create a temporary file for communicating input parameters
 	   to the preprocessor. */
-      source_path = strdup(tempnam(NULL, "ivrlg"));
-      assert(source_path);
-      source_file = fopen(source_path, "w");
+      source_path = strdup(my_tempfile("ivrlg", &source_file));
       if (NULL == source_file) {
 	    fprintf(stderr, "%s: Error opening temporary file %s\n",
 		    argv[0], source_path);
@@ -436,9 +407,7 @@ int main(int argc, char **argv)
 
 	/* Create another temporary file for passing configuration
 	   information to ivl. */
-      iconfig_path = strdup(tempnam(NULL, "ivrlh"));
-      assert(iconfig_path);
-      iconfig_file = fopen(iconfig_path, "w");
+      iconfig_path = strdup(my_tempfile("ivrlh", &iconfig_file));
       if (NULL == iconfig_file) {
 	    fprintf(stderr, "%s: Error opening temporary file %s\n",
 		    argv[0], iconfig_path);
@@ -710,17 +679,37 @@ int main(int argc, char **argv)
 	/* Done writing to the iconfig file. Close it now. */
       fclose(iconfig_file);
 
-      if (strcmp(targ,"vvm") == 0)
-	    return t_vvm(cmd, ncmd);
-      else {
-	    return t_default(cmd, ncmd);
-      }
+      return t_default(cmd, ncmd);
 
       return 0;
 }
 
 /*
  * $Log: main.c,v $
+ * Revision 1.49  2002/12/04 03:26:59  steve
+ *  Mingw32 compatible temp file management.
+ *
+ * Revision 1.48  2002/12/04 02:29:36  steve
+ *  Use O_EXCL when opening temp files.
+ *
+ * Revision 1.47  2002/08/12 01:27:48  steve
+ *  Escape the backslash in the windows file name.
+ *
+ * Revision 1.46  2002/08/10 22:36:59  steve
+ *  No longer any nead for -rdynamic flag
+ *
+ * Revision 1.45  2002/08/10 22:27:13  steve
+ *  Kill links to vvm.
+ *
+ * Revision 1.44  2002/07/15 00:33:50  steve
+ *  Improve temporary file name guess.
+ *
+ * Revision 1.43  2002/07/14 23:32:31  steve
+ *  No longer need the .exe on generated files.
+ *
+ * Revision 1.42  2002/07/14 23:11:35  steve
+ *  Do temp file creation by hand.
+ *
  * Revision 1.41  2002/05/28 20:40:37  steve
  *  ivl indexes the search path for libraries, and
  *  supports case insensitive module-to-file lookup.

driver/substit.c

@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2002 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: substit.c,v 1.4 2002/08/12 01:35:01 steve Exp $"
+#endif
+
+# include  <string.h>
+# include  <stdlib.h>
+#ifdef HAVE_MALLOC_H
+# include  <malloc.h>
+#endif
+
+
+char* substitutions(const char*str)
+{
+      size_t nbuf = strlen(str) + 1;
+      char*buf = malloc(nbuf);
+      char*cp = buf;
+
+      while (*str) {
+
+	    if ((str[0] == '$') && (str[1] == '(')) {
+		    /* If I find a $(x) string in the source, replace
+		       it in the destination with the contents of the
+		       environment variable x. */
+		  char*name;
+		  char*value;
+		  const char*ep = strchr(str, ')');
+		  str += 2;
+
+		  name = malloc(ep-str+1);
+		  strncpy(name, str, ep-str);
+		  name[ep-str] = 0;
+
+		  str = ep + 1;
+
+		  value = getenv(name);
+		  free(name);
+		  if (value == 0)
+			continue;
+
+		  if (strlen(value) >= (nbuf - (cp-buf))) {
+			size_t old_size = cp - buf;
+			nbuf = (cp - buf) + strlen(value) + 1;
+			buf = realloc(buf, nbuf);
+			cp = buf + old_size;
+		  }
+
+		  strcpy(cp, value);
+		  cp += strlen(cp);
+
+	    } else {
+		  if ( (cp - buf) == nbuf ) {
+			size_t old_size = nbuf;
+			nbuf = old_size + 32;
+			buf = realloc(buf, nbuf);
+			cp = buf + old_size;
+		  }
+
+		  *cp++ = *str++;
+	    }
+      }
+
+	/* Add the trailing nul to the string, and reallocate the
+	   buffer to be a tight fit. */
+      if ( (cp - buf) == nbuf ) {
+	    size_t old_size = nbuf;
+	    nbuf = old_size + 1;
+	    buf = realloc(buf, nbuf);
+	    buf[old_size] = 0;
+      } else {
+	    *cp++ = 0;
+	    nbuf = cp - buf;
+	    buf = realloc(buf, nbuf);
+      }
+
+      return buf;
+}
+
+
+/*
+ * $Log: substit.c,v $
+ * Revision 1.4  2002/08/12 01:35:01  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.3  2002/08/11 23:47:04  steve
+ *  Add missing Log and Ident strings.
+ *
+ * Revision 1.2  2002/06/25 01:33:01  steve
+ *  include malloc.h only when available.
+ *
+ * Revision 1.1  2002/06/23 20:10:51  steve
+ *  Variable substitution in command files.
+ *
+ */
+

dup_expr.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2002 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: dup_expr.cc,v 1.7 2002/01/28 00:52:41 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: dup_expr.cc,v 1.9 2002/11/09 00:25:27 steve Exp $"
 #endif
 
 # include "config.h"
@@ -65,6 +65,21 @@ NetETernary* NetETernary::dup_expr() const
       return tmp;
 }
 
+NetEUFunc* NetEUFunc::dup_expr() const
+{
+      NetEUFunc*tmp;
+      svector<NetExpr*> tmp_parms (parms_.count());
+
+      for (unsigned idx = 0 ;  idx < tmp_parms.count() ;  idx += 1) {
+	    assert(parms_[idx]);
+	    tmp_parms[idx] = parms_[idx]->dup_expr();
+      }
+
+      tmp = new NetEUFunc(func_, result_->dup_expr(), tmp_parms);
+
+      return tmp;
+}
+
 NetEUnary* NetEUnary::dup_expr() const
 {
       NetEUnary*tmp = new NetEUnary(op_, expr_->dup_expr());
@@ -74,6 +89,12 @@ NetEUnary* NetEUnary::dup_expr() const
 
 /*
  * $Log: dup_expr.cc,v $
+ * Revision 1.9  2002/11/09 00:25:27  steve
+ *  Add dup_expr for user defined function calls.
+ *
+ * Revision 1.8  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.7  2002/01/28 00:52:41  steve
  *  Add support for bit select of parameters.
  *  This leads to a NetESelect node and the
@@ -94,12 +115,5 @@ NetEUnary* NetEUnary::dup_expr() const
  * Revision 1.3  2000/05/04 03:37:58  steve
  *  Add infrastructure for system functions, move
  *  $time to that structure and add $random.
- *
- * Revision 1.2  2000/02/23 02:56:54  steve
- *  Macintosh compilers do not support ident.
- *
- * Revision 1.1  1999/11/27 19:07:57  steve
- *  Support the creation of scopes.
- *
  */
 

elab_anet.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: elab_anet.cc,v 1.4 2001/12/03 04:47:14 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: elab_anet.cc,v 1.5 2002/08/12 01:34:58 steve Exp $"
 #endif
 
 # include "config.h"
@@ -149,6 +149,9 @@ NetNet* PEIdent::elaborate_anet(Design*des, NetScope*scope) const
 
 /*
  * $Log: elab_anet.cc,v $
+ * Revision 1.5  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.4  2001/12/03 04:47:14  steve
  *  Parser and pform use hierarchical names as hname_t
  *  objects instead of encoded strings.

elab_expr.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: elab_expr.cc,v 1.60 2002/05/24 00:44:54 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: elab_expr.cc,v 1.66 2002/09/21 21:28:18 steve Exp $"
 #endif
 
 # include "config.h"
@@ -120,7 +120,8 @@ NetEBinary* PEBinary::elaborate_expr_base_(Design*des,
 	  case '^':
 	  case '&':
 	  case '|':
-	  case 'O':
+	  case 'O': // NOR (~|)
+	  case 'A': // NAND (~&)
 	  case 'X':
 	    tmp = new NetEBBits(op_, lp, rp);
 	    tmp->set_line(*this);
@@ -201,7 +202,7 @@ NetExpr* PECallFunction::elaborate_sfunc_(Design*des, NetScope*scope) const
 
 	    PExpr*expr = parms_[0];
 	    NetExpr*sub = expr->elaborate_expr(des, scope, true);
-	    verinum val (sub->expr_width(), sizeof(unsigned));
+	    verinum val (sub->expr_width(), 8*sizeof(unsigned));
 	    delete sub;
 
 	    sub = new NetEConst(val);
@@ -375,6 +376,8 @@ NetExpr* PEConcat::elaborate_expr(Design*des, NetScope*scope, bool) const
       NetEConcat*tmp = new NetEConcat(parms_.count(), repeat);
       tmp->set_line(*this);
 
+      unsigned wid_sum = 0;
+
 	/* Elaborate all the parameters and attach them to the concat node. */
       for (unsigned idx = 0 ;  idx < parms_.count() ;  idx += 1) {
 	    assert(parms_[idx]);
@@ -390,9 +393,12 @@ NetExpr* PEConcat::elaborate_expr(Design*des, NetScope*scope, bool) const
 		  des->errors += 1;
 	    }
 
+	    wid_sum += ex->expr_width();
 	    tmp->set(idx, ex);
       }
 
+      tmp->set_width(wid_sum * tmp->repeat());
+
       return tmp;
 }
 
@@ -627,11 +633,21 @@ NetExpr* PEIdent::elaborate_expr(Design*des, NetScope*scope,
 		  unsigned idx = net->sb_to_idx(msv);
 
 		  if (idx >= net->pin_count()) {
-			cerr << get_line() << ": internal error: "
-			     << "bit " << msv << " out of range of net "
+			  /* The bit select is out of range of the
+			     vector. This is legal, but returns a
+			     constant 1'bx value. */
+			verinum x (verinum::Vx);
+			NetEConst*tmp = new NetEConst(x);
+			tmp->set_line(*this);
+
+			cerr << get_line() << ": warning: Bit select ["
+			     << msv << "] out of range of vector "
 			     << net->name() << "[" << net->msb()
 			     << ":" << net->lsb() << "]." << endl;
-			return 0;
+			cerr << get_line() << ":        : Replacing "
+			     << "expression with a constant 1'bx." << endl;
+			delete msn;
+			return tmp;
 		  }
 
 		  NetESignal*tmp = new NetESignal(net, idx, idx);
@@ -692,7 +708,7 @@ NetExpr* PEIdent::elaborate_expr(Design*des, NetScope*scope,
 	    assert(idx_ == 0);
 	    NetExpr*i = msb_->elaborate_expr(des, scope);
 	    if (msb_ && i == 0) {
-		  cerr << get_line() << ": error: Unable to exaborate "
+		  cerr << get_line() << ": error: Unable to elaborate "
 			"index expression `" << *msb_ << "'" << endl;
 		  des->errors += 1;
 		  return 0;
@@ -869,6 +885,24 @@ NetExpr* PEUnary::elaborate_expr(Design*des, NetScope*scope, bool) const
 
 /*
  * $Log: elab_expr.cc,v $
+ * Revision 1.66  2002/09/21 21:28:18  steve
+ *  Allow constant bit selects out of range.
+ *
+ * Revision 1.65  2002/09/18 04:08:45  steve
+ *  Spelling errors.
+ *
+ * Revision 1.64  2002/09/12 15:49:43  steve
+ *  Add support for binary nand operator.
+ *
+ * Revision 1.63  2002/08/19 02:39:16  steve
+ *  Support parameters with defined ranges.
+ *
+ * Revision 1.62  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.61  2002/06/14 21:38:41  steve
+ *  Fix expression width for repeat concatenations.
+ *
  * Revision 1.60  2002/05/24 00:44:54  steve
  *  Add support for $bits (SystemVerilog)
  *

elab_lval.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: elab_lval.cc,v 1.18 2002/03/09 04:02:26 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: elab_lval.cc,v 1.23 2002/11/21 23:27:51 steve Exp $"
 #endif
 
 # include "config.h"
@@ -67,7 +67,7 @@
  */
 NetAssign_* PExpr::elaborate_lval(Design*des, NetScope*scope) const
 {
-      NetNet*ll = 0; //XXXXelaborate_net(des, scope, 0, 0, 0, 0);
+      NetNet*ll = 0;
       if (ll == 0) {
 	    cerr << get_line() << ": Assignment l-value too complex."
 		 << endl;
@@ -139,14 +139,13 @@ NetAssign_* PEIdent::elaborate_lval(Design*des, NetScope*scope) const
 
       if (reg == 0) {
 	    NetMemory*mem = des->find_memory(scope, path_);
-	    if (mem != 0) {
-		  cerr << get_line() << ": sorry: I cannot handle "
-		       << "memories in this l-value context." << endl;
-	    } else {
-		  cerr << get_line() << ": error: Could not find variable ``"
-		       << path_ << "'' in ``" << scope->name() <<
-			"''" << endl;
-	    }
+	    if (mem != 0)
+		  return elaborate_mem_lval_(des, scope, mem);
+
+	    cerr << get_line() << ": error: Could not find variable ``"
+		 << path_ << "'' in ``" << scope->name() <<
+		  "''" << endl;
+
 	    des->errors += 1;
 	    return 0;
       }
@@ -171,16 +170,20 @@ NetAssign_* PEIdent::elaborate_lval(Design*des, NetScope*scope) const
 	    verinum*vl = lsb_->eval_const(des, scope);
 	    if (vl == 0) {
 		  cerr << lsb_->get_line() << ": error: "
-			"Part select expressions must be constant: "
-		       << *lsb_;
+			"Part select expressions must be constant."
+		       << endl;
+		  cerr << lsb_->get_line() << ":      : This lsb expression "
+			"violates the rule: " << *lsb_ << endl;
 		  des->errors += 1;
 		  return 0;
 	    }
 	    verinum*vm = msb_->eval_const(des, scope);
-	    if (vl == 0) {
+	    if (vm == 0) {
 		  cerr << msb_->get_line() << ": error: "
-			"Part select expressions must be constant: "
-		       << *msb_;
+			"Part select expressions must be constant."
+		       << endl;
+		  cerr << msb_->get_line() << ":      : This msb expression "
+			"violates the rule: " << *msb_ << endl;
 		  des->errors += 1;
 		  return 0;
 	    }
@@ -275,6 +278,47 @@ NetAssign_* PEIdent::elaborate_lval(Design*des, NetScope*scope) const
       return lv;
 }
 
+NetAssign_* PEIdent::elaborate_mem_lval_(Design*des, NetScope*scope,
+					NetMemory*mem) const
+{
+      if (msb_ == 0) {
+	    cerr << get_line() << ": error: Assign to memory \""
+		 << mem->name() << "\" requires a word select index."
+		 << endl;
+	    des->errors += 1;
+	    return 0;
+      }
+
+      if (msb_ && lsb_) {
+	    cerr << get_line() << ": error: Cannot use part select on "
+		 << "memory \"" << mem->name() << ".\"" << endl;
+	    des->errors += 1;
+	    return 0;
+      }
+
+      assert(msb_ && !lsb_);
+
+      NetExpr*ix = msb_->elaborate_expr(des, scope);
+      if (ix == 0)
+	    return 0;
+
+	/* Evaluate the memory index expression down as must as
+	   possible. Ideally, we can get it down to a constant. */
+      if (! dynamic_cast<NetEConst*>(ix)) {
+	    NetExpr*tmp = ix->eval_tree();
+	    if (tmp) {
+		  tmp->set_line(*ix);
+		  delete ix;
+		  ix = tmp;
+	    }
+      }
+
+      NetAssign_*lv = new NetAssign_(mem);
+      lv->set_bmux(ix);
+      lv->set_part(0, mem->width());
+      return lv;
+}
+
 NetAssign_* PENumber::elaborate_lval(Design*des, NetScope*) const
 {
       cerr << get_line() << ": error: Constant values not allowed "
@@ -285,6 +329,23 @@ NetAssign_* PENumber::elaborate_lval(Design*des, NetScope*) const
 
 /*
  * $Log: elab_lval.cc,v $
+ * Revision 1.23  2002/11/21 23:27:51  steve
+ *  Precalculate indices to l-value arrays.
+ *
+ * Revision 1.22  2002/11/21 18:15:40  steve
+ *  Fix const test of msb in assignment l-values.
+ *
+ * Revision 1.21  2002/11/02 01:10:49  steve
+ *  Detect memories without work index in l-value.
+ *
+ * Revision 1.20  2002/08/12 01:34:58  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.19  2002/06/04 05:38:44  steve
+ *  Add support for memory words in l-value of
+ *  blocking assignments, and remove the special
+ *  NetAssignMem class.
+ *
  * Revision 1.18  2002/03/09 04:02:26  steve
  *  Constant expressions are not l-values for task ports.
  *

elab_net.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2000 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2002 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: elab_net.cc,v 1.90 2002/05/23 03:08:51 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: elab_net.cc,v 1.103 2002/12/06 03:08:19 steve Exp $"
 #endif
 
 # include "config.h"
@@ -67,6 +67,8 @@ NetNet* PEBinary::elaborate_net(Design*des, NetScope*scope,
 	  case '|': // Bitwise OR
 	  case '&':
 	  case '^':
+	  case 'A': // Bitwise NAND (~&)
+	  case 'O': // Bitwise NOR (~|)
 	  case 'X': // Exclusing NOR
 	    return elaborate_net_bit_(des, scope, width, rise, fall, decay);
 	  case 'E': // === (case equals)
@@ -138,9 +140,9 @@ NetNet* PEBinary::elaborate_net(Design*des, NetScope*scope,
 	    osig = 0;
       }
 
-      if (NetTmp*tmp = dynamic_cast<NetTmp*>(lsig))
+      if (NetSubnet*tmp = dynamic_cast<NetSubnet*>(lsig))
 	    delete tmp;
-      if (NetTmp*tmp = dynamic_cast<NetTmp*>(rsig))
+      if (NetSubnet*tmp = dynamic_cast<NetSubnet*>(rsig))
 	    delete tmp;
 
       return osig;
@@ -340,6 +342,20 @@ NetNet* PEBinary::elaborate_net_bit_(Design*des, NetScope*scope,
 	    }
 	    break;
 
+	  case 'A': // NAND (~&)
+	    for (unsigned idx = 0 ;  idx < lsig->pin_count() ;  idx += 1) {
+		  NetLogic*gate = new NetLogic(scope, scope->local_hsymbol(),
+					       3, NetLogic::NAND);
+		  connect(gate->pin(1), lsig->pin(idx));
+		  connect(gate->pin(2), rsig->pin(idx));
+		  connect(gate->pin(0), osig->pin(idx));
+		  gate->rise_time(rise);
+		  gate->fall_time(fall);
+		  gate->decay_time(decay);
+		  des->add_node(gate);
+	    }
+	    break;
+
 	  case '|': // Bitwise OR
 	    for (unsigned idx = 0 ;  idx < lsig->pin_count() ;  idx += 1) {
 		  NetLogic*gate = new NetLogic(scope, scope->local_hsymbol(),
@@ -354,6 +370,20 @@ NetNet* PEBinary::elaborate_net_bit_(Design*des, NetScope*scope,
 	    }
 	    break;
 
+	  case 'O': // Bitwise NOR
+	    for (unsigned idx = 0 ;  idx < lsig->pin_count() ;  idx += 1) {
+		  NetLogic*gate = new NetLogic(scope, scope->local_hsymbol(),
+					       3, NetLogic::NOR);
+		  connect(gate->pin(1), lsig->pin(idx));
+		  connect(gate->pin(2), rsig->pin(idx));
+		  connect(gate->pin(0), osig->pin(idx));
+		  gate->rise_time(rise);
+		  gate->fall_time(fall);
+		  gate->decay_time(decay);
+		  des->add_node(gate);
+	    }
+	    break;
+
 	  default:
 	    assert(0);
       }
@@ -398,6 +428,7 @@ NetNet* PEBinary::elaborate_net_cmp_(Design*des, NetScope*scope,
 					verinum::V0);
 	    des->add_node(tmp);
 	    zero = new NetNet(scope, scope->local_hsymbol(), NetNet::WIRE);
+	    zero->local_flag(true);
 	    connect(tmp->pin(0), zero->pin(0));
       }
 
@@ -744,7 +775,9 @@ NetNet* PEBinary::elaborate_net_log_(Design*des, NetScope*scope,
 
 	      /* The reduced logical value is a new nexus, create a
 		 temporary signal to represent it. */
-	    NetNet*tmp = new NetTmp(scope, scope->local_hsymbol());
+	    NetNet*tmp = new NetNet(scope, scope->local_hsymbol(),
+				    NetNet::IMPLICIT, 1);
+	    tmp->local_flag(true);
 	    connect(gate->pin(1), tmp->pin(0));
 
 	    des->add_node(gate_t);
@@ -763,7 +796,9 @@ NetNet* PEBinary::elaborate_net_log_(Design*des, NetScope*scope,
 
 	      /* The reduced logical value is a new nexus, create a
 		 temporary signal to represent it. */
-	    NetNet*tmp = new NetTmp(scope, scope->local_hsymbol());
+	    NetNet*tmp = new NetNet(scope, scope->local_hsymbol(),
+				    NetNet::IMPLICIT, 1);
+	    tmp->local_flag(true);
 	    connect(gate->pin(2), tmp->pin(0));
 
 	    des->add_node(gate_t);
@@ -944,7 +979,9 @@ NetNet* PEBinary::elaborate_net_shift_(Design*des, NetScope*scope,
       if (lsig->pin_count() < lwidth) {
 	    NetConst*zero = new NetConst(scope, scope->local_hsymbol(),
 					 verinum::V0);
-	    NetTmp*tmp = new NetTmp(scope, scope->local_hsymbol());
+	    NetNet*tmp = new NetNet(scope, scope->local_hsymbol(),
+				    NetNet::IMPLICIT, 1);
+	    tmp->local_flag(true);
 	    des->add_node(zero);
 	    connect(zero->pin(0), tmp->pin(0));
 	    for (unsigned idx = lsig->pin_count() ; idx < lwidth ;  idx += 1)
@@ -957,7 +994,9 @@ NetNet* PEBinary::elaborate_net_shift_(Design*des, NetScope*scope,
 	    connect(rsig->pin(idx), gate->pin_Distance(idx));
 
       if (op_ == 'r') {
-	    NetTmp*tmp = new NetTmp(scope, scope->local_hsymbol());
+	    NetNet*tmp = new NetNet(scope, scope->local_hsymbol(),
+				    NetNet::IMPLICIT, 1);
+	    tmp->local_flag(true);
 	    NetConst*dir = new NetConst(scope, scope->local_hsymbol(),
 					verinum::V1);
 	    connect(dir->pin(0), gate->pin_Direction());
@@ -1164,7 +1203,7 @@ NetNet* PEConcat::elaborate_net(Design*des, NetScope*scope,
 }
 
 /*
- * This provate method handles the special case that we have a
+ * This private method handles the special case that we have a
  * non-constant bit-select of an identifier. We already know that the
  * signal that is represented is "sig".
  */
@@ -1179,12 +1218,25 @@ NetNet* PEIdent::elaborate_net_bitmux_(Design*des, NetScope*scope,
 	/* Elaborate the selector. */
       NetNet*sel = msb_->elaborate_net(des, scope, 0, 0, 0, 0);
 
+      unsigned sig_width = sig->pin_count();
       NetMux*mux = new NetMux(scope, scope->local_hsymbol(), 1,
-			      sig->pin_count(),
-			      sel->pin_count());
+			      sig_width, sel->pin_count());
 
-      for (unsigned idx = 0 ;  idx < sig->pin_count() ;  idx += 1)
-	    connect(mux->pin_Data(0, idx), sig->pin(idx));
+	/* Connect the signal bits to the mux. Account for the
+	   direction of the numbering (lsb to msb vs. msb to lsb) by
+	   swapping the connection order. */
+
+      if (sig->msb() > sig->lsb()) {
+
+	    sel = add_to_net(des, sel, -sig->lsb());
+	    for (unsigned idx = 0 ;  idx < sig_width ;  idx += 1)
+		  connect(mux->pin_Data(0, idx), sig->pin(idx));
+      } else {
+
+	    sel = add_to_net(des, sel, -sig->msb());
+	    for (unsigned idx = 0 ;  idx < sig_width ;  idx += 1)
+		  connect(mux->pin_Data(0, idx), sig->pin(sig_width-idx-1));
+      }
 
       for (unsigned idx = 0 ;  idx < sel->pin_count() ;  idx += 1)
 	    connect(mux->pin_Sel(idx), sel->pin(idx));
@@ -1298,15 +1350,13 @@ NetNet* PEIdent::elaborate_net(Design*des, NetScope*scope,
 		  lidx = tmp;
 	    }
 
-	    NetNet*tmp = new NetNet(scope, scope->local_hsymbol(),
-				    sig->type(), midx-lidx+1);
-	    tmp->local_flag(true);
+	    unsigned part_count = midx-lidx+1;
 
 	      /* Check that the bit or part select of the signal is
 		 within the range of the part. The lidx is the
 		 normalized index of the LSB, so that plus the desired
 		 width must be <= the width of the references signal. */
-	    if ((lidx + tmp->pin_count()) > sig->pin_count()) {
+	    if ((lidx + part_count) > sig->pin_count()) {
 		  cerr << get_line() << ": error: bit/part select ["
 		       << mval->as_long() << ":" << lval->as_long()
 		       << "] out of range for " << sig->name() << endl;
@@ -1314,8 +1364,7 @@ NetNet* PEIdent::elaborate_net(Design*des, NetScope*scope,
 		  return sig;
 	    }
 
-	    for (unsigned idx = lidx ;  idx <= midx ;  idx += 1)
-		  connect(tmp->pin(idx-lidx), sig->pin(idx));
+	    NetSubnet*tmp = new NetSubnet(sig, lidx, part_count);
 
 	    sig = tmp;
 
@@ -1336,14 +1385,7 @@ NetNet* PEIdent::elaborate_net(Design*des, NetScope*scope,
 		  idx = 0;
 	    }
 
-	      /* This is a bit select, create a compatible NetNet with
-		 a single bit that links to the selected bit of the
-		 expression. */
-	    NetNet*tmp = new NetNet(scope, scope->local_hsymbol(),
-				    sig->type(), 1);
-	    tmp->local_flag(true);
-
-	    connect(tmp->pin(0), sig->pin(idx));
+	    NetSubnet*tmp = new NetSubnet(sig, idx, 1);
 	    sig = tmp;
       }
 
@@ -1373,15 +1415,19 @@ NetNet* PEIdent::elaborate_net_ram_(Design*des, NetScope*scope,
       if (adr == 0)
 	    return 0;
 
+	// Memory names are only the base names. Since NetObj names
+	// are still fullnames, and we are deriving such names from
+	// the memory name, make a fullname here.
+      string hname = scope->name() + "." + mem->name();
 
-      NetRamDq*ram = new NetRamDq(scope, des->local_symbol(mem->name()),
+      NetRamDq*ram = new NetRamDq(scope, des->local_symbol(hname),
 				  mem, adr->pin_count());
       des->add_node(ram);
 
       for (unsigned idx = 0 ;  idx < adr->pin_count() ;  idx += 1)
 	    connect(ram->pin_Address(idx), adr->pin(idx));
 
-      NetNet*osig = new NetNet(scope, des->local_symbol(mem->name()),
+      NetNet*osig = new NetNet(scope, des->local_symbol(hname),
 			       NetNet::IMPLICIT, ram->width());
       osig->local_flag(true);
 
@@ -1391,11 +1437,70 @@ NetNet* PEIdent::elaborate_net_ram_(Design*des, NetScope*scope,
       return osig;
 }
 
+/*
+ * The concatenation is also OK an an l-value. This method elaborates
+ * it as a structural l-value.
+ */
+NetNet* PEConcat::elaborate_lnet(Design*des, NetScope*scope,
+				 bool implicit_net_ok) const
+{
+      assert(scope);
+
+      svector<NetNet*>nets (parms_.count());
+      unsigned pins = 0;
+      unsigned errors = 0;
+
+      if (repeat_) {
+	    cerr << get_line() << ": sorry: I do not know how to"
+		  " elaborate repeat concatenation nets." << endl;
+	    return 0;
+      }
+
+	/* Elaborate the operands of the concatenation. */
+      for (unsigned idx = 0 ;  idx < nets.count() ;  idx += 1) {
+	    nets[idx] = parms_[idx]->elaborate_lnet(des, scope,
+						    implicit_net_ok);
+	    if (nets[idx] == 0)
+		  errors += 1;
+	    else
+		  pins += nets[idx]->pin_count();
+      }
+
+	/* If any of the sub expressions failed to elaborate, then
+	   delete all those that did and abort myself. */
+      if (errors) {
+	    for (unsigned idx = 0 ;  idx < nets.count() ;  idx += 1) {
+		  if (nets[idx]) delete nets[idx];
+	    }
+	    des->errors += 1;
+	    return 0;
+      }
+
+	/* Make the temporary signal that connects to all the
+	   operands, and connect it up. Scan the operands of the
+	   concat operator from least significant to most significant,
+	   which is opposite from how they are given in the list. */
+      NetNet*osig = new NetNet(scope, des->local_symbol(scope->name()),
+			       NetNet::IMPLICIT, pins);
+      pins = 0;
+      for (unsigned idx = nets.count() ;  idx > 0 ;  idx -= 1) {
+	    NetNet*cur = nets[idx-1];
+	    for (unsigned pin = 0 ;  pin < cur->pin_count() ;  pin += 1) {
+		  connect(osig->pin(pins), cur->pin(pin));
+		  pins += 1;
+	    }
+      }
+
+      osig->local_flag(true);
+      return osig;
+}
+
 /*
  * Identifiers in continuous assignment l-values are limited to wires
  * and that ilk. Detect registers and memories here and report errors.
  */
-NetNet* PEIdent::elaborate_lnet(Design*des, NetScope*scope) const
+NetNet* PEIdent::elaborate_lnet(Design*des, NetScope*scope,
+				bool implicit_net_ok) const
 {
       string path = scope->name();
 
@@ -1409,29 +1514,41 @@ NetNet* PEIdent::elaborate_lnet(Design*des, NetScope*scope) const
 		  return 0;
 	    }
 
-	    cerr << get_line() << ": error: Net " << path_
-		 << " is not defined in this context." << endl;
-	    cerr << get_line() << ":      : Do you mean this? wire "
-		 << path_ << " = <expr>;" << endl;
-	    return 0;
+	    if (implicit_net_ok && !error_implicit) {
+
+		  sig = new NetNet(scope, scope->name()+"."+path_.peek_name(0),
+				   NetNet::IMPLICIT, 1);
+
+		  if (warn_implicit) {
+			cerr << get_line() << ": warning: implicit "
+			      "definition of wire " << scope->name()
+			     << "." << path_.peek_name(0) << "." << endl;
+		  }
+
+	    } else {
+		  cerr << get_line() << ": error: Net " << path_
+		       << " is not defined in this context." << endl;
+		  cerr << get_line() << ":      : Do you mean this? wire "
+		       << path_ << " = <expr>;" << endl;
+		  return 0;
+	    }
       }
 
       assert(sig);
 
 	/* Don't allow registers as assign l-values. */
       if (sig->type() == NetNet::REG) {
-	    cerr << get_line() << ": error: registers (" << sig->name()
-		 << ") cannot be l-values in continuous"
+	    cerr << get_line() << ": error: reg " << sig->name()
+		 << "; cannot be an L-value in continuous"
 		 << " assignments." << endl;
 	    return 0;
       }
 
       if (sig->port_type() == NetNet::PINPUT) {
-	    cerr << get_line() << ": warning: assign l-value ``"
-		 << sig->name() << "'' is also an input to "
-		 << sig->scope()->name() << "." << endl;
-	    cerr << sig->get_line() << ": warning: input ``"
-		 << sig->name() << "'' is coerced to inout." << endl;
+	    cerr << get_line() << ": warning: L-value ``"
+		 << sig->name() << "'' is also an input port." << endl;
+	    cerr << sig->get_line() << ": warning: input "
+		 << sig->name() << "; is coerced to inout." << endl;
 	    sig->port_type(NetNet::PINOUT);
       }
 
@@ -1447,24 +1564,21 @@ NetNet* PEIdent::elaborate_lnet(Design*des, NetScope*scope) const
 	    unsigned lidx = sig->sb_to_idx(lval->as_long());
 
 	    if (midx >= lidx) {
-		  NetTmp*tmp = new NetTmp(scope, scope->local_hsymbol(),
-					  midx-lidx+1);
-		  if (tmp->pin_count() > sig->pin_count()) {
+		  unsigned subnet_wid = midx-lidx+1;
+		  if (subnet_wid > sig->pin_count()) {
 			cerr << get_line() << ": bit select out of "
 			     << "range for " << sig->name() << endl;
 			return sig;
 		  }
 
-		  for (unsigned idx = lidx ;  idx <= midx ;  idx += 1)
-			connect(tmp->pin(idx-lidx), sig->pin(idx));
+		  NetSubnet*tmp = new NetSubnet(sig, lidx, subnet_wid);
 
 		  sig = tmp;
 
 	    } else {
-		  NetTmp*tmp = new NetTmp(scope, scope->local_hsymbol(),
-					  lidx-midx+1);
+		  unsigned subnet_wid = midx-lidx+1;
 
-		  if (tmp->pin_count() > sig->pin_count()) {
+		  if (subnet_wid > sig->pin_count()) {
 			cerr << get_line() << ": error: "
 			     << "part select out of range for "
 			     << sig->name() << "." << endl;
@@ -1472,9 +1586,7 @@ NetNet* PEIdent::elaborate_lnet(Design*des, NetScope*scope) const
 			return sig;
 		  }
 
-		  assert(tmp->pin_count() <= sig->pin_count());
-		  for (unsigned idx = lidx ;  idx >= midx ;  idx -= 1)
-			connect(tmp->pin(idx-midx), sig->pin(idx));
+		  NetSubnet*tmp = new NetSubnet(sig, lidx, subnet_wid);
 
 		  sig = tmp;
 	    }
@@ -1496,8 +1608,8 @@ NetNet* PEIdent::elaborate_lnet(Design*des, NetScope*scope) const
 		  des->errors += 1;
 		  idx = 0;
 	    }
-	    NetTmp*tmp = new NetTmp(scope, scope->local_hsymbol(), 1);
-	    connect(tmp->pin(0), sig->pin(idx));
+
+	    NetSubnet*tmp = new NetSubnet(sig, idx, 1);
 	    sig = tmp;
       }
 
@@ -1562,24 +1674,26 @@ NetNet* PEIdent::elaborate_port(Design*des, NetScope*scope) const
 	    unsigned lidx = sig->sb_to_idx(lval->as_long());
 
 	    if (midx >= lidx) {
-		  NetTmp*tmp = new NetTmp(scope, scope->local_hsymbol(),
-					  midx-lidx+1);
-		  if (tmp->pin_count() > sig->pin_count()) {
+		  unsigned part_count = midx-lidx+1;
+		  if (part_count > sig->pin_count()) {
 			cerr << get_line() << ": bit select out of "
 			     << "range for " << sig->name() << endl;
 			return sig;
 		  }
 
+		  NetSubnet*tmp = new NetSubnet(sig, lidx, part_count);
 		  for (unsigned idx = lidx ;  idx <= midx ;  idx += 1)
 			connect(tmp->pin(idx-lidx), sig->pin(idx));
 
 		  sig = tmp;
 
 	    } else {
-		  NetTmp*tmp = new NetTmp(scope, scope->local_hsymbol(),
-					  lidx-midx+1);
-		  assert(tmp->pin_count() <= sig->pin_count());
-		  for (unsigned idx = lidx ;  idx >= midx ;  idx -= 1)
+		    /* XXXX Signals reversed?? */
+		  unsigned part_count = lidx-midx+1;
+		  assert(part_count <= sig->pin_count());
+
+		  NetSubnet*tmp = new NetSubnet(sig, midx, part_count);
+		  for (unsigned idx = midx ;  idx >= lidx ;  idx -= 1)
 			connect(tmp->pin(idx-midx), sig->pin(idx));
 
 		  sig = tmp;
@@ -1602,7 +1716,7 @@ NetNet* PEIdent::elaborate_port(Design*des, NetScope*scope) const
 		  des->errors += 1;
 		  idx = 0;
 	    }
-	    NetTmp*tmp = new NetTmp(scope, scope->local_hsymbol(), 1);
+	    NetSubnet*tmp = new NetSubnet(sig, idx, 1);
 	    connect(tmp->pin(0), sig->pin(idx));
 	    sig = tmp;
       }
@@ -1817,7 +1931,8 @@ NetNet* PETernary::elaborate_net(Design*des, NetScope*scope,
 	    for (unsigned idx = 0;  idx < expr_sig->pin_count(); idx += 1)
 		  connect(log->pin(idx+1), expr_sig->pin(idx));
 
-	    NetNet*tmp = new NetTmp(scope, scope->local_hsymbol());
+	    NetNet*tmp = new NetNet(scope, scope->local_hsymbol(),
+				    NetNet::IMPLICIT, 1);
 	    tmp->local_flag(true);
 	    connect(tmp->pin(0), log->pin(0));
 	    des->add_node(log);
@@ -1858,12 +1973,39 @@ NetNet* PETernary::elaborate_net(Design*des, NetScope*scope,
       NetMux*mux = new NetMux(scope, scope->local_hsymbol(), dwidth, 2, 1);
       connect(mux->pin_Sel(0), expr_sig->pin(0));
 
+	/* Connect the data inputs. */
       for (unsigned idx = 0 ;  idx < dwidth ;  idx += 1) {
-	    connect(mux->pin_Result(idx), sig->pin(idx));
 	    connect(mux->pin_Data(idx,0), fal_sig->pin(idx));
 	    connect(mux->pin_Data(idx,1), tru_sig->pin(idx));
       }
 
+	/* If there are non-zero output delays, then create bufz
+	   devices to carry the propagation delays. Otherwise, just
+	   connect the result to the output. */
+      if (rise || fall || decay) {
+	    NetNet*tmp = new NetNet(scope, scope->local_hsymbol(),
+				    NetNet::WIRE, dwidth);
+	    for (unsigned idx = 0 ;  idx < dwidth ;  idx += 1) {
+
+		  NetBUFZ*tmpz = new NetBUFZ(scope, scope->local_hsymbol());
+		  tmpz->rise_time(rise);
+		  tmpz->fall_time(fall);
+		  tmpz->decay_time(decay);
+		  tmpz->pin(0).drive0(drive0);
+		  tmpz->pin(0).drive1(drive1);
+
+		  connect(mux->pin_Result(idx), tmp->pin(idx));
+		  connect(tmp->pin(idx), tmpz->pin(1));
+		  connect(sig->pin(idx), tmpz->pin(0));
+
+		  des->add_node(tmpz);
+	    }
+
+      } else {
+	    for (unsigned idx = 0 ;  idx < dwidth ;  idx += 1) {
+		  connect(mux->pin_Result(idx), sig->pin(idx));
+	    }
+      }
 
 	/* If the MUX device result is too narrow to fill out the
 	   desired result, pad with zeros by creating a NetConst device. */
@@ -1911,11 +2053,19 @@ NetNet* PEUnary::elaborate_net(Design*des, NetScope*scope,
 	    if (val == 0)
 		  break;
 
+	    if (width == 0)
+		  width = val->len();
+
+	    assert(width > 0);
 	    sig = new NetNet(scope, scope->local_hsymbol(),
 			     NetNet::WIRE, width);
 	    sig->local_flag(true);
 
-	    verinum tmp(v_not(*val) + verinum(1UL, width), width);
+	      /* Take the 2s complement by taking the 1s complement
+		 and adding 1. */
+	    verinum tmp (v_not(*val));
+	    verinum one (1UL, width);
+	    tmp = tmp + one;
 	    NetConst*con = new NetConst(scope, scope->local_hsymbol(), tmp);
 	    for (unsigned idx = 0 ;  idx < width ;  idx += 1)
 		  connect(sig->pin(idx), con->pin(idx));
@@ -2042,9 +2192,12 @@ NetNet* PEUnary::elaborate_net(Design*des, NetScope*scope,
 
 	  case '-': // Unary 2's complement.
 	    sig = new NetNet(scope, scope->local_hsymbol(),
-			     NetNet::WIRE, sub_sig->pin_count());
+			     NetNet::WIRE, owidth);
 	    sig->local_flag(true);
 
+	    if (sub_sig->pin_count() < owidth)
+		  sub_sig = pad_to_width(des, sub_sig, owidth);
+
 	    switch (sub_sig->pin_count()) {
 		case 0:
 		  assert(0);
@@ -2083,10 +2236,33 @@ NetNet* PEUnary::elaborate_net(Design*des, NetScope*scope,
 		  break;
 
 		default:
-		  cerr << get_line() << ": internal error: Wide unary " 
-		       << "minus not supported here." << endl;
-		  des->errors += 1;
-		  sig = 0;
+		  NetAddSub*sub = new NetAddSub(scope, scope->local_hsymbol(),
+						sig->pin_count());
+		  sub->attribute("LPM_Direction", verinum("SUB"));
+
+		  des->add_node(sub);
+
+		  for (unsigned idx = 0 ;  idx < sig->pin_count();  idx += 1)
+			connect(sig->pin(idx), sub->pin_Result(idx));
+
+		  for (unsigned idx = 0; idx < sub_sig->pin_count(); idx += 1)
+			connect(sub_sig->pin(idx), sub->pin_DataB(idx));
+
+		  verinum tmp_num (verinum::V0, sub->width(), true);
+		  NetConst*tmp_con = new NetConst(scope,
+						  scope->local_hsymbol(),
+						  tmp_num);
+		  des->add_node(tmp_con);
+
+		  NetNet*tmp_sig = new NetNet(scope, scope->local_hsymbol(),
+					      NetNet::WIRE,
+					      sub_sig->pin_count());
+		  tmp_sig->local_flag(true);
+
+		  for (unsigned idx = 0; idx < sig->pin_count(); idx += 1) {
+			connect(tmp_sig->pin(idx), sub->pin_DataA(idx));
+			connect(tmp_sig->pin(idx), tmp_con->pin(idx));
+		  }
 		  break;
 	    }
 	    break;
@@ -2102,6 +2278,45 @@ NetNet* PEUnary::elaborate_net(Design*des, NetScope*scope,
 
 /*
  * $Log: elab_net.cc,v $
+ * Revision 1.103  2002/12/06 03:08:19  steve
+ *  Reword some error messages for clarity.
+ *
+ * Revision 1.102  2002/11/09 19:20:48  steve
+ *  Port expressions for output ports are lnets, not nets.
+ *
+ * Revision 1.101  2002/09/18 04:29:55  steve
+ *  Add support for binary NOR operator.
+ *
+ * Revision 1.100  2002/09/12 15:49:43  steve
+ *  Add support for binary nand operator.
+ *
+ * Revision 1.99  2002/09/08 01:37:13  steve
+ *  Fix padding of operand of unary minus.
+ *
+ * Revision 1.98  2002/08/31 03:48:50  steve
+ *  Fix reverse bit ordered bit select in continuous assignment.
+ *
+ * Revision 1.97  2002/08/21 02:28:03  steve
+ *  Carry mux output delays.
+ *
+ * Revision 1.96  2002/08/14 03:57:27  steve
+ *  Constants can self-size themselves in unsized contexts.
+ *
+ * Revision 1.95  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.94  2002/08/05 04:18:45  steve
+ *  Store only the base name of memories.
+ *
+ * Revision 1.93  2002/07/05 21:26:17  steve
+ *  Avoid emitting to vvp local net symbols.
+ *
+ * Revision 1.92  2002/06/22 04:22:40  steve
+ *  Wide unary minus in continuous assignments.
+ *
+ * Revision 1.91  2002/06/19 04:20:03  steve
+ *  Remove NetTmp and add NetSubnet class.
+ *
  * Revision 1.90  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute
@@ -2127,38 +2342,5 @@ NetNet* PEUnary::elaborate_net(Design*des, NetScope*scope,
  *
  * Revision 1.84  2001/12/31 04:23:59  steve
  *  Elaborate multiply nets with constant operands ad NetConst.
- *
- * Revision 1.83  2001/12/30 21:32:03  steve
- *  Support elaborate_net for PEString objects.
- *
- * Revision 1.82  2001/12/03 04:47:14  steve
- *  Parser and pform use hierarchical names as hname_t
- *  objects instead of encoded strings.
- *
- * Revision 1.81  2001/11/10 02:08:49  steve
- *  Coerse input to inout when assigned to.
- *
- * Revision 1.80  2001/11/08 05:15:50  steve
- *  Remove string paths from PExpr elaboration.
- *
- * Revision 1.79  2001/11/07 04:26:46  steve
- *  elaborate_lnet uses scope instead of string path.
- *
- * Revision 1.78  2001/11/07 04:01:59  steve
- *  eval_const uses scope instead of a string path.
- *
- * Revision 1.77  2001/10/28 01:14:53  steve
- *  NetObj constructor finally requires a scope.
- *
- * Revision 1.76  2001/10/16 02:19:26  steve
- *  Support IVL_LPM_DIVIDE for structural divide.
- *
- * Revision 1.75  2001/09/14 04:20:49  steve
- *  dead code.
- *
- * Revision 1.74  2001/09/14 04:16:52  steve
- *  Elaborate == to NetCompare instead of XNOR and AND
- *  gates. This allows code generators to generate
- *  better code in certain cases.
  */
 

elab_pexpr.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: elab_pexpr.cc,v 1.15 2002/05/06 02:30:27 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: elab_pexpr.cc,v 1.18 2002/12/05 02:14:33 steve Exp $"
 #endif
 
 # include "config.h"
@@ -108,11 +108,6 @@ NetEConcat* PEConcat::elaborate_pexpr(Design*des, NetScope*scope) const
 		       << *ex << endl;
 		  des->errors += 1;
 
-	    } else if (ex->expr_width() == 0) {
-		  cerr << ex->get_line() << ": internal error: "
-		       << "Operand of concatenation has no width: "
-		       << *ex << endl;
-		  des->errors += 1;
 	    }
 
 	    tmp->set(idx, ex);
@@ -150,15 +145,26 @@ NetExpr*PEIdent::elaborate_pexpr(Design*des, NetScope*scope) const
 	    return 0;
       }
 
-      if (msb_ || lsb_ || idx_) {
-	    cerr << get_line() << ": error: Cannot bit/part select "
-		  "bits of parameters." << endl;
-	    des->errors += 1;
-      }
-
       NetExpr*res = new NetEParam(des, pscope, hname_t(name));
       assert(res);
       delete name;
+
+      assert(idx_ == 0);
+      if (msb_ && lsb_) {
+	    cerr << get_line() << ": sorry: Cannot part select "
+		  "bits of parameters." << endl;
+	    des->errors += 1;
+
+      } else if (msb_) {
+
+	      /* We have here a bit select. Insert a NetESelect node
+		 to handle it. */
+	    NetExpr*tmp = msb_->elaborate_pexpr(des, scope);
+	    if (tmp != 0) {
+		  res = new NetESelect(res, tmp, 1);
+	    }
+      }
+
       return res;
 }
 
@@ -222,6 +228,15 @@ NetExpr*PEUnary::elaborate_pexpr (Design*des, NetScope*scope) const
 
 /*
  * $Log: elab_pexpr.cc,v $
+ * Revision 1.18  2002/12/05 02:14:33  steve
+ *  Support bit select in constant expressions.
+ *
+ * Revision 1.17  2002/11/09 01:40:19  steve
+ *  Postpone parameter width check to evaluation.
+ *
+ * Revision 1.16  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.15  2002/05/06 02:30:27  steve
  *  Allow parameters in concatenation of widths are defined.
  *

elab_scope.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: elab_scope.cc,v 1.13 2001/12/30 04:47:57 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: elab_scope.cc,v 1.17 2002/10/19 22:59:49 steve Exp $"
 #endif
 
 # include "config.h"
@@ -54,7 +54,7 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
 	// the pform and just place a NetEParam placeholder in the
 	// place of the elaborated expression.
 
-      typedef map<string,PExpr*>::const_iterator mparm_it_t;
+      typedef map<string,param_expr_t>::const_iterator mparm_it_t;
       typedef map<hname_t,PExpr*>::const_iterator hparm_it_t;
 
 
@@ -64,13 +64,21 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
       for (mparm_it_t cur = parameters.begin()
 		 ; cur != parameters.end() ;  cur ++) {
 
-	    scope->set_parameter((*cur).first, new NetEParam);
+	    NetEParam*tmp = new NetEParam;
+	    if ((*cur).second.msb)
+		  tmp->cast_signed( (*cur).second.signed_flag );
+
+	    scope->set_parameter((*cur).first, tmp, 0, 0, false);
       }
 
       for (mparm_it_t cur = localparams.begin()
 		 ; cur != localparams.end() ;  cur ++) {
 
-	    scope->set_parameter((*cur).first, new NetEParam);
+	    NetEParam*tmp = new NetEParam;
+	    if ((*cur).second.msb)
+		  tmp->cast_signed( (*cur).second.signed_flag );
+
+	    scope->set_parameter((*cur).first, tmp, 0, 0, false);
       }
 
 
@@ -82,11 +90,29 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
       for (mparm_it_t cur = parameters.begin()
 		 ; cur != parameters.end() ;  cur ++) {
 
-	    PExpr*ex = (*cur).second;
+	    PExpr*ex = (*cur).second.expr;
 	    assert(ex);
 
 	    NetExpr*val = ex->elaborate_pexpr(des, scope);
-	    val = scope->set_parameter((*cur).first, val);
+	    NetExpr*msb = 0;
+	    NetExpr*lsb = 0;
+	    bool signed_flag = false;
+
+	      /* If the parameter declaration includes msb and lsb,
+		 then use them to calculate a width for the
+		 result. Then make sure the constant expression of the
+		 parameter value is coerced to have the correct
+		 and defined width. */
+	    if ((*cur).second.msb) {
+		  msb = (*cur).second.msb ->elaborate_pexpr(des, scope);
+		  assert(msb);
+		  lsb = (*cur).second.lsb ->elaborate_pexpr(des, scope);
+		  signed_flag = (*cur).second.signed_flag;
+	    }
+
+	    val->cast_signed(signed_flag);
+	    val = scope->set_parameter((*cur).first, val,
+				       msb, lsb, signed_flag);
 	    assert(val);
 	    delete val;
       }
@@ -94,11 +120,11 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
       for (mparm_it_t cur = localparams.begin()
 		 ; cur != localparams.end() ;  cur ++) {
 
-	    PExpr*ex = (*cur).second;
+	    PExpr*ex = (*cur).second.expr;
 	    assert(ex);
 
 	    NetExpr*val = ex->elaborate_pexpr(des, scope);
-	    val = scope->set_parameter((*cur).first, val);
+	    val = scope->set_parameter((*cur).first, val, 0, 0, false);
 	    assert(val);
 	    delete val;
       }
@@ -306,9 +332,12 @@ void PGModule::elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const
 
 	    PExpr*tmp = (*cur).second;
 	    NetExpr*val = tmp->elaborate_pexpr(des, sc);
-	    val = my_scope->set_parameter((*cur).first, val);
-	    assert(val);
-	    delete val;
+	    bool flag = my_scope->replace_parameter((*cur).first, val);
+	    if (! flag) {
+		  cerr << val->get_line() << ": warning: parameter "
+		       << (*cur).first << " not found in "
+		       << sc->name() << "." << endl;
+	    }
       }
 }
 
@@ -467,6 +496,19 @@ void PWhile::elaborate_scope(Design*des, NetScope*scope) const
 
 /*
  * $Log: elab_scope.cc,v $
+ * Revision 1.17  2002/10/19 22:59:49  steve
+ *  Redo the parameter vector support to allow
+ *  parameter names in range expressions.
+ *
+ * Revision 1.16  2002/09/01 03:01:48  steve
+ *  Properly cast signedness of parameters with ranges.
+ *
+ * Revision 1.15  2002/08/19 02:39:16  steve
+ *  Support parameters with defined ranges.
+ *
+ * Revision 1.14  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.13  2001/12/30 04:47:57  steve
  *  Properly handle empty target in positionla parameter override.
  *

elab_sig.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: elab_sig.cc,v 1.22 2002/05/23 03:08:51 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: elab_sig.cc,v 1.25 2002/08/12 01:34:59 steve Exp $"
 #endif
 
 # include "config.h"
@@ -498,8 +498,7 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
 	    assert(lval);
 	    assert(rval);
 
-	    string name = scope->name();
-	    name = name + "." + hname_.peek_tail_name();
+	    string name = hname_.peek_tail_name();
 
 	    long lnum = lval->as_long();
 	    long rnum = rval->as_long();
@@ -517,6 +516,7 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
 	    sig->set_line(*this);
 	    sig->port_type(port_type_);
 	    sig->set_signed(get_signed());
+	    sig->set_isint(get_isint());
 
 	    for (unsigned idx = 0 ;  idx < nattrib ;  idx += 1)
 		  sig->attribute(attrib_list[idx].key, attrib_list[idx].val);
@@ -525,6 +525,15 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
 
 /*
  * $Log: elab_sig.cc,v $
+ * Revision 1.25  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.24  2002/08/05 04:18:45  steve
+ *  Store only the base name of memories.
+ *
+ * Revision 1.23  2002/06/21 04:59:35  steve
+ *  Carry integerness throughout the compilation.
+ *
  * Revision 1.22  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute

elaborate.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1998-2002 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: elaborate.cc,v 1.251 2002/05/27 00:08:45 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: elaborate.cc,v 1.266 2002/12/05 04:15:14 steve Exp $"
 #endif
 
 # include "config.h"
@@ -122,7 +122,44 @@ void PGAssign::elaborate(Design*des, NetScope*scope) const
 	    if (rid->pin_count() < cnt)
 		  cnt = rid->pin_count();
 
-	    if ((rid->type() == lval->type()) && (rise_time == 0)) {
+	    bool need_driver_flag = false;
+
+	      /* If the device is linked to itself, a driver is
+		 needed. Should I print a warning here? */
+	    for (unsigned idx = 0 ;  idx < cnt ;  idx += 1) {
+		  if (lval->pin(idx) .is_linked (rid->pin(idx))) {
+			need_driver_flag = true;
+			break;
+		  }
+	    }
+
+	      /* If the nets are different type (i.e. reg vs tri) then
+		 a driver is needed. */
+	    if (rid->type() != lval->type())
+		  need_driver_flag = true;
+
+	      /* If there is a delay, then I need a driver to carry
+		 it. */
+	    if (rise_time || fall_time || decay_time)
+		  need_driver_flag = true;
+
+	      /* If there is a strength to be carried, then I need a
+		 driver to carry that strength. */
+	    for (unsigned idx = 0 ;  idx < cnt ;  idx += 1) {
+		  if (rid->pin(idx).drive0() != drive0) {
+			need_driver_flag = true;
+			break;
+		  }
+		  if (rid->pin(idx).drive1() != drive1) {
+			need_driver_flag = true;
+			break;
+		  }
+	    }
+
+	    if (! need_driver_flag) {
+		    /* Don't need a driver, presumably because the
+		       r-value already has the needed drivers. Just
+		       hook things up. */
 		  unsigned idx;
 		  for (idx = 0 ;  idx < cnt; idx += 1)
 			connect(lval->pin(idx), rid->pin(idx));
@@ -138,6 +175,8 @@ void PGAssign::elaborate(Design*des, NetScope*scope) const
 		  }
 
 	    } else {
+		    /* Do need a driver. Use BUFZ objects to carry the
+		       strength and delays. */
 		  unsigned idx;
 		  for (idx = 0 ; idx < cnt ;  idx += 1) {
 			NetBUFZ*dev = new NetBUFZ(scope,
@@ -409,7 +448,7 @@ void PGBuiltin::elaborate(Design*des, NetScope*scope) const
 		  des->errors += 1;
 	    }
 
-	    if (NetTmp*tmp = dynamic_cast<NetTmp*>(sig))
+	    if (NetSubnet*tmp = dynamic_cast<NetSubnet*>(sig))
 		  delete tmp;
       }
 }
@@ -573,41 +612,47 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
 	      // port. sig is the thing outside the module that
 	      // connects to the port.
 
-	    NetNet*sig = (*pins)[idx]->elaborate_net(des, scope,
-						     prts_pin_count,
-						     0, 0, 0);
-	    if (sig == 0) {
-		  cerr << "internal error: Expression too complicated "
-			"for elaboration." << endl;
-		  continue;
+	    NetNet*sig;
+	    if ((prts.count() >= 1)
+		&& (prts[0]->port_type() != NetNet::PINPUT)) {
+
+		  sig = (*pins)[idx]->elaborate_lnet(des, scope, true);
+		  if (sig == 0) {
+			cerr << (*pins)[idx]->get_line() << ": error: "
+			     << "Output port expression must support "
+			     << "continuous assignment." << endl;
+			des->errors += 1;
+			continue;
+		  }
+
+	    } else {
+		  sig = (*pins)[idx]->elaborate_net(des, scope,
+						    prts_pin_count,
+						    0, 0, 0);
+		  if (sig == 0) {
+			cerr << "internal error: Expression too complicated "
+			      "for elaboration." << endl;
+			continue;
+		  }
 	    }
 
 	    assert(sig);
 
-	      // Check that a reg is not passed as an output or inout
-	      // port of the module. sig is the elaborated signal in
-	      // the outside that is to be passed, and prts is a
-	      // concatenation of signals on the input that receive a
-	      // reg value.
-	    if ((sig->type() == NetNet::REG)
-		&& (prts.count() >= 1)
+#ifndef NDEBUG
+	    if ((prts.count() >= 1)
 		&& (prts[0]->port_type() != NetNet::PINPUT)) {
-		  cerr << get_line() << ": error: reg/variable "
-		       << sig->name() << " cannot connect to "
-		       << "output port " << (idx+1) << " of "
-		       << my_scope->name() << "." << endl;
-		  des->errors += 1;
-		  continue;
+		  assert(sig->type() != NetNet::REG);
 	    }
-
+#endif
 
 	      // Check that the parts have matching pin counts. If
 	      // not, they are different widths. Note that idx is 0
 	      // based, but users count parameter positions from 1.
 	    if (prts_pin_count != sig->pin_count()) {
-		  cerr << get_line() << ": warning: Port " << (idx+1) << " of "
+		  cerr << get_line() << ": warning: Port " << (idx+1)
+		       << " (" << rmod->ports[idx]->name << ") of "
 		       << type_ << " expects " << prts_pin_count <<
-			" pins, got " << sig->pin_count() << "." << endl;
+			" bits, got " << sig->pin_count() << "." << endl;
 
 		  if (prts_pin_count > sig->pin_count()) {
 			cerr << get_line() << ":        : Leaving "
@@ -617,7 +662,7 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
 		  } else {
 			cerr << get_line() << ":        : Leaving "
 			     << (sig->pin_count()-prts_pin_count)
-			     << " high bits of the parameter dangling."
+			     << " high bits of the expression dangling."
 			     << endl;
 		  }
 	    }
@@ -656,7 +701,7 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
 	    }
 
 
-	    if (NetTmp*tmp = dynamic_cast<NetTmp*>(sig))
+	    if (NetSubnet*tmp = dynamic_cast<NetSubnet*>(sig))
 		  delete tmp;
       }
 }
@@ -719,7 +764,7 @@ void PGModule::elaborate_udp_(Design*des, PUdp*udp, NetScope*scope) const
 	    connect(sig->pin(0), net->pin(idx));
 
 	      // Delete excess holding signal.
-	    if (NetTmp*tmp = dynamic_cast<NetTmp*>(sig))
+	    if (NetSubnet*tmp = dynamic_cast<NetSubnet*>(sig))
 		  delete tmp;
       }
       
@@ -798,61 +843,6 @@ void PGModule::elaborate_scope(Design*des, NetScope*sc) const
       des->errors += 1;
 }
 
-/*
- * The concatenation is also OK an an l-value. This method elaborates
- * it as a structural l-value.
- */
-NetNet* PEConcat::elaborate_lnet(Design*des, NetScope*scope) const
-{
-      assert(scope);
-
-      svector<NetNet*>nets (parms_.count());
-      unsigned pins = 0;
-      unsigned errors = 0;
-
-      if (repeat_) {
-	    cerr << get_line() << ": sorry: I do not know how to"
-		  " elaborate repeat concatenation nets." << endl;
-	    return 0;
-      }
-
-	/* Elaborate the operands of the concatenation. */
-      for (unsigned idx = 0 ;  idx < nets.count() ;  idx += 1) {
-	    nets[idx] = parms_[idx]->elaborate_lnet(des, scope);
-	    if (nets[idx] == 0)
-		  errors += 1;
-	    else
-		  pins += nets[idx]->pin_count();
-      }
-
-	/* If any of the sub expressions failed to elaborate, then
-	   delete all those that did and abort myself. */
-      if (errors) {
-	    for (unsigned idx = 0 ;  idx < nets.count() ;  idx += 1) {
-		  if (nets[idx]) delete nets[idx];
-	    }
-	    des->errors += 1;
-	    return 0;
-      }
-
-	/* Make the temporary signal that connects to all the
-	   operands, and connect it up. Scan the operands of the
-	   concat operator from least significant to most significant,
-	   which is opposite from how they are given in the list. */
-      NetNet*osig = new NetNet(scope, des->local_symbol(scope->name()),
-			       NetNet::IMPLICIT, pins);
-      pins = 0;
-      for (unsigned idx = nets.count() ;  idx > 0 ;  idx -= 1) {
-	    NetNet*cur = nets[idx-1];
-	    for (unsigned pin = 0 ;  pin < cur->pin_count() ;  pin += 1) {
-		  connect(osig->pin(pins), cur->pin(pin));
-		  pins += 1;
-	    }
-      }
-
-      osig->local_flag(true);
-      return osig;
-}
 
 NetProc* Statement::elaborate(Design*des, NetScope*) const
 {
@@ -863,41 +853,10 @@ NetProc* Statement::elaborate(Design*des, NetScope*) const
       return cur;
 }
 
-NetProc* PAssign::assign_to_memory_(NetMemory*mem, PExpr*ix,
-				    Design*des, NetScope*scope) const
-{
-      assert(scope);
-      NetExpr*rv = rval()->elaborate_expr(des, scope);
-      if (rv == 0)
-	    return 0;
-
-      assert(rv);
-
-      rv->set_width(mem->width());
-      if (ix == 0) {
-	    cerr << get_line() << ": internal error: No index in lval "
-		 << "of assignment to memory?" << endl;
-	    return 0;
-      }
-
-      assert(ix);
-      NetExpr*idx = ix->elaborate_expr(des, scope);
-      if (idx == 0) {
-	      /* Elaboration failed. The error message was already
-		 printed, so just give up here. */
-	    return 0;
-      }
-
-      if (rv->expr_width() < mem->width())
-	    rv = pad_to_width(rv, mem->width());
-
-      NetAssignMem*am = new NetAssignMem(mem, idx, rv);
-      am->set_line(*this);
-      return am;
-}
 
 NetAssign_* PAssign_::elaborate_lval(Design*des, NetScope*scope) const
 {
+      assert(lval_);
       return lval_->elaborate_lval(des, scope);
 }
 
@@ -956,22 +915,6 @@ NetProc* PAssign::elaborate(Design*des, NetScope*scope) const
 {
       assert(scope);
 
-	/* Catch the case where the lvalue is a reference to a memory
-	   item. These are handled differently. */
-      do {
-	    const PEIdent*id = dynamic_cast<const PEIdent*>(lval());
-	    if (id == 0) break;
-
-	    NetNet*net = des->find_signal(scope, id->path());
-	    if (net && (net->scope() == scope))
-		  break;
-
-	    if (NetMemory*mem = des->find_memory(scope, id->path()))
-		  return assign_to_memory_(mem, id->msb_, des, scope);
-
-      } while(0);
-
-
 	/* elaborate the lval. This detects any part selects and mux
 	   expressions that might exist. */
       NetAssign_*lv = elaborate_lval(des, scope);
@@ -1032,7 +975,7 @@ NetProc* PAssign::elaborate(Design*des, NetScope*scope) const
 	    rv->set_width(wid);
 	    rv = pad_to_width(rv, wid);
 
-	    if (! rv->set_width(wid)) {
+	    if (wid != rv->expr_width()) {
 		  cerr << get_line() << ": error: Unable to match "
 			"expression width of " << rv->expr_width() <<
 			" to l-value width of " << wid << "." << endl;
@@ -1097,36 +1040,6 @@ NetProc* PAssign::elaborate(Design*des, NetScope*scope) const
       return cur;
 }
 
-/*
- * I do not really know how to elaborate mem[x] <= expr, so this
- * method pretends it is a blocking assign and elaborates
- * that. However, I report an error so that the design isn't actually
- * executed by anyone.
- */
-NetProc* PAssignNB::assign_to_memory_(NetMemory*mem, PExpr*ix,
-				      Design*des, NetScope*scope) const
-{
-      assert(scope);
-
-	/* Elaborate the r-value expression, ... */
-      NetExpr*rv = rval()->elaborate_expr(des, scope);
-      if (rv == 0)
-	    return 0;
-
-      assert(rv);
-      rv->set_width(mem->width());
-
-	/* Elaborate the expression to calculate the index, ... */
-      NetExpr*idx = ix->elaborate_expr(des, scope);
-      assert(idx);
-
-	/* And connect them together in an assignment NetProc. */
-      NetAssignMemNB*am = new NetAssignMemNB(mem, idx, rv);
-      am->set_line(*this);
-
-      return am;
-}
-
 /*
  * The l-value of a procedural assignment is a very much constrained
  * expression. To wit, only identifiers, bit selects and part selects
@@ -1139,31 +1052,36 @@ NetProc* PAssignNB::elaborate(Design*des, NetScope*scope) const
 {
       assert(scope);
 
-	/* Catch the case where the lvalue is a reference to a memory
-	   item. These are handled differently. */
-      do {
-	    const PEIdent*id = dynamic_cast<const PEIdent*>(lval());
-	    if (id == 0) break;
-
-	    if (NetMemory*mem = des->find_memory(scope, id->path()))
-		  return assign_to_memory_(mem, id->msb_, des, scope);
-
-      } while(0);
-
-
       NetAssign_*lv = elaborate_lval(des, scope);
       if (lv == 0) return 0;
 
       assert(rval());
 
-	/* Elaborate the r-value expression. This generates a
-	   procedural expression that I attach to the assignment. */
-      NetExpr*rv = rval()->elaborate_expr(des, scope);
-      if (rv == 0)
+      NetExpr*rv;
+
+	/* Evaluate the rval expression if possible, otherwise just
+	   elaborate it. */
+      if (verinum*val = rval()->eval_const(des, scope)) {
+	    rv = new NetEConst(*val);
+	    delete val;
+
+      } else if (rv = rval()->elaborate_expr(des, scope)) {
+
+	      /* OK, go on. */
+
+      } else {
+	      /* Unable to elaborate expression. Retreat. */
 	    return 0;
+      }
 
       assert(rv);
 
+	/* Try to evaluate the expression, at least as far as possible. */
+      if (NetExpr*tmp = rv->eval_tree()) {
+	    delete rv;
+	    rv = tmp;
+      }
+
       { unsigned wid = count_lval_width(lv);
         rv->set_width(wid);
 	rv = pad_to_width(rv, wid);
@@ -1217,8 +1135,10 @@ NetProc* PBlock::elaborate(Design*des, NetScope*scope) const
 	    nscope = scope;
 
 	// Handle the special case that the block contains only one
-	// statement. There is no need to keep the block node.
-      if (list_.count() == 1) {
+	// statement. There is no need to keep the block node. Also,
+	// don't elide named blocks, because they might be referenced
+	// elsewhere.
+      if ((list_.count() == 1) && (name_.length() == 0)) {
 	    assert(list_[0]);
 	    NetProc*tmp = list_[0]->elaborate(des, nscope);
 	    return tmp;
@@ -1415,21 +1335,39 @@ NetProc* PCallTask::elaborate(Design*des, NetScope*scope) const
  * A call to a system task involves elaborating all the parameters,
  * then passing the list to the NetSTask object.
  *XXXX
- * There is a single special in the call to a system task. Normally,
- * an expression cannot take an unindexed memory. However, it is
- * possible to take a system task parameter a memory if the expression
- * is trivial.
+ * There is a single special case in the call to a system
+ * task. Normally, an expression cannot take an unindexed
+ * memory. However, it is possible to take a system task parameter a
+ * memory if the expression is trivial.
  */
 NetProc* PCallTask::elaborate_sys(Design*des, NetScope*scope) const
 {
       assert(scope);
 
-      svector<NetExpr*>eparms (nparms());
+      unsigned parm_count = nparms();
 
-      for (unsigned idx = 0 ;  idx < nparms() ;  idx += 1) {
+	/* Catch the special case that the system task has no
+	   parameters. The "()" string will be parsed as a single
+	   empty parameter, when we really mean no parameters at all. */
+      if ((nparms() == 1) && (parm(0) == 0))
+	    parm_count = 0;
+
+      svector<NetExpr*>eparms (parm_count);
+
+      for (unsigned idx = 0 ;  idx < parm_count ;  idx += 1) {
 	    PExpr*ex = parm(idx);
-
 	    eparms[idx] = ex? ex->elaborate_expr(des, scope, true) : 0;
+
+	      /* Attempt to pre-evaluate the parameters. It may be
+		 possible to at least partially reduce the
+		 expression. */
+	    if (eparms[idx] && !dynamic_cast<NetEConst*>(eparms[idx])) {
+		  NetExpr*tmp = eparms[idx]->eval_tree();
+		  if (tmp != 0) {
+			delete eparms[idx];
+			eparms[idx] = tmp;
+		  }
+	    }
       }
 
       NetSTask*cur = new NetSTask(path_.peek_name(0), eparms);
@@ -1559,22 +1497,6 @@ NetProc* PCallTask::elaborate_usr(Design*des, NetScope*scope) const
 	    if (port->port_type() == NetNet::PINPUT)
 		  continue;
 
-	      /* Handle the special case that the output parameter is
-		 a memory word. Generate a NetAssignMem instead of a
-		 NetAssign. */
-	    NetMemory*mem;
-	    const PEIdent*id = dynamic_cast<const PEIdent*>(parms_[idx]);
-	    if (id && (mem = des->find_memory(scope, id->path()))) {
-
-		  NetExpr*ix = id->msb_->elaborate_expr(des, scope);
-		  assert(ix);
-
-		  NetExpr*rx = new NetESignal(port);
-		  NetAssignMem*am = new NetAssignMem(mem, ix, rx);
-		  block->append(am);
-		  continue;
-	    }
-
 
 	      /* Elaborate an l-value version of the port expression
 		 for output and inout ports. If the expression does
@@ -1918,7 +1840,7 @@ NetProc* PEventStatement::elaborate_st(Design*des, NetScope*scope,
 	    assert(expr_[0]->expr());
 	    PEIdent*id = dynamic_cast<PEIdent*>(expr_[0]->expr());
 	    NetEvent*ev;
-	    if (id && (ev = scope->find_event(id->path()))) {
+	    if (id && (ev = des->find_event(scope, id->path()))) {
 		  NetEvWait*pr = new NetEvWait(enet);
 		  pr->add_event(ev);
 		  pr->set_line(*this);
@@ -1978,7 +1900,7 @@ NetProc* PEventStatement::elaborate_st(Design*des, NetScope*scope,
 		 skip the rest of the expression handling. */
 
 	    if (PEIdent*id = dynamic_cast<PEIdent*>(expr_[idx]->expr())) {
-		  NetEvent*tmp = scope->find_event(id->path());
+		  NetEvent*tmp = des->find_event(scope, id->path());
 		  if (tmp) {
 			wa->add_event(tmp);
 			continue;
@@ -2037,15 +1959,13 @@ NetProc* PEventStatement::elaborate_st(Design*des, NetScope*scope,
 	   expression (and not a named event) then add this
 	   event. Otherwise, we didn't use it so delete it. */
       if (expr_count > 0) {
-	    if (NetEvent*match = ev->find_similar_event()) {
-		  delete ev;
-		  wa->add_event(match);
-
-	    } else {
-
-		  scope->add_event(ev);
-		  wa->add_event(ev);
-	    }
+	    scope->add_event(ev);
+	    wa->add_event(ev);
+	      /* NOTE: This event that I am adding to the wait may be
+		 a duplicate of another event somewhere else. However,
+		 I don't know that until all the modules are hooked
+		 up, so it is best to leave find_similar_event to
+		 after elaboration. */
       } else {
 	    delete ev;
       }
@@ -2352,7 +2272,7 @@ NetProc* PTrigger::elaborate(Design*des, NetScope*scope) const
 {
       assert(scope);
 
-      NetEvent*ev = scope->find_event(event_);
+      NetEvent*ev = des->find_event(scope, event_);
       if (ev == 0) {
 	    cerr << get_line() << ": error: event <" << event_ << ">"
 		 << " not found." << endl;
@@ -2569,113 +2489,58 @@ Design* elaborate(list<const char*>roots)
 
 /*
  * $Log: elaborate.cc,v $
+ * Revision 1.266  2002/12/05 04:15:14  steve
+ *  precalculate r-values of nb assignments and task arguments.
+ *
+ * Revision 1.265  2002/11/26 03:35:13  steve
+ *  Do not set width if width is already OK.
+ *
+ * Revision 1.264  2002/11/09 19:20:48  steve
+ *  Port expressions for output ports are lnets, not nets.
+ *
+ * Revision 1.263  2002/08/28 18:54:36  steve
+ *  Evaluate nonblocking assign r-values.
+ *
+ * Revision 1.262  2002/08/15 02:11:54  steve
+ *  Handle special case of empty system task argument list.
+ *
+ * Revision 1.261  2002/08/13 05:35:00  steve
+ *  Do not elide named blocks.
+ *
+ * Revision 1.260  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.259  2002/07/31 23:55:38  steve
+ *  Add port name to pin size error message.
+ *
+ * Revision 1.258  2002/07/24 16:22:59  steve
+ *  Save event matching for nodangle.
+ *
+ * Revision 1.257  2002/07/18 02:06:37  steve
+ *  Need driver for sure in assign feedback and other cases.
+ *
+ * Revision 1.256  2002/07/18 00:24:22  steve
+ *  Careful with assign to self.
+ *
+ * Revision 1.255  2002/07/03 05:34:59  steve
+ *  Fix scope search for events.
+ *
+ * Revision 1.254  2002/06/19 04:20:03  steve
+ *  Remove NetTmp and add NetSubnet class.
+ *
+ * Revision 1.253  2002/06/05 03:44:25  steve
+ *  Add support for memory words in l-value of
+ *  non-blocking assignments, and remove the special
+ *  NetAssignMem_ and NetAssignMemNB classes.
+ *
+ * Revision 1.252  2002/06/04 05:38:44  steve
+ *  Add support for memory words in l-value of
+ *  blocking assignments, and remove the special
+ *  NetAssignMem class.
+ *
  * Revision 1.251  2002/05/27 00:08:45  steve
  *  Support carrying the scope of named begin-end
  *  blocks down to the code generator, and have
  *  the vvp code generator use that to support disable.
- *
- * Revision 1.250  2002/05/26 01:39:02  steve
- *  Carry Verilog 2001 attributes with processes,
- *  all the way through to the ivl_target API.
- *
- *  Divide signal reference counts between rval
- *  and lval references.
- *
- * Revision 1.249  2002/05/23 03:08:51  steve
- *  Add language support for Verilog-2001 attribute
- *  syntax. Hook this support into existing $attribute
- *  handling, and add number and void value types.
- *
- *  Add to the ivl_target API new functions for access
- *  of complex attributes attached to gates.
- *
- * Revision 1.248  2002/05/12 19:16:58  steve
- *  Accept errors in memory index expression.
- *
- * Revision 1.247  2002/05/07 05:06:07  steve
- *  Use else clause instead of ! to preface wait events.
- *
- * Revision 1.246  2002/04/24 17:40:48  steve
- *  Agressively evalutate case expressions.
- *
- * Revision 1.245  2002/04/22 00:53:39  steve
- *  Do not allow implicit wires in sensitivity lists.
- *
- * Revision 1.244  2002/04/21 22:31:02  steve
- *  Redo handling of assignment internal delays.
- *  Leave it possible for them to be calculated
- *  at run time.
- *
- * Revision 1.243  2002/04/21 04:59:07  steve
- *  Add support for conbinational events by finding
- *  the inputs to expressions and some statements.
- *  Get case and assignment statements working.
- *
- * Revision 1.242  2002/04/13 02:33:17  steve
- *  Detect missing indices to memories (PR#421)
- *
- * Revision 1.241  2002/03/09 04:02:26  steve
- *  Constant expressions are not l-values for task ports.
- *
- * Revision 1.240  2002/01/23 05:56:22  steve
- *  elaborate deassign lval as done for assign.
- *
- * Revision 1.239  2002/01/19 20:09:56  steve
- *  Evaluate case guards, if possible.
- *
- * Revision 1.238  2001/12/31 00:39:20  steve
- *  Remove test print
- *
- * Revision 1.237  2001/12/29 20:19:31  steve
- *  Do not delete delay expressions of UDP instances.
- *
- * Revision 1.236  2001/12/06 05:04:49  steve
- *  Forgot to evaluate UDP delays.
- *
- * Revision 1.235  2001/12/06 04:44:11  steve
- *  Support delays on UDP instances.
- *
- * Revision 1.234  2001/12/03 04:47:14  steve
- *  Parser and pform use hierarchical names as hname_t
- *  objects instead of encoded strings.
- *
- * Revision 1.233  2001/11/22 06:20:59  steve
- *  Use NetScope instead of string for scope path.
- *
- * Revision 1.232  2001/11/08 05:15:50  steve
- *  Remove string paths from PExpr elaboration.
- *
- * Revision 1.231  2001/11/07 04:26:46  steve
- *  elaborate_lnet uses scope instead of string path.
- *
- * Revision 1.230  2001/11/07 04:01:59  steve
- *  eval_const uses scope instead of a string path.
- *
- * Revision 1.229  2001/11/04 23:12:29  steve
- *  Pad limited r-values in continuous assignments.
- *
- * Revision 1.228  2001/10/31 03:22:31  steve
- *  Give up if roots are missing.
- *
- * Revision 1.227  2001/10/28 01:14:53  steve
- *  NetObj constructor finally requires a scope.
- *
- * Revision 1.226  2001/10/22 23:26:37  steve
- *  Better error message for mising root module.
- *
- * Revision 1.225  2001/10/22 02:05:20  steve
- *  Handle activating tasks in another root.
- *
- * Revision 1.224  2001/10/21 00:42:47  steve
- *  Module types in pform are char* instead of string.
- *
- * Revision 1.223  2001/10/20 23:02:40  steve
- *  Add automatic module libraries.
- *
- * Revision 1.222  2001/10/20 05:21:51  steve
- *  Scope/module names are char* instead of string.
- *
- * Revision 1.221  2001/10/19 21:53:24  steve
- *  Support multiple root modules (Philip Blundell)
  */
 

emit.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: emit.cc,v 1.66 2002/03/09 02:10:22 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: emit.cc,v 1.70 2002/11/03 20:36:10 steve Exp $"
 #endif
 
 # include "config.h"
@@ -161,18 +161,6 @@ bool NetAssignNB::emit_proc(struct target_t*tgt) const
       return true;
 }
 
-bool NetAssignMem::emit_proc(struct target_t*tgt) const
-{
-      tgt->proc_assign_mem(this);
-      return true;
-}
-
-bool NetAssignMemNB::emit_proc(struct target_t*tgt) const
-{
-      tgt->proc_assign_mem_nb(this);
-      return true;
-}
-
 bool NetBlock::emit_proc(struct target_t*tgt) const
 {
       return tgt->proc_block(this);
@@ -482,11 +470,31 @@ bool emit(const Design*des, const char*type)
 		  return des->emit(tgt->meth);
 
       }
+
+      cerr << "error: Code generator type " << type
+	   << " not found." << endl;
+      return false;
 }
 
 
 /*
  * $Log: emit.cc,v $
+ * Revision 1.70  2002/11/03 20:36:10  steve
+ *  Error message for mising code generator type.
+ *
+ * Revision 1.69  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.68  2002/06/05 03:44:25  steve
+ *  Add support for memory words in l-value of
+ *  non-blocking assignments, and remove the special
+ *  NetAssignMem_ and NetAssignMemNB classes.
+ *
+ * Revision 1.67  2002/06/04 05:38:44  steve
+ *  Add support for memory words in l-value of
+ *  blocking assignments, and remove the special
+ *  NetAssignMem class.
+ *
  * Revision 1.66  2002/03/09 02:10:22  steve
  *  Add the NetUserFunc netlist node.
  *

eval.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: eval.cc,v 1.27 2002/05/23 03:08:51 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: eval.cc,v 1.32 2002/10/19 22:59:49 steve Exp $"
 #endif
 
 # include "config.h"
@@ -142,16 +142,20 @@ verinum* PEIdent::eval_const(const Design*des, const NetScope*scope) const
       if (expr == 0)
 	    return 0;
 
-      assert(msb_ == 0);
-
-      if (dynamic_cast<const NetEParam*>(expr)) {
-	    cerr << get_line() << ": sorry: I cannot evaluate ``" <<
-		  path_ << "'' in this scope: " << scope->name() << endl;
+      const NetEConst*eval = dynamic_cast<const NetEConst*>(expr);
+      if (eval == 0) {
+	    cerr << get_line() << ": internal error: Unable to evaluate "
+		 << "constant expression (parameter=" << path_
+		 << "): " << *expr << endl;
 	    return 0;
       }
 
-      const NetEConst*eval = dynamic_cast<const NetEConst*>(expr);
       assert(eval);
+
+      if (msb_ || lsb_)
+	    return 0;
+
+
       return new verinum(eval->value());
 }
 
@@ -222,6 +226,22 @@ verinum* PEUnary::eval_const(const Design*des, const NetScope*scope) const
 
 /*
  * $Log: eval.cc,v $
+ * Revision 1.32  2002/10/19 22:59:49  steve
+ *  Redo the parameter vector support to allow
+ *  parameter names in range expressions.
+ *
+ * Revision 1.31  2002/10/13 05:01:07  steve
+ *  More verbose eval_const assert message.
+ *
+ * Revision 1.30  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.29  2002/06/07 02:57:54  steve
+ *  Simply give up on constants with indices.
+ *
+ * Revision 1.28  2002/06/06 18:57:04  steve
+ *  Better error for identifier index eval.
+ *
  * Revision 1.27  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute

eval_attrib.cc

@@ -16,13 +16,15 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT)
-#ident "$Id: eval_attrib.cc,v 1.1 2002/05/23 03:08:51 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: eval_attrib.cc,v 1.5 2002/08/12 01:34:59 steve Exp $"
 #endif
 
+# include  "config.h"
 # include  "util.h"
 # include  "PExpr.h"
 # include  "netlist.h"
+# include  <iostream>
 # include  <assert.h>
 
 /*
@@ -49,11 +51,14 @@ attrib_list_t* evaluate_attributes(const map<string,PExpr*>&att,
 	    table[idx].key = (*cur).first;
 	    PExpr*exp = (*cur).second;
 
+	      /* If the attribute value is given in the source, then
+		 evalulate it as a constant. If the value is not
+		 given, then assume the value is 1. */
 	    verinum*tmp;
 	    if (exp)
 		  tmp = exp->eval_const(des, scope);
 	    else
-		  tmp = new verinum();
+		  tmp = new verinum(1);
 
 	    if (tmp == 0)
 		  cerr << "internal error: no result for " << *exp << endl;
@@ -69,6 +74,18 @@ attrib_list_t* evaluate_attributes(const map<string,PExpr*>&att,
 
 /*
  * $Log: eval_attrib.cc,v $
+ * Revision 1.5  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.4  2002/08/10 21:59:39  steve
+ *  The default attribute value is 1.
+ *
+ * Revision 1.3  2002/06/06 18:57:18  steve
+ *  Use standard name for iostream.
+ *
+ * Revision 1.2  2002/06/03 03:55:14  steve
+ *  compile warnings.
+ *
  * Revision 1.1  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute

eval_rconst.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: eval_rconst.cc,v 1.4 2001/11/07 04:01:59 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: eval_rconst.cc,v 1.5 2002/08/12 01:34:59 steve Exp $"
 #endif
 
 # include "config.h"
@@ -81,6 +81,9 @@ verireal* PEIdent::eval_rconst(const Design*des, const NetScope*scope) const
 
 /*
  * $Log: eval_rconst.cc,v $
+ * Revision 1.5  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.4  2001/11/07 04:01:59  steve
  *  eval_const uses scope instead of a string path.
  *

eval_tree.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: eval_tree.cc,v 1.40 2002/05/25 16:43:47 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: eval_tree.cc,v 1.44 2002/12/05 02:14:33 steve Exp $"
 #endif
 
 # include "config.h"
@@ -752,7 +752,13 @@ NetEConst* NetEConcat::eval_tree()
 			     << "operand has indefinite width: "
 			     << *parms_[idx] << endl;
 			local_errors += 1;
+		  } else if (expr->expr_width() == 0) {
+			cerr << expr->get_line() << ": internal error: "
+			     << "Operand of concatenation has no width: "
+			     << *expr << endl;
+			local_errors += 1;
 		  }
+
 		  gap += expr->expr_width();
 	    }
 
@@ -884,10 +890,57 @@ NetExpr* NetEParam::eval_tree()
 
 	// The result can be saved as the value of the parameter for
 	// future reference, and return a copy to the caller.
-      scope_->set_parameter(name_.peek_name(0), res);
+      scope_->replace_parameter(name_.peek_name(0), res);
       return res->dup_expr();
 }
 
+NetEConst* NetESelect::eval_tree()
+{
+      NetEConst*expr = dynamic_cast<NetEConst*>(expr_);
+      if (expr == 0) {
+	    NetExpr*tmp = expr_->eval_tree();
+	    if (tmp != 0) {
+		  delete expr_;
+		  expr_ = tmp;
+	    }
+
+	    expr = dynamic_cast<NetEConst*>(expr_);
+      }
+
+      NetEConst*base = dynamic_cast<NetEConst*>(base_);
+      if (base == 0) {
+	    NetExpr*tmp = base_->eval_tree();
+	    if (tmp != 0) {
+		  delete base_;
+		  base_ = tmp;
+	    }
+
+	    base = dynamic_cast<NetEConst*>(base_);
+      }
+
+      if (expr == 0)
+	    return 0;
+      if (base == 0)
+	    return 0;
+
+      verinum eval = expr->value();
+      verinum oval (verinum::V0, expr_width(), true);
+      long bval = base->value().as_long();
+
+      for (long idx = 0 ;  idx < expr_width() ;  idx += 1) {
+	    if ((bval >= eval.len()) || (bval < 0))
+		  oval.set(idx, verinum::Vx);
+	    else 
+		  oval.set(idx, eval.get(bval));
+
+	    bval += 1;
+      }
+
+      NetEConst*res = new NetEConst(oval);
+      return res;
+}
+
+
 /*
  * A ternary expression evaluation is controlled by the condition
  * expression. If the condition evaluates to true or false, then
@@ -1134,6 +1187,19 @@ NetEConst* NetEUReduce::eval_tree()
 
 /*
  * $Log: eval_tree.cc,v $
+ * Revision 1.44  2002/12/05 02:14:33  steve
+ *  Support bit select in constant expressions.
+ *
+ * Revision 1.43  2002/11/09 01:40:19  steve
+ *  Postpone parameter width check to evaluation.
+ *
+ * Revision 1.42  2002/10/19 22:59:49  steve
+ *  Redo the parameter vector support to allow
+ *  parameter names in range expressions.
+ *
+ * Revision 1.41  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.40  2002/05/25 16:43:47  steve
  *  Eval ^ and &0 expressions.
  *

examples/hello.vl

@@ -31,7 +31,7 @@
   *  file "hello" which is compiled, linked and ready to run. Run this
   *  program like so:
   *  
-  *      ./hello
+  *      vvp hello
   *  
   *  and the program will print the message to its output. Easy! For
   *  more on how to make the iverilog command work, see the iverilog

examples/hello_vpi.c

@@ -16,7 +16,9 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#ident "$Id: hello_vpi.c,v 1.1 2002/04/18 03:25:16 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: hello_vpi.c,v 1.3 2002/08/12 01:35:01 steve Exp $"
+#endif
 
 /*
  * This file contains an example VPI module to demonstrate the tools
@@ -60,6 +62,12 @@ void (*vlog_startup_routines[])() = {
 };
 /*
  * $Log: hello_vpi.c,v $
+ * Revision 1.3  2002/08/12 01:35:01  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.2  2002/08/11 23:47:04  steve
+ *  Add missing Log and Ident strings.
+ *
  * Revision 1.1  2002/04/18 03:25:16  steve
  *  More examples.
  *

examples/sqrt-virtex.v

@@ -0,0 +1,377 @@
+/*
+ * Copyright (c) 2002 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ *
+ *   $Id: sqrt-virtex.v,v 1.2 2002/11/13 01:49:43 steve Exp $"
+ */
+
+/*
+ * This module is a synthesizeable square-root function. It is also a
+ * detailed example of how to target Xilinx Virtex parts using
+ * Icarus Verilog. In fact, for no particular reason other then to
+ * be excessively specific, I will step through the process of
+ * generating a design for a Spartan-II XC2S15-VQ100, and also how to
+ * generate a generic library part for larger Virtex designs.
+ *
+ * In addition to Icarus Verilog, you will need implementation
+ * software from Xilinx. As of this writing, this example was tested
+ * with Foundation 4.2i, but it should work the same with ISE and
+ * Webpack software.
+ *
+ * This example source contains all the Verilog needed to do
+ * everything described below. We use conditional compilation to
+ * select the bits of Verilog that are needed to perform each specific
+ * task.
+ *
+ * SIMULATE THE DESIGN
+ *
+ * This source file includes a simulation test bench. To compile the
+ * program to include this test bench, use the command line:
+ *
+ *    iverilog -DSIMULATE=1 -oa.out sqrt-virtex.v
+ *
+ * This generates the file "a.out" that can then be executed with the
+ * command:
+ *
+ *    vvp a.out
+ *
+ * This causes the simulation to run a long set of example sqrt
+ * calculations. Each result is checked by the test bench to assure
+ * that the result is valid. When it is done, the program prints
+ * "PASSED" and finishes the simulation.
+ *
+ * When you take a close look at the "main" module below, you will see
+ * that it uses Verilog constructs that are not synthesizeable. This
+ * is fine, as we will never try to synthesize it.
+ *
+ * LIBRARY PARTS
+ *
+ * One can use the sqrt32 module to generate an EDIF file suitable for
+ * use as a library part. This part can be imported to the Xilinx
+ * schematic editor, then placed like any other pre-existing
+ * macro. One can also pass the generated EDIF as a precompiled macro
+ * that other designers may use as they see fit.
+ *
+ * To make an EDIF file from the sqrt32 module, execute the command:
+ *
+ *    iverilog -osqrt32.edf -tfpga -parch=virtex sqrt-virtex.v
+ *
+ * The -parch=virtex tells the code generator to generate code for the
+ * virtex architecture family (we don't yet care what specific part)
+ * and the -osqrt32.edf places the output into the file
+ * sqrt32.edf.
+ *
+ * Without any preprocessor directives, the only module is the sqrt32
+ * module, so sqrt32 is compiled as the root. The ports of the module
+ * are automatically made into ports of the sqrt32.edf netlist, and
+ * the contents of the sqrt32 module are connected approprately.
+ *
+ * COMPLETE CHIP DESIGNS
+ *
+ * To make a complete chip design, there are other bits that need to
+ * be accounted for. Signals must be assigned to pins, and some
+ * special devices may need to be created. We also want to write into
+ * the EDIF file complete part information so that the implementation
+ * tools know how to route the complete design. The command to compile
+ * for our target part is:
+ *
+ *    iverilog -ochip.edf -tfpga \
+ *           -parch=virtex -ppart=XC2S15-VQ100 \
+ *           -DMAKE_CHIP=1 sqrt-virtex.v
+ *
+ * This command uses the "chip" module as the root. This module in
+ * turn has ports that are destined to be the pins of the completed
+ * part. The -ppart= option gives complete part information, that is
+ * in turn written into the EDIF file. This saves us the drudgery of
+ * repeating that part number for later commands.
+ *
+ * The next steps involve Xilinx software, and to talk to Xilinx
+ * software, the netlist must be in the form of an "ngd" file, a
+ * binary netlist format. The command:
+ *
+ *    ngdbuild chip.edf chip.ngd
+ *
+ * does the trick. The input to ngdbuild is the chip.edf file created
+ * by Icarus Verilog, and the output is the chip.ngd file that the
+ * implementation tools may read. From this point, it is best to refer
+ * to Xilinx documentation for the software you are using, but the
+ * quick summary is:
+ *
+ *    map -o map.ncd chip.ngd
+ *    par -w map.ncd chip.ncd
+ *
+ * The result of this sequence of commands is the chip.ncd file that
+ * is ready to be viewed by FPGA Edit, or converted to a bit stream,
+ * or whatever.
+ *
+ * POST MAP SIMULATION
+ *
+ * Warm fuzzies are good, and retesting your design after the part
+ * is mapped by the Xilinx backend tools is a cheap source of fuzzies.
+ * The command to make a Verilog file out of the mapped design is:
+ *
+ *    ngd2ver chip.ngd chip_root.v
+ *
+ * This command creates from the chip.ngd the file "chip_root.v" that
+ * contains Verilog code that simulates the mapped design. This output
+ * Verilog has the single root module "chip_root", which came from the
+ * name of the root module when we were making hte EDIF file in the
+ * first place. The module has ports named just line the ports of the
+ * chip_root module below.
+ *
+ * The generated Verilog uses the library in the directory
+ * $(XILINX)/verilog/src/simprims. This directory comes with the ISE
+ * WebPACK installation that you are using. Icarus Verilog is able to
+ * simulate using that library.
+ *
+ * To compile a post-map simulation of the chip_root.v, use the
+ * command:
+ *
+ *    iverilog -DSIMULATE -DPOST_MAP -ob.out \
+ *             -y $(XILINX)/verilog/src/simprims \
+ *             sqrt-virtex.v chip_root.v \
+ *             $(XILINX)/verilog/src/glbl.v
+ *
+ * This command line generates b.out from the source files
+ * sqrt-virtex.v and chip_root.v (the latter from ngd2ver)
+ * and the "-y <path>" flag specifies the library directory that will
+ * be needed. The glbl.v source file is also included to provide the
+ * GSR and related signals.
+ *
+ * The POST_MAP compiler directive causes the GSR manipulations
+ * included in the test bench to be compiled in, to simulate the chip
+ * startup. Other then that, the test bench runs the post-map design
+ * the same way the pre-synthesis design works.
+ *
+ * Run this design with the command:
+ *
+ *    vvp b.out
+ *
+ * And there you go.
+ */
+
+`ifndef POST_MAP
+ /*
+  * This module approximates the square root of an unsigned 32bit
+  * number. The algorithm works by doing a bit-wise binary search.
+  * Starting from the most significant bit, the accumulated value
+  * tries to put a 1 in the bit position. If that makes the square
+  * too big for the input, the bit is left zero, otherwise it is set
+  * in the result. This continues for each bit, decreasing in
+  * significance, until all the bits are calculated or all the
+  * remaining bits are zero.
+  *
+  * Since the result is an integer, this function really calculates
+  * value of the expression:
+  *
+  *      x = floor(sqrt(y))
+  *
+  * where sqrt(y) is the exact square root of y and floor(N) is the
+  * largest integer <= N.
+  *
+  * For 32bit numbers, this will never run more then 16 iterations,
+  * which amounts to 16 clocks.
+  */
+
+module sqrt32(clk, rdy, reset, x, .y(acc));
+   input  clk;
+   output rdy;
+   input  reset;
+
+   input [31:0] x;
+   output [15:0] acc;
+
+
+   // acc holds the accumulated result, and acc2 is the accumulated
+   // square of the accumulated result.
+   reg [15:0] acc;
+   reg [31:0] acc2;
+
+   // Keep track of which bit I'm working on.
+   reg [4:0]  bitl;
+   wire [15:0] bit = 1 << bitl;
+   wire [31:0] bit2 = 1 << (bitl << 1);
+
+   // The output is ready when the bitl counter underflows.
+   wire rdy = bitl[4];
+
+   // guess holds the potential next values for acc, and guess2 holds
+   // the square of that guess. The guess2 calculation is a little bit
+   // subtle. The idea is that:
+   //
+   //      guess2 = (acc + bit) * (acc + bit)
+   //             = (acc * acc) + 2*acc*bit + bit*bit
+   //             = acc2 + 2*acc*bit + bit2
+   //             = acc2 + 2 * (acc<<bitl) + bit
+   //
+   // This works out using shifts because bit and bit2 are known to
+   // have only a single bit in them.
+   wire [15:0] guess  = acc | bit;
+   wire [31:0] guess2 = acc2 + bit2 + ((acc << bitl) << 1);
+
+   (* ivl_synthesis_on *)
+   always @(posedge clk or posedge reset)
+      if (reset) begin
+	 acc = 0;
+	 acc2 = 0;
+	 bitl = 15;
+      end else begin
+	 if (guess2 <= x) begin
+	    acc  <= guess;
+	    acc2 <= guess2;
+	 end
+	 bitl <= bitl - 5'd1;
+      end
+
+endmodule // sqrt32
+
+`endif //  `ifndef POST_MAP
+
+`ifdef SIMULATE
+ /*
+  * This module is a test bench for the sqrt32 module. It runs some
+  * test input values through the sqrt32 module, and checks that the
+  * output is valid. If an invalid output is generated, print and
+  * error message and stop immediately. If all the tested values pass,
+  * then print PASSED after the test is complete.
+  */
+module main;
+
+   reg [31:0] x;
+   reg 	      clk, reset;
+
+   wire [15:0] y;
+   wire        rdy;
+
+`ifdef POST_MAP
+   chip_root dut(.clk(clk), .reset(reset), .rdy(rdy), .x(x), .y(y));
+`else
+   sqrt32 dut(.clk(clk), .reset(reset), .rdy(rdy), .x(x), .y(y));
+`endif
+
+   (* ivl_synthesis_off *)
+   always #5 clk = !clk;
+
+   task reset_dut;
+      begin
+	 reset = 1;
+	 #1 reset = 0;
+	 @(negedge clk) ;
+      end
+   endtask // reset_dut
+
+   task crank_dut;
+      begin
+	 while (rdy == 0) begin
+	    @(posedge clk) /* wait */;
+	 end
+      end
+   endtask // crank_dut
+
+`ifdef POST_MAP
+   reg        GSR;
+   assign      glbl.GSR = GSR;
+`endif
+
+   integer idx;
+
+   (* ivl_synthesis_off *)
+   initial begin
+      reset = 0;
+      clk = 0;
+
+      /* If doing a post-map simulation, when we need to wiggle
+         The GSR bit to simulate chip power-up. */
+`ifdef POST_MAP
+      GSR = 1;
+      #100 GSR = 0;
+`endif
+      #100 x = 1;
+      reset_dut;
+      crank_dut;
+      $display("x=%d, y=%d", x, y);
+
+      x = 3;
+      reset_dut;
+      crank_dut;
+      $display("x=%d, y=%d", x, y);
+
+      x = 4;
+      reset_dut;
+      crank_dut;
+      $display("x=%d, y=%d", x, y);
+
+      for (idx = 0 ;  idx < 200 ;  idx = idx + 1) begin
+	 x = $random;
+	 reset_dut;
+	 crank_dut;
+	 $display("x=%d, y=%d", x, y);
+
+	 if (x < (y * y)) begin
+	    $display("ERROR: y is too big");
+	    $finish;
+	 end
+
+	 if (x > ((y + 1)*(y + 1))) begin
+	    $display("ERROR: y is too small");
+	    $finish;
+	 end
+      end
+
+      $display("PASSED");
+      $finish;
+   end
+
+endmodule // main
+`endif
+
+`ifdef MAKE_CHIP
+ /*
+  * This module represents the chip packaging that we intend to
+  * generate. We bind pins here, and route the clock to the global
+  * clock buffer.
+  */
+module chip_root(clk, rdy, reset, x, y);
+   input  clk;
+   output rdy;
+   input  reset;
+
+   input [31:0] x;
+   output [15:0] y;
+
+   wire 	 clk_int;
+
+   (* cellref="BUFG:O,I" *)
+   buf gbuf (clk_int, clk);
+
+   sqrt32 dut(.clk(clk_int), .reset(reset), .rdy(rdy), .x(x), .y(y));
+
+   /* Assign the clk to GCLK0, which is on pin P39. */
+   $attribute(clk, "PAD", "39");
+
+   // We don't care where the remaining pins go, so set the pin number
+   // to 0. This tells the implementation tools that we want a PAD,
+   // but we don't care which. Also note the use of a comma (,)
+   // separated list to assign pins to the bits of a vector.
+   $attribute(rdy, "PAD", "0");
+   $attribute(reset, "PAD", "0");
+   $attribute(x, "PAD", "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0");
+   $attribute(y, "PAD", "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0");
+
+endmodule // chip_root
+
+`endif

expr_synth.cc

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: expr_synth.cc,v 1.33 2002/05/26 01:39:02 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: expr_synth.cc,v 1.37 2002/11/17 23:37:55 steve Exp $"
 #endif
 
 # include "config.h"
@@ -50,6 +50,7 @@ NetNet* NetEBAdd::synthesize(Design*des)
 
       string path = lsig->scope()->name()+"."+lsig->scope()->local_symbol();
       NetNet*osig = new NetNet(lsig->scope(), path, NetNet::IMPLICIT, width);
+      osig->local_flag(true);
 
       string oname = des->local_symbol(path);
       NetAddSub *adder = new NetAddSub(lsig->scope(), oname, width);
@@ -107,6 +108,26 @@ NetNet* NetEBBits::synthesize(Design*des)
 	    string oname = des->local_symbol(path);
 	    NetLogic*gate;
 
+	      /* If the rsig bit is constant, then look for special
+		 cases that I can use to reduce the generated
+		 logic. If I find one, then handle it immediately and
+		 skip the rest of the processing of this bit. */
+	    if (rsig->pin(idx).nexus()->drivers_constant()) {
+		  verinum::V bval = rsig->pin(idx).nexus()->driven_value();
+
+		    /* (A & 0) is (0) */
+		  if ((op() == '&') && bval == verinum::V0) {
+			connect(osig->pin(idx), rsig->pin(idx));
+			continue;
+		  }
+
+		    /* (A & 1) is A */
+		  if ((op() == '&') && bval == verinum::V1) {
+			connect(osig->pin(idx), lsig->pin(idx));
+			continue;
+		  }
+	    }
+
 	    switch (op()) {
 		case '&':
 		  gate = new NetLogic(scope, oname, 3, NetLogic::AND);
@@ -171,6 +192,33 @@ NetNet* NetEBComp::synthesize(Design*des)
 		  gate = new NetLogic(scope, des->local_symbol(path),
 				      lsig->pin_count()+1, NetLogic::OR);
 		  break;
+
+		case '>':
+		    /* sig > 0 is true if any bit in sig is set. This
+		       is very much like sig != 0. (0 > sig) shouldn't
+		       happen. */
+		  if (rcon) {
+			gate = new NetLogic(scope, des->local_symbol(path),
+					    lsig->pin_count()+1, NetLogic::OR);
+		  } else {
+			assert(0);
+			gate = new NetLogic(scope, des->local_symbol(path),
+				      lsig->pin_count()+1, NetLogic::NOR);
+		  }
+		  break;
+
+		case '<':
+		    /* 0 < sig is handled like sig > 0. */
+		  if (! rcon) {
+			gate = new NetLogic(scope, des->local_symbol(path),
+					    lsig->pin_count()+1, NetLogic::OR);
+		  } else {
+			assert(0);
+			gate = new NetLogic(scope, des->local_symbol(path),
+				      lsig->pin_count()+1, NetLogic::NOR);
+		  }
+		  break;
+
 		default:
 		  assert(0);
 	    }
@@ -587,6 +635,18 @@ NetNet* NetESignal::synthesize(Design*des)
 
 /*
  * $Log: expr_synth.cc,v $
+ * Revision 1.37  2002/11/17 23:37:55  steve
+ *  Magnitude compare to 0.
+ *
+ * Revision 1.36  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.35  2002/07/07 22:31:39  steve
+ *  Smart synthesis of binary AND expressions.
+ *
+ * Revision 1.34  2002/07/05 21:26:17  steve
+ *  Avoid emitting to vvp local net symbols.
+ *
  * Revision 1.33  2002/05/26 01:39:02  steve
  *  Carry Verilog 2001 attributes with processes,
  *  all the way through to the ivl_target API.

functor.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2000 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2002 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: functor.cc,v 1.26 2001/10/19 21:53:24 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: functor.cc,v 1.31 2002/08/16 05:18:27 steve Exp $"
 #endif
 
 # include "config.h"
@@ -128,30 +128,31 @@ void Design::functor(functor_t*fun)
 
 	// apply to nodes
       if (nodes_) {
+	    assert(nodes_functor_cur_ == 0);
+	    assert(nodes_functor_nxt_ == 0);
+
 	      /* Scan the circular list of nodes, starting with the
-		 front of the list. (nodes_ points to the *end* of the
-		 list.) The bar is the end point. At the end of the
-		 do-while loop, I know that the bar has been
-		 processed or (if bar == 0) no undeleted node has been
-		 processed. */
-	    NetNode*cur = nodes_->node_next_;
-	    NetNode*bar = 0;
+		 front of the list.
+
+		 This loop interacts with the Design::del_node method
+		 so that the functor is free to delete any nodes it
+		 choose. The destructors of the NetNode objects call
+		 the del_node method, which checks with the
+		 nodes_functor_* members, to keep the iterator
+		 operating safely. */
+	    nodes_functor_cur_ = nodes_;
 	    do {
-		  NetNode*tmp = cur->node_next_;
-		  cur->functor_node(this, fun);
+		  nodes_functor_nxt_ = nodes_functor_cur_->node_next_;
+		  nodes_functor_cur_->functor_node(this, fun);
 
-		    /* Detect the case that cur has been deleted by
-		       noticing if tmp->node_prev_ no longer points to
-		       cur. If that's the case, clear the bar. */
-		  if (tmp->node_prev_ != cur) {
-			if (cur == bar)
-			      bar = 0;
-		  } else if (bar == 0) {
-			bar = cur;
-		  }
-		  cur = tmp;
+		  if (nodes_functor_nxt_ == 0)
+			break;
+
+		  nodes_functor_cur_ = nodes_functor_nxt_;
+	    } while (nodes_ && (nodes_functor_cur_ != nodes_));
+	    nodes_functor_cur_ = 0;
+	    nodes_functor_nxt_ = 0;
 
-	    } while (nodes_ && (cur != bar));
       }
 }
 
@@ -234,35 +235,13 @@ int NetAssignNB::match_proc(proc_match_t*that)
       return that->assign_nb(this);
 }
 
-int proc_match_t::assign_mem(NetAssignMem*)
-{
-      return 0;
-}
-
-int NetAssignMem::match_proc(proc_match_t*that)
-{
-      return that->assign_mem(this);
-}
-
-int proc_match_t::assign_mem_nb(NetAssignMemNB*)
-{
-      return 0;
-}
-
-int NetAssignMemNB::match_proc(proc_match_t*that)
-{
-      return that->assign_mem_nb(this);
-}
-
 int proc_match_t::block(NetBlock*)
 {
-      cerr << "default (failing) match for block" << endl;
       return 0;
 }
 
 int NetBlock::match_proc(proc_match_t*that)
 {
-      cerr << "NetBlock::match_proc" << endl;
       return that->block(this);
 }
 
@@ -288,6 +267,25 @@ int proc_match_t::event_wait(NetEvWait*)
 
 /*
  * $Log: functor.cc,v $
+ * Revision 1.31  2002/08/16 05:18:27  steve
+ *  Fix intermix of node functors and node delete.
+ *
+ * Revision 1.30  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.29  2002/08/10 22:07:38  steve
+ *  Remove useless error messages.
+ *
+ * Revision 1.28  2002/06/05 03:44:25  steve
+ *  Add support for memory words in l-value of
+ *  non-blocking assignments, and remove the special
+ *  NetAssignMem_ and NetAssignMemNB classes.
+ *
+ * Revision 1.27  2002/06/04 05:38:44  steve
+ *  Add support for memory words in l-value of
+ *  blocking assignments, and remove the special
+ *  NetAssignMem class.
+ *
  * Revision 1.26  2001/10/19 21:53:24  steve
  *  Support multiple root modules (Philip Blundell)
  *
@@ -306,77 +304,5 @@ int proc_match_t::event_wait(NetEvWait*)
  *
  * Revision 1.21  2000/08/01 02:48:41  steve
  *  Support <= in synthesis of DFF and ram devices.
- *
- * Revision 1.20  2000/07/16 04:56:07  steve
- *  Handle some edge cases during node scans.
- *
- * Revision 1.19  2000/07/15 05:13:43  steve
- *  Detect muxing Vz as a bufufN.
- *
- * Revision 1.18  2000/05/02 00:58:12  steve
- *  Move signal tables to the NetScope class.
- *
- * Revision 1.17  2000/04/20 00:28:03  steve
- *  Catch some simple identity compareoptimizations.
- *
- * Revision 1.16  2000/04/18 04:50:19  steve
- *  Clean up unneeded NetEvent objects.
- *
- * Revision 1.15  2000/04/16 23:32:18  steve
- *  Synthesis of comparator in expressions.
- *
- *  Connect the NetEvent and related classes
- *  together better.
- *
- * Revision 1.14  2000/04/12 20:02:53  steve
- *  Finally remove the NetNEvent and NetPEvent classes,
- *  Get synthesis working with the NetEvWait class,
- *  and get started supporting multiple events in a
- *  wait in vvm.
- *
- * Revision 1.13  2000/04/01 21:40:22  steve
- *  Add support for integer division.
- *
- * Revision 1.12  2000/02/23 02:56:54  steve
- *  Macintosh compilers do not support ident.
- *
- * Revision 1.11  2000/02/13 04:35:43  steve
- *  Include some block matching from Larry.
- *
- * Revision 1.10  2000/01/13 03:35:35  steve
- *  Multiplication all the way to simulation.
- *
- * Revision 1.9  2000/01/02 17:57:20  steve
- *  Handle nodes running out during node scan.
- *
- * Revision 1.8  1999/12/30 04:19:12  steve
- *  Propogate constant 0 in low bits of adders.
- *
- * Revision 1.7  1999/12/17 06:18:16  steve
- *  Rewrite the cprop functor to use the functor_t interface.
- *
- * Revision 1.6  1999/12/05 02:24:08  steve
- *  Synthesize LPM_RAM_DQ for writes into memories.
- *
- * Revision 1.5  1999/12/01 06:06:16  steve
- *  Redo synth to use match_proc_t scanner.
- *
- * Revision 1.4  1999/11/18 03:52:19  steve
- *  Turn NetTmp objects into normal local NetNet objects,
- *  and add the nodangle functor to clean up the local
- *  symbols generated by elaboration and other steps.
- *
- * Revision 1.3  1999/11/01 02:07:40  steve
- *  Add the synth functor to do generic synthesis
- *  and add the LPM_FF device to handle rows of
- *  flip-flops.
- *
- * Revision 1.2  1999/07/18 05:52:46  steve
- *  xnfsyn generates DFF objects for XNF output, and
- *  properly rewrites the Design netlist in the process.
- *
- * Revision 1.1  1999/07/17 22:01:13  steve
- *  Add the functor interface for functor transforms.
- *
  */
 

functor.h

@@ -18,8 +18,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: functor.h,v 1.17 2000/09/17 21:26:15 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: functor.h,v 1.20 2002/08/12 01:34:59 steve Exp $"
 #endif
 
 /*
@@ -83,9 +83,7 @@ struct proc_match_t {
       virtual ~proc_match_t();
 
       virtual int assign(class NetAssign*);
-      virtual int assign_mem(class NetAssignMem*);
       virtual int assign_nb(class NetAssignNB*);
-      virtual int assign_mem_nb(class NetAssignMemNB*);
       virtual int condit(class NetCondit*);
       virtual int event_wait(class NetEvWait*);
       virtual int block(class NetBlock*);
@@ -94,6 +92,19 @@ struct proc_match_t {
 
 /*
  * $Log: functor.h,v $
+ * Revision 1.20  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.19  2002/06/05 03:44:25  steve
+ *  Add support for memory words in l-value of
+ *  non-blocking assignments, and remove the special
+ *  NetAssignMem_ and NetAssignMemNB classes.
+ *
+ * Revision 1.18  2002/06/04 05:38:44  steve
+ *  Add support for memory words in l-value of
+ *  blocking assignments, and remove the special
+ *  NetAssignMem class.
+ *
  * Revision 1.17  2000/09/17 21:26:15  steve
  *  Add support for modulus (Eric Aardoom)
  *
@@ -108,32 +119,5 @@ struct proc_match_t {
  *
  * Revision 1.13  2000/04/20 00:28:03  steve
  *  Catch some simple identity compareoptimizations.
- *
- * Revision 1.12  2000/04/18 04:50:19  steve
- *  Clean up unneeded NetEvent objects.
- *
- * Revision 1.11  2000/04/12 20:02:53  steve
- *  Finally remove the NetNEvent and NetPEvent classes,
- *  Get synthesis working with the NetEvWait class,
- *  and get started supporting multiple events in a
- *  wait in vvm.
- *
- * Revision 1.10  2000/04/01 21:40:22  steve
- *  Add support for integer division.
- *
- * Revision 1.9  2000/02/23 02:56:54  steve
- *  Macintosh compilers do not support ident.
- *
- * Revision 1.8  2000/02/13 04:35:43  steve
- *  Include some block matching from Larry.
- *
- * Revision 1.7  2000/01/13 03:35:35  steve
- *  Multiplication all the way to simulation.
- *
- * Revision 1.6  1999/12/30 04:19:12  steve
- *  Propogate constant 0 in low bits of adders.
- *
- * Revision 1.5  1999/12/17 06:18:16  steve
- *  Rewrite the cprop functor to use the functor_t interface.
  */
 #endif

ieee1364-notes.txt

@@ -86,7 +86,7 @@ tool so it is not clear that the standard really is at fault. It is
 clear, however, that somebody goofed somewhere.
 
 My personal opinion is that there is no logical need to require that
-all module_item_declarations preceed any other module items. I
+all module_item_declarations precede any other module items. I
 personally would oppose such a restriction. It may make sense to
 require that declarations of variables within a module be preceded by
 their use, although even that is not necessary for the implementation
@@ -97,7 +97,7 @@ sample2 can have implications that affect any declaration order
 rules. When reaching into a module with a hierarchical name, the
 module being referenced is already completely declared (or not
 declared at all, as in sample2) so module_item order is completely
-irrelevent. But a "declare before use" rule would infect module
+irrelevant. But a "declare before use" rule would infect module
 ordering, by requiring that modules that are used be first defined.
 
 
@@ -141,7 +141,7 @@ ports.
 
 With the above in mind, I have decided to *allow* function and task
 ports to be declared with types, as long as the types are variable
-types, such ag reg or integer. Without this, there would be no
+types, such as reg or integer. Without this, there would be no
 portable way to pass integers into functions/tasks. The standard does
 not say it is allowed, but it doesn't *disallow* it, and other
 commercial tools seem to work similarly.
@@ -172,7 +172,7 @@ take it that x is allowed, as that is what Verilog-XL does.
 
 There seems to be ambiguity in how code like this should be parsed:
 
-	repeat (5) @(posedge clk) <statment>;
+	repeat (5) @(posedge clk) <statement>;
 
 There are two valid interpretations of this code, from the
 IEEE1364-1995 standard. One looks like this:
@@ -386,7 +386,7 @@ changes in inputs until the thread that changed the inputs yields
 execution.
 
 
-* BIT AND PART SELECTS OF PARAMTERS
+* BIT AND PART SELECTS OF PARAMETERS
 
 Bit and part selects are supposed to only be supported on vector nets
 and variables (wires, regs, etc.) However, it is common for Verilog
@@ -399,9 +399,19 @@ value with a defined size. The parameter value is considered be a
 constant vector of bits foo[X:0]. That is, zero based. The bit and
 part selects operate from that assumption.
 
+Verilog 2001 adds syntax to allow the user to explicitly declare the
+parameter range (i.e. parameter [5:0] foo = 9;) so Icarus Verilog will
+(or should) use the explicitly declared vector dimensions to interpret
+bit and part selects.
 
-$Id: ieee1364-notes.txt,v 1.11 2002/04/27 02:38:04 steve Exp $
+$Id: ieee1364-notes.txt,v 1.13 2002/08/20 04:11:53 steve Exp $
 $Log: ieee1364-notes.txt,v $
+Revision 1.13  2002/08/20 04:11:53  steve
+ Support parameters with defined ranges.
+
+Revision 1.12  2002/06/11 03:34:33  steve
+ Spelling patch (Larry Doolittle)
+
 Revision 1.11  2002/04/27 02:38:04  steve
  Support selecting bits from parameters.
 

iverilog-vpi.man

@@ -1,9 +1,10 @@
-.TH iverilog-vpi 1 "$Date: 2002/05/28 05:21:30 $" Version "$Date: 2002/05/28 05:21:30 $"
+.TH iverilog-vpi 1 "$Date: 2002/11/23 00:51:53 $" Version "$Date: 2002/11/23 00:51:53 $"
 .SH NAME
 iverilog-vpi - Compile front end for VPI modules
 
 .SH SYNOPSIS
 .B iverilog-vpi
+[--name=\fIname\fP]
 \fIsourcefile\fP...
 
 .SH DESCRIPTION
@@ -26,13 +27,42 @@ first source file is named \fIfoo.c\fP, the output becomes
 Include the named library in the link of the VPI module. This allows
 VPI modules to further reference external libraries.
 
+.TP 8
+.B --name=\fIname\fP
+Normally, the output VPI module will be named after the first source
+file passed to the command. This flag sets the name (without the .vpi
+suffix) of the output vpi module.
+
+.SH "PC-ONLY OPTIONS"
+
+The PC port of \fIiverilog-vpi\fP includes two special flags needed to
+support the more intractable development environment. These flags help
+the program locate parts that it needs.
+
+.TP 8
+.B -mingw=\fIpath\fP
+Tell the program the root of the Mingw compiler tool suite. The
+\fBvvp\fP runtime is compiled with this compiler, and this is the
+compiler that \fIiverilog-vpi\fP expects to use to compile your source
+code. This is notmally not needed, and if you do use it, it is only
+needed once. The compiler will save the \fIpath\fP in the registry for
+use later.
+
+.TP 8
+.B -ivl=\fIpath\fP
+Set for the use during compilation the root if the Icarus Verilog
+install. This is the place where you installed Icarus Verilog when you
+ran the installer. This flag is also only needed once, and the path is
+stored in the registry for future use.
+
 .SH "AUTHOR"
 .nf
 Steve Williams ([email protected])
 
 .SH SEE ALSO
 iverilog(1), vvp(1),
-.BR "<http://www.icarus.com/eda/verilog/>"
+.BR "<http://www.icarus.com/eda/verilog/>",
+.BR "<http://www.mingw.org>",
 
 .SH COPYRIGHT
 .nf

iverilog-vpi.sh

@@ -17,17 +17,17 @@
 #    59 Temple Place - Suite 330
 #    Boston, MA 02111-1307, USA
 #
-#ident "$Id: iverilog-vpi.sh,v 1.4 2002/05/23 03:35:05 steve Exp $"
+#ident "$Id: iverilog-vpi.sh,v 1.9 2002/10/19 23:18:52 steve Exp $"
 
 # These are the variables used for compiling files
 CC=gcc
 CXX=gcc
-CFLAGS="@PIC@ -O"
+CFLAGS="@PIC@ -O -I@INCLUDEDIR@"
 
 # These are used for linking...
 LD=gcc
 LDFLAGS="@SHARED@"
-LDLIBS="-lveriuser -lvpi"
+LDLIBS="-L@LIBDIR@ -lveriuser -lvpi"
 
 CCSRC=
 CXSRC=
@@ -44,13 +44,13 @@ do
     case $parm
     in
 
-    *.c) CCSRC="$SRC $parm"
+    *.c) CCSRC="$CCSRC $parm"
          if [ x$OUT = x ]; then
 	    OUT=`basename $parm .c`
 	 fi
 	 ;;
 
-    *.cc) CXSRC="$SRC $parm"
+    *.cc) CXSRC="$CXSRC $parm"
          if [ x$OUT = x ]; then
 	    OUT=`basename $parm .cc`
 	 fi
@@ -62,6 +62,10 @@ do
 	 fi
 	 ;;
 
+    --name=*)
+	 OUT=`echo $parm | cut -b8-`
+	 ;;
+
     -l*) LIB="$LIB $parm"
 	 ;;
 
@@ -70,7 +74,7 @@ do
 done
 
 if [ x$OUT = x ]; then
-    echo "Usage: vpi-tool [src and obj files]..."
+    echo "Usage: $0 [src and obj files]..."
     exit 0
 fi
 
@@ -80,25 +84,23 @@ OUT=$OUT".vpi"
 compile_errors=0
 
 # Compile all the source files into object files
-for src
-in $CCSRC
+for src in $CCSRC
 do
     base=`basename $src .c`
     obj=$base".o"
 
     echo "Compiling $src..."
-    $CC -c -o $obj $src || compile_errors=`expr $compile_errors + 1`
+    $CC -c -o $obj $CFLAGS $src || compile_errors=`expr $compile_errors + 1`
     OBJ="$OBJ $obj"
 done
 
-for src
-in $CXSRC
+for src in $CXSRC
 do
     base=`basename $src .cc`
     obj=$base".o"
 
     echo "Compiling $src..."
-    $CXX -c -o $obj $src || compile_errors=`expr $compile_errors + 1`
+    $CXX -c -o $obj $CFLAGS $src || compile_errors=`expr $compile_errors + 1`
     OBJ="$OBJ $obj"
 done
 
@@ -109,4 +111,4 @@ then
 fi
 
 echo "Making $OUT from $OBJ..."
-exec $LD -o $OUT $LDFLAGS $OBJ $LDLIBS
+exec $LD -o $OUT $LDFLAGS $OBJ $LIB $LDLIBS

iverilog.conf

@@ -72,21 +72,11 @@
 # These rules support synthesized and non-synthesized variants.
 
 [-tvvp -S]
-<ivl>%B/ivl %[v-v] -C%C %g %W %s %[M-M%M] %[N-N%N] %[T-T%T] -tdll -fDLL=%B/vvp.tgt -fVVP_EXECUTABLE=%B/../../bin/vvp -Fsynth -Fsyn-rules -Fcprop -Fnodangle %f %m -o%o -- -
+<ivl>%B/ivl %[v-v] -C%C %g %W %s %[M-M%M] %[N-N%N] %[T-T%T] -tdll -fDLL=%B/vvp.tgt -fVVP_EXECUTABLE=%B/../../bin/vvp -Fsynth2 -Fsynth -Fsyn-rules -Fcprop -Fnodangle %f %m -o%o -- -
 
 [-tvvp]
 <ivl>%B/ivl %[v-v] -C%C %g %W %s %[M-M%M] %[N-N%N] %[T-T%T] -tdll -fDLL=%B/vvp.tgt -fVVP_EXECUTABLE=%B/../../bin/vvp -Fcprop -Fnodangle %f %m -o%o -- -
 
-# --
-# The vvm target uses the <ivl> string to take the preprocessed code from
-# standard input, compile it with the vvm code generator and write the
-# result to %o.cc. The driver assumes this when invoking the C++ compiler
-# on the result.
-
-[-tvvm]
-<ivl>%B/ivl %[v-v] -C%C %g %W %s %[N-N%N] %[T-T%T] -tvvm -Fcprop -Fnodangle -fVPI_MODULE_PATH=%B %f %m -o%o.cc -- -
-
-
 # This is the XNF code generator.
 
 [-txnf]
@@ -94,7 +84,7 @@
 
 # And this is another XNF code generator, under development.
 [-tfpga]
-<ivl>%B/ivl -C%C %[v-v] %g %s %[M-M%M] %[N-N%N] %[T-T%T] %f -tdll -fDLL=%B/fpga.tgt -Fsynth -Fsyn-rules -Fcprop -Fnodangle -o%o -- -
+<ivl>%B/ivl -C%C %[v-v] %g %s %[M-M%M] %[N-N%N] %[T-T%T] %f -tdll -fDLL=%B/fpga.tgt -Fsynth2 -Fsynth -Fsyn-rules -Fcprop -Fnodangle -o%o -- -
 
 # --
 # This is the pal code generator. The target module requires the -fpart=<type>

ivl.def

@@ -54,6 +54,9 @@ ivl_logic_pin
 ivl_logic_pins
 ivl_logic_udp
 
+ivl_lpm_aset_value
+ivl_lpm_async_clr
+ivl_lpm_async_set
 ivl_lpm_basename
 ivl_lpm_clk
 ivl_lpm_data
@@ -81,8 +84,8 @@ ivl_lval_pins
 ivl_lval_sig
 
 ivl_memory_basename
-ivl_memory_name
 ivl_memory_root
+ivl_memory_scope
 ivl_memory_size
 ivl_memory_width
 
@@ -123,6 +126,8 @@ ivl_scope_tname
 ivl_signal_attr
 ivl_signal_attr_cnt
 ivl_signal_attr_val
+ivl_signal_integer
+ivl_signal_local
 ivl_signal_pin
 ivl_signal_pins
 ivl_signal_port

ivl_target.h

@@ -18,8 +18,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: ivl_target.h,v 1.98 2002/05/27 00:08:45 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: ivl_target.h,v 1.108 2002/10/23 01:47:17 steve Exp $"
 #endif
 
 #ifdef __cplusplus
@@ -98,7 +98,7 @@ _BEGIN_DECL
  * ivl_process_t
  *    A Verilog process is represented by one of these. A process may
  *    be an "initial" or an "always" process. These come from initial
- *    or always statements from the verilog source.
+ *    or always statements from the Verilog source.
  *
  * ivl_scope_t
  *    Elaborated scopes within a design are represented by this
@@ -337,7 +337,7 @@ typedef const struct ivl_attribute_s*ivl_attribute_t;
  *
  * ivl_design_process
  *    This function scans the processes (threads) in the design. It
- *    calls the user suplied function on each of the processes until
+ *    calls the user supplied function on each of the processes until
  *    one of the functors returns non-0 or all the processes are
  *    scanned. This function will return 0, or the non-zero value that
  *    was returned from the last scanned process.
@@ -418,7 +418,15 @@ extern ivl_nexus_t ivl_event_pos(ivl_event_t net, unsigned idx);
  *
  * ivl_expr_width
  *    This method returns the bit width of the expression at this
- *    node. It can be applied to any expression node.
+ *    node. It can be applied to any expression node, and returns the
+ *    *output* width of the expression node.
+ *
+ * ivl_expr_opcode
+ *    IVL_EX_BINARY and IVL_EX_UNARY expression nodes include an
+ *    upcode from this table:
+ *              &   -- AND
+ *              A   -- NAND (~&)
+ *              X   -- XNOR (~^)
  */
 
 extern ivl_expr_type_t ivl_expr_type(ivl_expr_t net);
@@ -429,7 +437,7 @@ extern const char* ivl_expr_bits(ivl_expr_t net);
 extern ivl_scope_t ivl_expr_def(ivl_expr_t net);
   /* IVL_EX_SIGNAL */
 extern unsigned    ivl_expr_lsi(ivl_expr_t net);
-  /* IVL_EX_SIGNAL, IVL_EX_SFUNC, IVL_EX_MEMORY */
+  /* IVL_EX_SIGNAL, IVL_EX_SFUNC */
 extern const char* ivl_expr_name(ivl_expr_t net);
   /* IVL_EX_BINARY IVL_EX_UNARY */
 extern char        ivl_expr_opcode(ivl_expr_t net);
@@ -461,13 +469,28 @@ extern unsigned    ivl_expr_width(ivl_expr_t net);
 /*
  * Memory.
  *
+ * ivl_memory_name (DEPRECATED)
+ *
+ * ivl_memory_basename
+ *    This returns the base name of the memory object. The base name
+ *    does not include the name of the scopes that contains the object.
+ *
+ * ivl_memory_size
+ * ivl_memory_width
+ *    These functions return the dimensions of the memory. The size is
+ *    the number of words in the memory, and the width is the number
+ *    of bits in each word.
+ *
+ * ivl_memory_scope
+ *    This returns the scope that contains the memory.
  */
 
-extern const char*ivl_memory_name(ivl_memory_t net);
 extern const char*ivl_memory_basename(ivl_memory_t net);
 extern int ivl_memory_root(ivl_memory_t net);
+extern ivl_scope_t ivl_memory_scope(ivl_memory_t net);
 extern unsigned ivl_memory_size(ivl_memory_t net);
 extern unsigned ivl_memory_width(ivl_memory_t net);
+
 extern ivl_memory_t ivl_expr_memory(ivl_expr_t net);
 
 /* LOGIC
@@ -515,7 +538,7 @@ extern unsigned    ivl_logic_pins(ivl_net_logic_t net);
 extern ivl_udp_t   ivl_logic_udp(ivl_net_logic_t net);
 extern unsigned    ivl_logic_delay(ivl_net_logic_t net, unsigned transition);
 
-  /* DEPRICATED */
+  /* DEPRECATED */
 extern const char* ivl_logic_attr(ivl_net_logic_t net, const char*key);
 
 extern unsigned        ivl_logic_attr_cnt(ivl_net_logic_t net);
@@ -550,7 +573,7 @@ extern const char* ivl_udp_name(ivl_udp_t net);
  *    this device.
  *
  * ivl_lpm_type
- *    Return the ivl_lpm_type_t of the secific LPM device.
+ *    Return the ivl_lpm_type_t of the specific LPM device.
  *
  * ivl_lpm_width
  *    Return the width of the LPM device. What this means depends on
@@ -567,7 +590,7 @@ extern const char* ivl_udp_name(ivl_udp_t net);
  *    vector for devices that have more inputs.
  *
  * ivl_lpm_datab
- *    Return the input data nexis for device types that have a second
+ *    Return the input data nexus for device types that have a second
  *    input vector. For example, arithmetic devices are like this.
  *
  * ivl_lpm_q
@@ -580,7 +603,7 @@ extern const char* ivl_udp_name(ivl_udp_t net);
  *
  * ivl_lpm_size
  *    In addition to a width, some devices have a size. The size is
- *    often the number of inputs per out, i.e. the number of inputs
+ *    often the number of inputs per out, i.e., the number of inputs
  *    per bit for a MUX.
  */
 extern const char*    ivl_lpm_name(ivl_lpm_t net);
@@ -589,6 +612,10 @@ extern ivl_scope_t    ivl_lpm_scope(ivl_lpm_t net);
 extern ivl_lpm_type_t ivl_lpm_type(ivl_lpm_t net);
 extern unsigned       ivl_lpm_width(ivl_lpm_t net);
 
+  /* IVL_LPM_FF */
+extern ivl_nexus_t ivl_lpm_async_clr(ivl_lpm_t net);
+extern ivl_nexus_t ivl_lpm_async_set(ivl_lpm_t net);
+extern ivl_expr_t  ivl_lpm_aset_value(ivl_lpm_t net);
   /* IVL_LPM_FF IVL_LPM_RAM */
 extern ivl_nexus_t ivl_lpm_clk(ivl_lpm_t net);
   /* IVL_LPM_UFUNC */
@@ -705,7 +732,7 @@ extern ivl_signal_t ivl_lval_sig(ivl_lval_t net);
  *    connected to the nexus.
  *
  *    If the target is an LPM device, then this value is zero, and it
- *    is up to the application to find the pin that referse to this
+ *    is up to the application to find the pin that refers to this
  *    nexus. The problem is that LPM devices do not have a pinout per
  *    se, the pins all have specific names.
  *
@@ -805,7 +832,7 @@ extern ivl_signal_t ivl_nexus_ptr_sig(ivl_nexus_ptr_t net);
  *
  * ivl_scope_lpm
  * ivl_scope_lpms
- *    Scopes have 0 or more LPM devices in them. These functions acess
+ *    Scopes have 0 or more LPM devices in them. These functions access
  *    those devices.
  *
  * ivl_scope_name
@@ -868,7 +895,7 @@ extern const char*  ivl_scope_tname(ivl_scope_t net);
 
 /* SIGNALS
  * Signals are named things in the Verilog source, like wires and
- * regs, and also named things that are preated as temporaries during
+ * regs, and also named things that are created as temporaries during
  * certain elaboration or optimization steps. A signal may also be a
  * port of a module or task.
  *
@@ -878,7 +905,7 @@ extern const char*  ivl_scope_tname(ivl_scope_t net);
  * ivl_signal_pins
  * ivl_signal_pin
  *    The ivl_signal_pin function returns the nexus connected to the
- *    signal. If the signal is a vectory, the idx can be a non-zero
+ *    signal. If the signal is a vector, the idx can be a non-zero
  *    value, and the result is the nexus for the specified bit.
  *
  * ivl_signal_port
@@ -891,16 +918,28 @@ extern const char*  ivl_scope_tname(ivl_scope_t net);
  *    net or variable may be signed. This function returns true if the
  *    signal is signed.
  *
- * ivl_signal_type
- *    Return the type of the signal, i.e. reg, wire, tri0, et al.
+ * ivl_signal_local
+ *    A signal that was generated by the compiler as a place holder is
+ *    marked as local.
  *
- * ivl_signal_name
+ * ivl_signal_type
+ *    Return the type of the signal, i.e., reg, wire, tri0, etc.
+ *
+ * ivl_signal_name (DEPRECATED)
  *    This function returns the fully scoped hierarchical name for the
  *    signal. The name refers to the entire vector that is the signal.
  *
+ *    NOTE: This function is deprecated. The heirarchical name is too
+ *    vague a construct when escaped names can have . characters in
+ *    them. Do no use this function in new code, it will disappear.
+ *
  * ivl_signal_basename
  *    This function returns the name of the signal, without the scope
- *    information. This is the tail of the signal name.
+ *    information. This is the tail of the signal name. Since Verilog
+ *    has an escape syntax, this name can contain any ASCII
+ *    characters, except NULL or white space. The leading \ and
+ *    trailing ' ' of escaped names in Verilog source are not part of
+ *    the name, so not included here.
  *
  * ivl_signal_attr
  *    Icarus Verilog supports attaching attributes to signals, with
@@ -913,6 +952,8 @@ extern ivl_nexus_t ivl_signal_pin(ivl_signal_t net, unsigned idx);
 extern unsigned    ivl_signal_pins(ivl_signal_t net);
 extern ivl_signal_port_t ivl_signal_port(ivl_signal_t net);
 extern int         ivl_signal_signed(ivl_signal_t net);
+extern int         ivl_signal_integer(ivl_signal_t net);
+extern int         ivl_signal_local(ivl_signal_t net);
 extern ivl_signal_type_t ivl_signal_type(ivl_signal_t net);
 extern const char* ivl_signal_name(ivl_signal_t net);
 extern const char* ivl_signal_basename(ivl_signal_t net);
@@ -929,7 +970,7 @@ extern ivl_attribute_t ivl_signal_attr_val(ivl_signal_t net, unsigned idx);
  * may be a compound statement.)
  *
  * The ivl_process_type function gets the type of the process,
- * an "inital" or "always" statement.
+ * an "initial" or "always" statement.
  *
  * A process is placed in a scope. The statement within the process
  * operates within the scope of the process unless there are calls
@@ -958,7 +999,7 @@ extern ivl_attribute_t ivl_process_attr_val(ivl_process_t net, unsigned idx);
  *
  * The ivl_statement_type() function returns the type code for the
  * statement. This is the major type, and implies which of the later
- * functions are applicable to the statemnt.
+ * functions are applicable to the statement.
  */
 extern ivl_statement_type_t ivl_statement_type(ivl_statement_t net);
 
@@ -1050,6 +1091,40 @@ _END_DECL
 
 /*
  * $Log: ivl_target.h,v $
+ * Revision 1.108  2002/10/23 01:47:17  steve
+ *  Fix synth2 handling of aset/aclr signals where
+ *  flip-flops are split by begin-end blocks.
+ *
+ * Revision 1.107  2002/09/26 03:18:04  steve
+ *  Generate vvp code for asynch set/reset of NetFF.
+ *
+ * Revision 1.106  2002/09/12 15:49:43  steve
+ *  Add support for binary nand operator.
+ *
+ * Revision 1.105  2002/08/24 05:03:40  steve
+ *  Missing declaration of ivl_memory_scope.
+ *
+ * Revision 1.104  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.103  2002/08/05 04:18:45  steve
+ *  Store only the base name of memories.
+ *
+ * Revision 1.102  2002/08/04 18:28:14  steve
+ *  Do not use hierarchical names of memories to
+ *  generate vvp labels. -tdll target does not
+ *  used hierarchical name string to look up the
+ *  memory objects in the design.
+ *
+ * Revision 1.101  2002/07/05 21:26:17  steve
+ *  Avoid emitting to vvp local net symbols.
+ *
+ * Revision 1.100  2002/06/21 04:59:35  steve
+ *  Carry integerness throughout the compilation.
+ *
+ * Revision 1.99  2002/06/11 03:34:33  steve
+ *  Spelling patch (Larry Doolittle)
+ *
  * Revision 1.98  2002/05/27 00:08:45  steve
  *  Support carrying the scope of named begin-end
  *  blocks down to the code generator, and have

ivl_target.txt

@@ -2,7 +2,7 @@
 Icarus Verilog LOADABLE TARGET API (ivl_target)
 
   Copyright 2002 Stephen Williams <[email protected]>
-  $Id: ivl_target.txt,v 1.2 2002/03/17 19:31:17 steve Exp $
+  $Id: ivl_target.txt,v 1.3 2002/06/11 03:34:33 steve Exp $
 
 
 The ivl_target API is the interface available to modules that the
@@ -12,7 +12,7 @@ for code generators that are intended to write netlist files or
 executable programs.
 
 The functions and types of the API are summarized in the ivl_target.h
-header file. This ducument describes how the functions and types of
+header file. This document describes how the functions and types of
 the API are used to access and interpret the netlist of the design.
 
 
@@ -40,6 +40,9 @@ There are ivl_lpm_size() input ports, each with the width
 ivl_lpm_data2_width(). The actual nexus is indexed by ivl_lpm_data2().
 
 $Log: ivl_target.txt,v $
+Revision 1.3  2002/06/11 03:34:33  steve
+ Spelling patch (Larry Doolittle)
+
 Revision 1.2  2002/03/17 19:31:17  steve
  Add API to support user defined function.
 

ivlpp/globals.h

@@ -18,8 +18,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: globals.h,v 1.6 2002/04/04 05:26:13 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: globals.h,v 1.7 2002/08/12 01:35:02 steve Exp $"
 #endif
 
 # include  <stdio.h>
@@ -44,6 +44,9 @@ extern int yyparse();
 
 /*
  * $Log: globals.h,v $
+ * Revision 1.7  2002/08/12 01:35:02  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.6  2002/04/04 05:26:13  steve
  *  Add dependency generation.
  *

ivlpp/lexor.lex

@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: lexor.lex,v 1.32 2002/04/04 05:26:13 steve Exp $"
+#ident "$Id: lexor.lex,v 1.36 2002/11/08 00:04:16 steve Exp $"
 #endif
 
 # include "config.h"
@@ -170,7 +170,7 @@ W [ \t\b\f]+
      directive and the name, go into PPDEFINE mode and prepare to
      collect the defined value. */
 
-`define{W}[a-zA-Z_][a-zA-Z0-9_]*{W}? { yy_push_state(PPDEFINE); def_start(); }
+`define{W}[a-zA-Z_][a-zA-Z0-9_$]*{W}? { yy_push_state(PPDEFINE); def_start(); }
 
 <PPDEFINE>.* {
       do_define();
@@ -194,7 +194,7 @@ W [ \t\b\f]+
       yy_pop_state();
   }
 
-`undef{W}[a-zA-Z_][a-zA-Z0-9_]*{W}?.* { def_undefine(); }
+`undef{W}[a-zA-Z_][a-zA-Z0-9_$]*{W}?.* { def_undefine(); }
 
 
   /* Detect conditional compilation directives, and parse them. If I
@@ -206,7 +206,7 @@ W [ \t\b\f]+
      condition that stacks on top of the IFDEF_FALSE so that output is
      not accidentally turned on within nested ifdefs. */
 
-^{W}?`ifdef{W}[a-zA-Z_][a-zA-Z0-9_]* {
+`ifdef{W}[a-zA-Z_][a-zA-Z0-9_$]* {
       char*name = strchr(yytext, '`');
       assert(name);
       name += 6;
@@ -219,7 +219,7 @@ W [ \t\b\f]+
       }
   }
 
-^{W}?`ifndef{W}[a-zA-Z_][a-zA-Z0-9_]* {
+`ifndef{W}[a-zA-Z_][a-zA-Z0-9_$]* {
       char*name = strchr(yytext, '`');
       assert(name);
       name += 7;
@@ -232,22 +232,23 @@ W [ \t\b\f]+
       }
   }
 
-<IFDEF_FALSE,IFDEF_SUPR>^{W}?`ifdef{W}.* { yy_push_state(IFDEF_SUPR); }
-<IFDEF_FALSE,IFDEF_SUPR>^{W}?`ifndef{W}.* { yy_push_state(IFDEF_SUPR); }
+<IFDEF_FALSE,IFDEF_SUPR>`ifdef{W} { yy_push_state(IFDEF_SUPR); }
+<IFDEF_FALSE,IFDEF_SUPR>`ifndef{W} { yy_push_state(IFDEF_SUPR); }
 
-<IFDEF_TRUE>{W}?`else  { BEGIN(IFDEF_FALSE); }
-<IFDEF_FALSE>{W}?`else { BEGIN(IFDEF_TRUE); }
-<IFDEF_SUPR>{W}?`else  {  }
+<IFDEF_TRUE>`else  { BEGIN(IFDEF_FALSE); }
+<IFDEF_FALSE>`else { BEGIN(IFDEF_TRUE); }
+<IFDEF_SUPR>`else  {  }
 
+<IFDEF_FALSE,IFDEF_SUPR>"//".* {  }
 <IFDEF_FALSE,IFDEF_SUPR>.  {  }
 <IFDEF_FALSE,IFDEF_SUPR>\n { istack->lineno += 1; fputc('\n', yyout); }
 
-<IFDEF_FALSE,IFDEF_TRUE,IFDEF_SUPR>^{W}?`endif {
+<IFDEF_FALSE,IFDEF_TRUE,IFDEF_SUPR>`endif {
       yy_pop_state();
   }
 
   /* This pattern notices macros and arranges for them to be replaced. */
-`[a-zA-Z][a-zA-Z0-9_]* { def_match(); }
+`[a-zA-Z][a-zA-Z0-9_$]* { def_match(); }
 
   /* Any text that is not a directive just gets passed through to the
      output. Very easy. */

ivlpp/main.c

@@ -16,8 +16,8 @@ const char COPYRIGHT[] =
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: main.c,v 1.15 2002/04/04 05:26:13 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: main.c,v 1.16 2002/08/12 01:35:02 steve Exp $"
 #endif
 
 # include "config.h"
@@ -288,6 +288,9 @@ int main(int argc, char*argv[])
 
 /*
  * $Log: main.c,v $
+ * Revision 1.16  2002/08/12 01:35:02  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.15  2002/04/04 05:26:13  steve
  *  Add dependency generation.
  *

lexor.lex

@@ -19,14 +19,14 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: lexor.lex,v 1.72 2002/05/23 03:08:51 steve Exp $"
+#ident "$Id: lexor.lex,v 1.74 2002/12/04 02:07:00 steve Exp $"
 #endif
 
 # include "config.h"
 
       //# define YYSTYPE lexval
 
-# include  <iostream.h>
+# include  <iostream>
 # include  "compiler.h"
 # include  "parse_misc.h"
 # include  "parse_api.h"
@@ -375,7 +375,7 @@ W [ \t\b\f\r]+
       if (isgraph(yytext[0]))
 	    cerr << yytext[0];
       else
-	    cerr << (unsigned)yytext[0];
+	    cerr << "hex " << hex << (0xffU & ((unsigned) (yytext[0])));
 
       cerr << ")" << endl; }
 

lexor_keyword.gperf

@@ -82,7 +82,7 @@ rpmos,		K_rpmos
 rtran,		K_rtran
 rtranif0,	K_rtranif0
 rtranif1,	K_rtranif1
-scalered,	K_scalered
+scalared,	K_scalared
 signed,		K_signed
 small,		K_small
 specify,	K_specify

lexor_keyword.h

@@ -18,14 +18,17 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: lexor_keyword.h,v 1.1 2000/03/12 17:09:41 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: lexor_keyword.h,v 1.2 2002/08/12 01:34:59 steve Exp $"
 #endif
 
 extern int lexor_keyword_code (const char*str, unsigned len);
 
 /*
  * $Log: lexor_keyword.h,v $
+ * Revision 1.2  2002/08/12 01:34:59  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.1  2000/03/12 17:09:41  steve
  *  Support localparam.
  *

libveriuser/Makefile.in

@@ -16,7 +16,7 @@
 #    59 Temple Place - Suite 330
 #    Boston, MA 02111-1307, USA
 #
-#ident "$Id: Makefile.in,v 1.10 2002/06/02 19:03:29 steve Exp $"
+#ident "$Id: Makefile.in,v 1.14 2002/06/11 15:19:12 steve Exp $"
 #
 #
 SHELL = /bin/sh
@@ -44,10 +44,13 @@ CFLAGS = @CFLAGS@
 LDFLAGS = @LDFLAGS@
 STRIP = @STRIP@
 
-A = a_close.o a_handle_tfarg.o a_initialize.o a_next_topmod.o \
-a_product_version.o
-O = finish.o getinstance.o getsimtime.o io_print.o mc_scan_plusargs.o \
-nump.o veriusertfs.o $A
+A = a_close.o a_fetch_argc.o a_fetch_argv.o a_fetch_fullname.o \
+a_fetch_tfarg.o a_handle_tfarg.o \
+a_initialize.o a_next_topmod.o a_object_of_type.o a_product_version.o \
+a_set_value.o a_version.o
+O = asynch.o finish.o getcstringp.o getinstance.o getlongp.o \
+getp.o getsimtime.o io_print.o mc_scan_plusargs.o nump.o putlongp.o \
+putp.o veriusertfs.o $A
 
 all: libveriuser.a
 

libveriuser/a_close.c

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT)
-#ident "$Id: a_close.c,v 1.1 2002/05/23 03:46:42 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: a_close.c,v 1.2 2002/08/12 01:35:02 steve Exp $"
 #endif
 
 # include  <acc_user.h>
@@ -26,6 +26,9 @@ void acc_close(void) { }
 
 /*
  * $Log: a_close.c,v $
+ * Revision 1.2  2002/08/12 01:35:02  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.1  2002/05/23 03:46:42  steve
  *  Add the acc_user.h header file.
  *

libveriuser/a_fetch_argc.c

@@ -0,0 +1,49 @@
+/* vi:sw=6
+ * Copyright (c) 2002 Michael Ruff (mruff at chiaro.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: a_fetch_argc.c,v 1.2 2002/08/12 01:35:02 steve Exp $"
+#endif
+
+# include  <vpi_user.h>
+# include  <veriuser.h>
+
+/*
+ * acc_fetch_argc implemented using VPI interface
+ */
+int acc_fetch_argc(void)
+{
+      s_vpi_vlog_info vpi_vlog_info;
+
+      /* get command line info */
+      if (! vpi_get_vlog_info(&vpi_vlog_info))
+	    return 0;
+
+      /* return argc */
+      return vpi_vlog_info.argc;
+}
+
+/*
+ * $Log: a_fetch_argc.c,v $
+ * Revision 1.2  2002/08/12 01:35:02  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.1  2002/06/11 15:19:12  steve
+ *  Add acc_fetch_argc/argv/version (mruff)
+ *
+ */

libveriuser/a_fetch_argv.c

@@ -0,0 +1,49 @@
+/* vi:sw=6
+ * Copyright (c) 2002 Michael Ruff (mruff at chiaro.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: a_fetch_argv.c,v 1.2 2002/08/12 01:35:02 steve Exp $"
+#endif
+
+# include  <vpi_user.h>
+# include  <veriuser.h>
+
+/*
+ * acc_fetch_argv implemented using VPI interface
+ */
+char **acc_fetch_argv(void)
+{
+      s_vpi_vlog_info vpi_vlog_info;
+
+      /* get command line info */
+      if (! vpi_get_vlog_info(&vpi_vlog_info))
+	    return (char **)0;
+
+      /* return argc */
+      return vpi_vlog_info.argv;
+}
+
+/*
+ * $Log: a_fetch_argv.c,v $
+ * Revision 1.2  2002/08/12 01:35:02  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.1  2002/06/11 15:19:12  steve
+ *  Add acc_fetch_argc/argv/version (mruff)
+ *
+ */

libveriuser/a_fetch_fullname.c

@@ -0,0 +1,42 @@
+/* vi:sw=6
+ * Copyright (c) 2002 Michael Ruff (mruff at chiaro.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: a_fetch_fullname.c,v 1.2 2002/08/12 01:35:02 steve Exp $"
+#endif
+
+#include  <vpi_user.h>
+#include  <acc_user.h>
+
+/*
+ * acc_fetch_fullname implemented using VPI interface
+ */
+char *acc_fetch_fullname(handle object)
+{
+      return vpi_get_str(vpiFullName, object);
+}
+
+/*
+ * $Log: a_fetch_fullname.c,v $
+ * Revision 1.2  2002/08/12 01:35:02  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.1  2002/06/07 02:58:58  steve
+ *  Add a bunch of acc/tf functions. (mruff)
+ *
+ */

libveriuser/a_fetch_tfarg.c

@@ -0,0 +1,83 @@
+/* vi:sw=6
+ * Copyright (c) 2002 Michael Ruff (mruff at chiaro.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: a_fetch_tfarg.c,v 1.2 2002/08/12 01:35:02 steve Exp $"
+#endif
+
+#include  <vpi_user.h>
+#include  <acc_user.h>
+
+/*
+ * acc_fetch_tfarg routines implemented using VPI interface
+ */
+int acc_fetch_tfarg_int(int n)
+{
+      vpiHandle sys_h, sys_i, arg_h = 0;
+      s_vpi_value value;
+      int rtn;
+
+      sys_h = vpi_handle(vpiSysTfCall, 0);
+      sys_i = vpi_iterate(vpiArgument, sys_h);
+
+      /* scan to nth argument */
+      while (n > 0 && (arg_h = vpi_scan(sys_i))) n--;
+
+      if (arg_h) {
+	    value.format=vpiIntVal;
+	    vpi_get_value(arg_h, &value);
+	    rtn = value.value.integer; 
+      } else {
+	    rtn = 0;
+      }
+
+      return rtn;
+}
+
+char *acc_fetch_tfarg_str(int n)
+{
+      vpiHandle sys_h, sys_i, arg_h = 0;
+      s_vpi_value value;
+      char *rtn;
+
+      sys_h = vpi_handle(vpiSysTfCall, 0);
+      sys_i = vpi_iterate(vpiArgument, sys_h);
+
+      /* scan to nth argument */
+      while (n > 0 && (arg_h = vpi_scan(sys_i))) n--;
+
+      if (arg_h) {
+	    value.format=vpiStringVal;
+	    vpi_get_value(arg_h, &value);
+	    rtn = value.value.str; 
+      } else {
+	    rtn = (char *) 0;
+      }
+
+      return rtn;
+}
+
+/*
+ * $Log: a_fetch_tfarg.c,v $
+ * Revision 1.2  2002/08/12 01:35:02  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.1  2002/06/07 02:58:58  steve
+ *  Add a bunch of acc/tf functions. (mruff)
+ *
+ */

libveriuser/a_handle_tfarg.c

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT)
-#ident "$Id: a_handle_tfarg.c,v 1.1 2002/06/02 19:03:58 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: a_handle_tfarg.c,v 1.2 2002/08/12 01:35:02 steve Exp $"
 #endif
 
 #include  <acc_user.h>
@@ -48,6 +48,9 @@ handle acc_handle_tfarg(int n)
 
 /*
  * $Log: a_handle_tfarg.c,v $
+ * Revision 1.2  2002/08/12 01:35:02  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.1  2002/06/02 19:03:58  steve
  *  Add acc_handle_tfarg and acc_next_topmode
  *

libveriuser/a_initialize.c

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT)
-#ident "$Id: a_initialize.c,v 1.1 2002/05/23 03:46:42 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: a_initialize.c,v 1.2 2002/08/12 01:35:02 steve Exp $"
 #endif
 
 # include  <acc_user.h>
@@ -33,6 +33,9 @@ int acc_initialize()
 
 /*
  * $Log: a_initialize.c,v $
+ * Revision 1.2  2002/08/12 01:35:02  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.1  2002/05/23 03:46:42  steve
  *  Add the acc_user.h header file.
  *

libveriuser/a_next_topmod.c

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT)
-#ident "$Id: a_next_topmod.c,v 1.1 2002/06/02 19:03:58 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: a_next_topmod.c,v 1.2 2002/08/12 01:35:02 steve Exp $"
 #endif
 
 #include  <assert.h>
@@ -49,6 +49,9 @@ handle acc_next_topmod(handle prev_topmod)
 
 /*
  * $Log: a_next_topmod.c,v $
+ * Revision 1.2  2002/08/12 01:35:02  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.1  2002/06/02 19:03:58  steve
  *  Add acc_handle_tfarg and acc_next_topmode
  *

libveriuser/a_object_of_type.c

@@ -0,0 +1,68 @@
+/* vi:sw=6
+ * Copyright (c) 2002 Michael Ruff (mruff at chiaro.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: a_object_of_type.c,v 1.2 2002/08/12 01:35:02 steve Exp $"
+#endif
+
+#include  <assert.h>
+#include  <vpi_user.h>
+#include  <acc_user.h>
+
+/*
+ * acc_object_of_type implemented using VPI interface
+ */
+int acc_object_of_type(handle object, int type)
+{
+      int vtype;
+      int rtn = 0;	/* false */
+
+      /* get VPI type of object */
+      vtype = vpi_get(vpiType, object);
+
+      switch (type) {
+	    case accScope:
+		  if (vtype == vpiModule || vtype == vpiNamedBegin ||
+		      vtype == vpiNamedFork || vtype == vpiTask ||
+		      vtype == vpiFunction) rtn = 1;
+		  break;
+	    case accScalar:
+		  if (vtype == vpiReg || vtype == vpiNet)
+			rtn = vpi_get(vpiSize, object) == 1;
+		  break;
+	    case accVector:
+		  if (vtype == vpiReg || vtype == vpiNet)
+			rtn = vpi_get(vpiSize, object) > 1;
+		  break;
+	    default:
+		  vpi_printf("acc_object_of_type: Unknown type %d\n", type);
+		  assert(0);
+      }
+
+      return rtn;
+}
+
+/*
+ * $Log: a_object_of_type.c,v $
+ * Revision 1.2  2002/08/12 01:35:02  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.1  2002/06/07 02:58:58  steve
+ *  Add a bunch of acc/tf functions. (mruff)
+ *
+ */

libveriuser/a_product_version.c

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT)
-#ident "$Id: a_product_version.c,v 1.1 2002/05/30 02:06:05 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: a_product_version.c,v 1.2 2002/08/12 01:35:02 steve Exp $"
 #endif
 
 # include  <vpi_user.h>
@@ -34,6 +34,9 @@ char *acc_product_version(void)
 
 /*
  * $Log: a_product_version.c,v $
+ * Revision 1.2  2002/08/12 01:35:02  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.1  2002/05/30 02:06:05  steve
  *  Implement acc_product_version.
  *

libveriuser/a_set_value.c

@@ -0,0 +1,121 @@
+/* vi:sw=6
+ * Copyright (c) 2002 Michael Ruff (mruff at chiaro.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: a_set_value.c,v 1.2 2002/08/12 01:35:02 steve Exp $"
+#endif
+
+#include  <assert.h>
+#include  <acc_user.h>
+#include  <vpi_user.h>
+
+/*
+ * acc_set_value implemented using VPI interface
+ */
+int acc_set_value(handle object, p_setval_value value, p_setval_delay delay)
+{
+      s_vpi_time when, *whenp;
+      s_vpi_value val;
+      int flags;
+
+      assert(delay);
+      assert(value);
+      assert(object);
+
+      /* map setval_delay.model to flags */
+      switch (delay->model) {
+	    case accNoDelay:            flags = vpiNoDelay; break;
+	    case accInertialDelay:      flags = vpiInertialDelay; break;
+	    case accTransportDelay:     flags = vpiTransportDelay; break;
+	    case accPureTransportDelay: flags = vpiPureTransportDelay; break;
+	    case accForceFlag:          flags = vpiForceFlag; break;
+	    case accReleaseFlag:        flags = vpiReleaseFlag; break;
+	    default: assert(0); break;
+      }
+
+      /* map acc_time to vpi_time */
+      if (delay->model != accNoDelay) {
+	    switch (delay->time.type) {
+		  case accSimTime:  when.type = vpiSimTime; break;
+		  case accRealTime: when.type = vpiScaledRealTime; break;
+		  default: assert(0); break;
+	    }
+	    when.high = delay->time.high;
+	    when.low = delay->time.low;
+	    when.real = delay->time.real;
+
+	    whenp = &when;
+      } else
+	    whenp = 0;
+
+      /* map setval_value to vpi_value and flags */
+      switch (value->format) {
+	    case accBinStrVal:
+		  val.format = vpiBinStrVal;
+		  val.value.str = value->value.str;
+		  break;
+	    case accOctStrVal:
+		  val.format = vpiOctStrVal;
+		  val.value.str = value->value.str;
+		  break;
+	    case accDecStrVal:
+		  val.format = vpiDecStrVal;
+		  val.value.str = value->value.str;
+		  break;
+	    case accHexStrVal:
+		  val.format = vpiHexStrVal;
+		  val.value.str = value->value.str;
+		  break;
+	    case accScalarVal:
+		  val.format = vpiScalarVal;
+		  val.value.scalar = value->value.scalar;
+		  break;
+	    case accIntVal:
+		  val.format = vpiIntVal;
+		  val.value.integer = value->value.integer;
+		  break;
+	    case accRealVal:
+		  val.format = vpiRealVal;
+		  val.value.real = value->value.real;
+		  break;
+	    case accStringVal:
+		  val.format = vpiStringVal;
+		  val.value.str = value->value.str;
+		  break;
+	    case accVectorVal:
+		  val.format = vpiVectorVal;
+		  val.value.vector = (p_vpi_vecval)value->value.vector;
+		  break;
+	    default: assert(0); break;
+      }
+
+      /* put value */
+      vpi_put_value(object, &val, whenp, flags);
+
+      return 1;
+}
+
+/*
+ * $Log: a_set_value.c,v $
+ * Revision 1.2  2002/08/12 01:35:02  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.1  2002/06/07 02:58:59  steve
+ *  Add a bunch of acc/tf functions. (mruff)
+ *
+ */

libveriuser/a_version.c

@@ -0,0 +1,43 @@
+/* vi:sw=6
+ * Copyright (c) 2002 Michael Ruff (mruff at chiaro.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: a_version.c,v 1.2 2002/08/12 01:35:02 steve Exp $"
+#endif
+
+# include  <vpi_user.h>
+# include  <acc_user.h>
+
+char *acc_version(void)
+{
+      s_vpi_vlog_info info;
+
+      if (! vpi_get_vlog_info(&info)) return (char *)0;
+
+      return info.version;
+}
+
+/*
+ * $Log: a_version.c,v $
+ * Revision 1.2  2002/08/12 01:35:02  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.1  2002/06/11 15:19:12  steve
+ *  Add acc_fetch_argc/argv/version (mruff)
+ *
+ */

libveriuser/asynch.c

@@ -0,0 +1,51 @@
+/* vi:sw=6
+ * Copyright (c) 2002 Michael Ruff (mruff at chiaro.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: asynch.c,v 1.2 2002/08/12 01:35:02 steve Exp $"
+#endif
+
+# include  <veriuser.h>
+
+/* Enables async misctf callbacks */
+int async_misctf_enable;
+
+/*
+ * Implement misctf async enable
+ */
+int tf_asynchon(void)
+{
+      async_misctf_enable = 1;
+      return 0;
+}
+
+int tf_asynchoff(void)
+{
+      async_misctf_enable = 0;
+      return 0;
+}
+
+/*
+ * $Log: asynch.c,v $
+ * Revision 1.2  2002/08/12 01:35:02  steve
+ *  conditional ident string using autoconfig.
+ *
+ * Revision 1.1  2002/06/04 01:40:03  steve
+ *  Add asynchon and asynchoff
+ *
+ */

libveriuser/finish.c

@@ -16,8 +16,8 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#if !defined(WINNT)
-#ident "$Id: finish.c,v 1.1 2002/05/19 05:21:00 steve Exp $"
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: finish.c,v 1.2 2002/08/12 01:35:02 steve Exp $"
 #endif
 
 # include  <vpi_user.h>
@@ -41,6 +41,9 @@ int tf_dostop(void)
 
 /*
  * $Log: finish.c,v $
+ * Revision 1.2  2002/08/12 01:35:02  steve
+ *  conditional ident string using autoconfig.
+ *
  * Revision 1.1  2002/05/19 05:21:00  steve
  *  Start the libveriuser library.
  *