Change the VPI call process so that loaded .vpi modules
use a function table instead of implicit binding.
This commit is contained in:
steve
parent
e28b7f06c5
commit
7009dc8d9b
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@ -1,7 +1,7 @@
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/*
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* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
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*
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* $Id: README.txt,v 1.27 2001/06/07 03:09:03 steve Exp $
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* $Id: README.txt,v 1.28 2001/06/15 03:28:30 steve Exp $
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*/
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VVP SIMULATION ENGINE
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@ -296,28 +296,44 @@ data bus, bit 0 is the lsb of the first word, bit 20 is the lsb of the
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second word.
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Structural read access is implemented in terms of address and data
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ports. An address port is the concatinations of the smallest number of
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address bits required to express each address range. The addresses
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applied to the address port are expected to be withing the ranges
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specified.
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ports. The addresses applied to the address port are expected to be
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withing the ranges specified, not based at zero.
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An port is a vector of functors that is wide enough to accept all
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address bits and at least as wide as the requested subset of the data
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port.
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A read port is a vector of functors that is wide enough to accept all
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provided address bits and at least as wide as the requested subset of
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the data port.
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<label> .mem/port <memid>, <msb>,<lsb>, <symbols_list> ;
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<label> .mem/port <memid>, <msb>,<lsb>, <aw>, <addr_bits> ;
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<label> identifies the vector of output functors, to allow connections
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to the data output. <memid> is the label of the memory. <msb>,<lsb>
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select a part of the data width. These are not relative to the data
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port range defined for the memory. The LSB of the data word if here
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port range defined for the memory. The LSB of the data word is here
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referred to as 0, regardless to the range specified in the memory
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definition. The <symbols_list> connects to the address inputs of this
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port.
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definition. <addr_bits> is a list of symbols, which connect to the
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address inputs of this port. There are <aw> address bits (<aw> may
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become a list of numbers, when multi-index memory ports become
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supported).
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Any address change, or any change in the addressed memory contents is
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imediately propagated to the port outputs.
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A write port is a superset of a read port. It is a vector of functors
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that is wide enough to accept the address bits, an event input, a
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write enable input, and the data inputs.
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<label> .mem/port <memid>, <msb>,<lsb>, <aw>, <addr_bits>,
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<event>, <we>, <data> ;
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<event> is an event functor that triggers a write, if the <we> input
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is true. <data> is a list of symbols that connect to the data input
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port. For asynchronous transparent write operation, connect
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<event> to C<z>, the RAM will transparently follow any changes on
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address and data lines, while <we> is true.
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There is no Verilog construct that calls for a structural write port
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to a memory, but synthesis may ask for lpm_ram_d[pq] objects.
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To initialize a memory, use:
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.mem/init <memid>[<start>],
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: compile.cc,v 1.74 2001/06/10 17:12:51 steve Exp $"
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#ident "$Id: compile.cc,v 1.75 2001/06/15 03:28:31 steve Exp $"
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#endif
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# include "arith.h"
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@ -612,6 +612,7 @@ void compile_memory(char *label, char *name, int msb, int lsb,
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void compile_memory_port(char *label, char *memid,
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unsigned msb, unsigned lsb,
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unsigned naddr,
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unsigned argc, struct symb_s *argv)
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{
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vvp_memory_t mem = memory_find(memid);
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@ -624,21 +625,25 @@ void compile_memory_port(char *label, char *memid,
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assert (msb < memory_data_width(mem));
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unsigned nbits = msb-lsb+1;
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unsigned awidth = memory_addr_width(mem);
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unsigned nfun = (awidth + 3)/4;
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bool writable = argc >= (naddr + 2 + nbits);
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unsigned nfun = naddr;
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if (writable)
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nfun += 2 + nbits;
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assert(nfun == argc);
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nfun = (nfun+3)/4;
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if (nfun < nbits)
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nfun = nbits;
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vvp_ipoint_t ix = functor_allocate(nfun);
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assert(argc == awidth);
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define_functor_symbol(label, ix);
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free(label);
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inputs_connect(ix, argc, argv);
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free(argv);
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memory_port_new(mem, ix, nbits, lsb);
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memory_port_new(mem, ix, nbits, lsb, naddr, writable);
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}
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void compile_memory_init(char *memid, unsigned i, unsigned char val)
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@ -1335,6 +1340,10 @@ vvp_ipoint_t debug_lookup_functor(const char*name)
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/*
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* $Log: compile.cc,v $
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* Revision 1.75 2001/06/15 03:28:31 steve
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* Change the VPI call process so that loaded .vpi modules
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* use a function table instead of implicit binding.
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*
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* Revision 1.74 2001/06/10 17:12:51 steve
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* Instructions can forward reference functors.
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*
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: compile.h,v 1.25 2001/06/07 03:09:03 steve Exp $"
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#ident "$Id: compile.h,v 1.26 2001/06/15 03:28:31 steve Exp $"
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#endif
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# include <stdio.h>
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@ -108,6 +108,7 @@ extern void compile_memory(char *label, char *name, int lsb, int msb,
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extern void compile_memory_port(char *label, char *memid,
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unsigned lsb, unsigned msb,
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unsigned naddr,
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unsigned argc, struct symb_s *argv);
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extern void compile_memory_init(char *memid, unsigned idx, unsigned char val);
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@ -190,6 +191,10 @@ extern void compile_net(char*label, char*name,
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/*
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* $Log: compile.h,v $
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* Revision 1.26 2001/06/15 03:28:31 steve
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* Change the VPI call process so that loaded .vpi modules
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* use a function table instead of implicit binding.
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*
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* Revision 1.25 2001/06/07 03:09:03 steve
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* Implement .arith/sub subtraction.
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*
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@ -19,7 +19,7 @@
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; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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; This sample demonstrates memory, also including index register
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; arithmetic.
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; arithmetic. And a memory write port
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main .scope "example";
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@ -36,12 +36,20 @@ memory .mem "memory", 8,2, 27,5 ;
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;;; An address/data port.
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;
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; reg [4:0] a;
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; reg we;
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; event wclk;
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; reg [5:0] di;
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; wire [5:0] d = memory[a][8:3];
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; reg [6:0] m;
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a .var "a", 4,0;
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we .var "we", 0,0;
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wclk .event "wclk";
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di .var "di", 5,0;
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d .net "d", 5,0, mem[0],mem[1],mem[2],mem[3],mem[4],mem[5];
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mem .mem/port memory, 6,1, a[0],a[1],a[2],a[3],a[4];
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mem .mem/port memory, 6,1,
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5, a[0],a[1],a[2],a[3],a[4],
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wclk, we, di[0],di[1],di[2],di[3],di[4],di[5];
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m .var "m", 6,0;
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;;; The data port mem[] does not connect to the LSB of the memory.
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@ -76,6 +84,7 @@ m .var "m", 6,0;
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; always
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; begin
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; #5 $display("a:%b d:%b", a, d);
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; -> wclk;
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; #5 a <= a+1;
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; end
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@ -85,6 +94,8 @@ always ;
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%vpi_call "$display", "a:%b d:%b", a, d;
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%set wclk, 0;
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%delay 5;
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%load 10, a[0];
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@ -109,8 +120,18 @@ always ;
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;
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; initial
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; begin
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; we = 0;
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; di = 'b 10zx10;
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; a = 0;
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; #320;
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; #220;
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; $readmemh("memory.hex", memory);
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; #30;
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; we = 1;
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; #5;
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; $display("write to a=%b", a);
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; #5;
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; we = 0;
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; #60;
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; memory[23] <= 'b 1xz01;
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; #320;
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; m = memory[9];
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@ -121,6 +142,13 @@ always ;
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.scope main;
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initial ;
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%set we, 0;
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%set di[0], 0;
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%set di[1], 1;
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%set di[2], 2;
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%set di[3], 3;
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%set di[4], 0;
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%set di[5], 1;
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%set a[0], 0;
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%set a[1], 0;
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%set a[2], 0;
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%delay 220;
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%vpi_call "$readmemh", "memory.hex", memory;
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%delay 100;
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%delay 30;
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%set we, 1;
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%delay 5;
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%vpi_call "$display", "write to a=%b", a;
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%delay 5;
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%set we, 0;
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%delay 60;
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;;; Memories are indexed by index register 3. The index register
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;;; points to the bit position in the memory. Each memory word
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140
vvp/memory.cc
140
vvp/memory.cc
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@ -18,7 +18,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: memory.cc,v 1.3 2001/05/08 23:59:33 steve Exp $"
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#ident "$Id: memory.cc,v 1.4 2001/06/15 03:28:31 steve Exp $"
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#endif
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#include "memory.h"
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@ -37,7 +37,6 @@ struct vvp_memory_s
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// Address port properties:
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unsigned size; // total number of data words
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unsigned awidth; // total number of address bits
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unsigned a_idxs; // number of address indices
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vvp_memory_index_t a_idx; // vector of address indices
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@ -55,18 +54,12 @@ unsigned memory_data_width(vvp_memory_t mem)
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return mem->width;
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}
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unsigned memory_addr_width(vvp_memory_t mem)
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{
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return mem->awidth;
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}
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#define VVP_MEMORY_NO_ADDR ((int)0x80000000)
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struct vvp_memory_index_s
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{
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int first; // first memory address
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unsigned size; // number of valid addresses
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unsigned awidth; // width of address port
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};
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struct vvp_memory_port_s : public vvp_fobj_s
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@ -76,11 +69,16 @@ struct vvp_memory_port_s : public vvp_fobj_s
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vvp_memory_t mem;
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vvp_ipoint_t ix;
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unsigned naddr;
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vvp_memory_port_t next;
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int cur_addr;
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vvp_memory_bits_t cur_bits;
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int bitoff;
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int nbits;
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unsigned bitoff;
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unsigned nbits;
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bool writable;
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};
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@ -142,7 +140,6 @@ void memory_new(vvp_memory_t mem, char *name, int msb, int lsb,
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assert(mem->a_idxs);
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mem->size = 1;
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mem->awidth = 0;
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for (unsigned i=0; i < mem->a_idxs; i++)
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{
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vvp_memory_index_t x = mem->a_idx + i;
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@ -156,19 +153,6 @@ void memory_new(vvp_memory_t mem, char *name, int msb, int lsb,
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x->size = lsw - msw + 1;
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x->first = msw;
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}
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int m = lsw ^ msw;
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x->awidth = 0;
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if (m < 0)
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{
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if (lsw < 0)
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m = ~lsw | msw;
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else
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m = lsw | ~msw;
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x->awidth++;
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}
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for (int c=1; c<m; c<<=1)
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x->awidth ++;
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mem->awidth += x->awidth;
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mem->size *= x->size;
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}
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@ -182,19 +166,25 @@ void memory_new(vvp_memory_t mem, char *name, int msb, int lsb,
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void memory_port_new(vvp_memory_t mem, vvp_ipoint_t ix,
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unsigned nbits, unsigned bitoff)
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unsigned nbits, unsigned bitoff,
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unsigned naddr, bool writable)
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{
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vvp_memory_port_t a = new struct vvp_memory_port_s;
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a->mem = mem;
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a->ix = ix;
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a->naddr = naddr;
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a->writable = writable;
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a->nbits = nbits;
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a->bitoff = bitoff;
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a->next = mem->addr_root;
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a->mem->addr_root = a;
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unsigned nfun = (a->mem->awidth+3)/4;
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unsigned nfun = naddr;
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if (writable)
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nfun += 2 + nbits;
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nfun = (nfun+3)/4;
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if (nfun < nbits)
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nfun = nbits;
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@ -225,25 +215,14 @@ void memory_init_nibble(vvp_memory_t mem, unsigned idx, unsigned char val)
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inline static
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vvp_memory_bits_t get_word(vvp_memory_t mem, int addr)
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{
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if (addr == VVP_MEMORY_NO_ADDR)
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return 0x0;
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// Compute the word index into the bits array.
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unsigned waddr = 0;
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for (unsigned i = 0; i<mem->a_idxs; i++)
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{
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vvp_memory_index_t x = mem->a_idx + i;
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unsigned iwaddr = (addr - x->first) & ((1<<x->awidth) - 1);
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waddr *= x->size;
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// This fails for negative
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if (iwaddr >= x->size)
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return 0x0;
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waddr += iwaddr;
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addr >>= x->awidth;
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}
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assert(waddr < mem->size);
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assert(mem->a_idxs==1);
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unsigned waddr = addr - mem->a_idx[0].first;
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if (waddr >= mem->size)
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return 0x0;
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return mem->bits + waddr*mem->fwidth;
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}
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@ -294,7 +273,7 @@ bool update_addr_bit(vvp_memory_port_t addr, vvp_ipoint_t ip)
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{
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unsigned abit = ip - addr->ix;
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assert(abit >= 0 && abit < addr->mem->awidth);
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assert(abit >= 0 && abit < addr->naddr);
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int old = addr->cur_addr;
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@ -319,7 +298,7 @@ static
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void update_addr(vvp_memory_port_t addr)
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{
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addr->cur_addr = 2;
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for (unsigned i=0; i < addr->mem->awidth; i++)
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for (unsigned i=0; i < addr->naddr; i++)
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{
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update_addr_bit(addr, addr->ix+i);
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if (addr->cur_addr == VVP_MEMORY_NO_ADDR)
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@ -332,7 +311,7 @@ void update_data(vvp_memory_port_t data,
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vvp_memory_bits_t bits)
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{
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assert(data);
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for (int i=0; i < data->nbits; i++)
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for (unsigned i=0; i < data->nbits; i++)
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{
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vvp_ipoint_t dx = ipoint_index(data->ix, i);
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functor_t df = functor_index(dx);
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@ -345,17 +324,6 @@ void update_data(vvp_memory_port_t data,
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}
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}
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void vvp_memory_port_s::set(vvp_ipoint_t i, functor_t f, bool push)
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{
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if (update_addr_bit(this, i))
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update_data(this, cur_bits);
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}
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unsigned vvp_memory_port_s::get(vvp_ipoint_t i, functor_t f)
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{
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assert(0);
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}
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static
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void update_data_ports(vvp_memory_t mem, int addr, int bit,
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unsigned char val)
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@ -365,11 +333,10 @@ void update_data_ports(vvp_memory_t mem, int addr, int bit,
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{
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if (addr == a->cur_addr)
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{
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vvp_memory_port_t d = a; // historic
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int i = bit - d->bitoff;
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if (i >= 0 && i < d->nbits)
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unsigned i = bit - a->bitoff;
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if (i < a->nbits)
|
||||
{
|
||||
vvp_ipoint_t ix = ipoint_index(d->ix, i);
|
||||
vvp_ipoint_t ix = ipoint_index(a->ix, i);
|
||||
functor_t df = functor_index(ix);
|
||||
if (df->oval != val)
|
||||
{
|
||||
|
|
@ -382,6 +349,55 @@ void update_data_ports(vvp_memory_t mem, int addr, int bit,
|
|||
}
|
||||
}
|
||||
|
||||
static inline
|
||||
void write_event(vvp_memory_port_t p)
|
||||
{
|
||||
unsigned we = functor_get_input(p->ix + p->naddr + 1);
|
||||
if (!we)
|
||||
return;
|
||||
|
||||
for (unsigned i=0; i < p->nbits; i++)
|
||||
{
|
||||
unsigned val = functor_get_input(p->ix + p->naddr + 2 + i);
|
||||
if (set_bit(p->cur_bits, i + p->bitoff, val))
|
||||
{
|
||||
// if a write would change the memory bit, but <we> is
|
||||
// undefined (x or z), set the bit to x.
|
||||
if (we > 1)
|
||||
{
|
||||
set_bit(p->cur_bits, i + p->bitoff, 2);
|
||||
val = 2;
|
||||
}
|
||||
update_data_ports(p->mem, p->cur_addr, i + p->bitoff, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void vvp_memory_port_s::set(vvp_ipoint_t i, functor_t f, bool push)
|
||||
{
|
||||
if (i < ix+naddr)
|
||||
{
|
||||
if (update_addr_bit(this, i))
|
||||
update_data(this, cur_bits);
|
||||
}
|
||||
|
||||
// An event at ix+naddr always sets the value 0, and triggeres a write.
|
||||
// If the write event port is 3, then it's not connected, and the
|
||||
// write port is transparent, controlled by ix+naddr+1, the write enable.
|
||||
|
||||
if (i == ix+naddr
|
||||
|| (writable && functor_get_input(ix+naddr) == 3))
|
||||
{
|
||||
assert(writable);
|
||||
write_event(this);
|
||||
}
|
||||
}
|
||||
|
||||
unsigned vvp_memory_port_s::get(vvp_ipoint_t i, functor_t f)
|
||||
{
|
||||
assert(0);
|
||||
}
|
||||
|
||||
|
||||
// %set/mem
|
||||
|
||||
|
|
|
|||
11
vvp/memory.h
11
vvp/memory.h
|
|
@ -20,7 +20,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#if !defined(WINNT)
|
||||
#ident "$Id: memory.h,v 1.2 2001/05/08 23:59:33 steve Exp $"
|
||||
#ident "$Id: memory.h,v 1.3 2001/06/15 03:28:31 steve Exp $"
|
||||
#endif
|
||||
|
||||
#include "pointers.h"
|
||||
|
|
@ -38,7 +38,9 @@ typedef struct vvp_memory_index_s *vvp_memory_index_t;
|
|||
void memory_new(vvp_memory_t mem, char *name, int lsb, int msb,
|
||||
unsigned idxs, long *idx);
|
||||
void memory_port_new(vvp_memory_t mem, vvp_ipoint_t ix,
|
||||
unsigned nbits, unsigned bitoff);
|
||||
unsigned nbits, unsigned bitoff,
|
||||
unsigned naddr, bool writable);
|
||||
|
||||
void memory_init_nibble(vvp_memory_t mem, unsigned idx, unsigned char val);
|
||||
|
||||
void memory_set(vvp_memory_t mem, unsigned idx, unsigned char val);
|
||||
|
|
@ -46,7 +48,6 @@ unsigned memory_get(vvp_memory_t mem, unsigned idx);
|
|||
void schedule_memory(vvp_memory_t mem, unsigned idx,
|
||||
unsigned char val, unsigned delay);
|
||||
|
||||
unsigned memory_addr_width(vvp_memory_t mem);
|
||||
unsigned memory_size(vvp_memory_t mem);
|
||||
char *memory_name(vvp_memory_t mem);
|
||||
unsigned memory_data_width(vvp_memory_t mem);
|
||||
|
|
@ -60,6 +61,10 @@ vvp_memory_t memory_create(char *label);
|
|||
|
||||
/*
|
||||
* $Log: memory.h,v $
|
||||
* Revision 1.3 2001/06/15 03:28:31 steve
|
||||
* Change the VPI call process so that loaded .vpi modules
|
||||
* use a function table instead of implicit binding.
|
||||
*
|
||||
* Revision 1.2 2001/05/08 23:59:33 steve
|
||||
* Add ivl and vvp.tgt support for memories in
|
||||
* expressions and l-values. (Stephan Boettcher)
|
||||
|
|
|
|||
10
vvp/parse.y
10
vvp/parse.y
|
|
@ -19,7 +19,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#if !defined(WINNT)
|
||||
#ident "$Id: parse.y,v 1.29 2001/06/07 03:09:03 steve Exp $"
|
||||
#ident "$Id: parse.y,v 1.30 2001/06/15 03:28:31 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "parse_misc.h"
|
||||
|
|
@ -139,8 +139,8 @@ statement
|
|||
| T_LABEL K_MEM T_STRING ',' T_NUMBER ',' T_NUMBER ',' numbers ';'
|
||||
{ compile_memory($1, $3, $5, $7, $9.cnt, $9.nvec); }
|
||||
|
||||
| T_LABEL K_MEM_P T_SYMBOL ',' T_NUMBER ',' T_NUMBER ',' symbols ';'
|
||||
{ compile_memory_port($1, $3, $5, $7, $9.cnt, $9.vect); }
|
||||
| T_LABEL K_MEM_P T_SYMBOL ',' T_NUMBER ',' T_NUMBER ',' T_NUMBER ',' symbols ';'
|
||||
{ compile_memory_port($1, $3, $5, $7, $9, $11.cnt, $11.vect); }
|
||||
|
||||
| mem_init_stmt
|
||||
|
||||
|
|
@ -458,6 +458,10 @@ int compile_design(const char*path)
|
|||
|
||||
/*
|
||||
* $Log: parse.y,v $
|
||||
* Revision 1.30 2001/06/15 03:28:31 steve
|
||||
* Change the VPI call process so that loaded .vpi modules
|
||||
* use a function table instead of implicit binding.
|
||||
*
|
||||
* Revision 1.29 2001/06/07 03:09:03 steve
|
||||
* Implement .arith/sub subtraction.
|
||||
*
|
||||
|
|
|
|||
Loading…
Reference in New Issue