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Implement %ix/load.

This commit is contained in:
steve 2001-05-01 05:00:02 +00:00
parent cb39b3b65c
commit 2bf7653ab9
4 changed files with 56 additions and 17 deletions
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7
vvp/compile.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: compile.cc,v 1.49 2001/05/01 02:18:15 steve Exp $"
#ident "$Id: compile.cc,v 1.50 2001/05/01 05:00:02 steve Exp $"
#endif
# include "compile.h"
@ -82,7 +82,7 @@ const static struct opcode_table_s opcode_table[] = {
{ "%end", of_END, 0, {OA_NONE, OA_NONE, OA_NONE} },
{ "%inv", of_INV, 2, {OA_BIT1, OA_BIT2, OA_NONE} },
{ "%ix/add", of_IX_ADD, 2, {OA_BIT1, OA_NUMBER, OA_NONE} },
{ "%ix/load",of_IX_LOAD,3, {OA_BIT1, OA_BIT2, OA_NUMBER} },
{ "%ix/load",of_IX_LOAD,2, {OA_BIT1, OA_NUMBER, OA_NONE} },
{ "%ix/mul", of_IX_MUL, 2, {OA_BIT1, OA_NUMBER, OA_NONE} },
{ "%jmp", of_JMP, 1, {OA_CODE_PTR, OA_NONE, OA_NONE} },
{ "%jmp/0", of_JMP0, 2, {OA_CODE_PTR, OA_BIT1, OA_NONE} },
@ -1064,6 +1064,9 @@ void compile_dump(FILE*fd)
/*
* $Log: compile.cc,v $
* Revision 1.50 2001/05/01 05:00:02 steve
* Implement %ix/load.
*
* Revision 1.49 2001/05/01 02:18:15 steve
* Account for ipoint_input_index behavior in inputs_connect.
*

47
vvp/opcodes.txt
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@ -1,7 +1,7 @@
/*
* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
*
* $Id: opcodes.txt,v 1.14 2001/04/18 04:21:23 steve Exp $
* $Id: opcodes.txt,v 1.15 2001/05/01 05:00:02 steve Exp $
*/
@ -44,7 +44,7 @@ that contains the bit value to assign.
These instructions perform a generic comparison of two vectors of equal
size. The <bit-l> and <bit-r> numbers address the least-significant
bit of each vector, and <wid> is the width. If either operator is 0,
bit of each vector, and <wid> is the width. If either operand is 0,
1, 2 or 3 then it is taken to be a constant replicated to the selected
width.
@ -66,7 +66,8 @@ to implement all the Verilog comparison operators.
The %cmp/u and %cmp/s differ only in the handling of the lt bit. The
%cmp/u does an unsigned compare, whereas the %cmp/s does a signed
compare.
compare. In either case, if either operand constains x or z, then lt
bit gets the x value.
* %cmp/z <bit-l>, <bit-r>, <wid>
* %cmp/x <bit-l>, <bit-r>, <wid>
@ -118,6 +119,14 @@ bit:
z --> x
* %ix/load <idx>, <value>
This instruction loads an immediate value into the addressed index
register. The index register holds numeric values, so the <value> is a
number. The idx value selects the index register, and may be 0, 1, 2
or 3.
* %jmp <code-label>
The %jmp instruction performs an unconditional branch to a given
@ -141,17 +150,22 @@ continues. It has no effect in the current thread other then to wait
until the top child is cleared.
It is an error to execute %join if there are no children in the child
stack. If a child thread terminates before this instruction is called,
it remains in the stack as a zombie until the %join reaps it.
stack. Every %join in the thread must have a matching %fork that
spawned off a child thread.
If a thread terminates (i.e. executes %end) all its children are
terminated as well.
If the matching child instruction is still running, a %join suspends
the calling thread until the child ends. If the child is already
ended, then the %join does not block or yield the thread.
* %load <bit>, <functor-label>
This instruction loads a value from the given functor output into the
specified thread register bit.
specified thread register bit. The functor-label can refer to a .net,
a .var or a .functor, and may be indexed with array syntax to get at a
functor within a vector of functors. This instruction loads only a
single bit.
* %mov <dst>, <src>, <wid>
@ -159,23 +173,33 @@ This instruction copies a vector from one place in register space to
another. The destination and source vectors are assumed to be the same
width and non-overlapping. The <dst> may not be 0-3, but if the <src>
is one of the 4 constant bits, the effect is to replicate the value
into the destination vector. Useful for filling a vector.
into the destination vector. This is useful for filling a vector.
* %nor/r <dst>, <src>, <wid>
The %nor/r instruction is a reduction nor. That is, the <src> is a
vector with width, but the result is a single bit. The <src> vector is
not affected by the operation unless the <dst> bit is within the vector.
not affected by the operation unless the <dst> bit is within the
vector. The result is calculated before the <dst> bit is written, so
it is valid to place the <dst> within the <src>.
The actual operation performed is the inverted or of all the bits in
the vector.
* %or <dst>, <src>, <wid>
Perform the bitwise or of the vectors.
Perform the bitwise or of the vectors. Each bit in the <dst> is
combined with the corresponding bit in the source, according to the
truth table:
1 or ? --> 1
? or 1 --> 1
0 or 0 --> 0
otherwise x
* %set <var-label>, <bit>
This sets a bit of a variable, and is used to implement blocking
@ -191,6 +215,7 @@ declared using VPI. The operands are compiled down to a vpiHandle for
the call. The instruction contains only the vpiHandle for the
call. See the vpi.txt file for more on system task/function calls.
* %wait <functor-label>
When a thread executes this instruction, it places itself in the

9
vvp/vthread.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: vthread.cc,v 1.30 2001/05/01 01:09:39 steve Exp $"
#ident "$Id: vthread.cc,v 1.31 2001/05/01 05:00:02 steve Exp $"
#endif
# include "vthread.h"
@ -644,8 +644,8 @@ bool of_IX_MUL(vthread_t thr, vvp_code_t cp)
bool of_IX_LOAD(vthread_t thr, vvp_code_t cp)
{
// TODO
return true;
thr->index[cp->bit_idx1 & 3] = cp->number;
return true;
}
@ -925,6 +925,9 @@ bool of_ZOMBIE(vthread_t thr, vvp_code_t)
/*
* $Log: vthread.cc,v $
* Revision 1.31 2001/05/01 05:00:02 steve
* Implement %ix/load.
*
* Revision 1.30 2001/05/01 01:09:39 steve
* Add support for memory objects. (Stephan Boettcher)
*

10
vvp/vthread.txt
View File

@ -1,7 +1,7 @@
/*
* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
*
* $Id: vthread.txt,v 1.2 2001/03/22 05:08:00 steve Exp $
* $Id: vthread.txt,v 1.3 2001/05/01 05:00:02 steve Exp $
*/
@ -40,6 +40,14 @@ The remaining 64K-8 possible <bit> values are read-write bit registers
that can be accessed singly or as vectors. This obviously implies that
a bit address is 16 bits.
Threads also contain 4 numeric ``index'' registers. These are binary
values (no unknowns) that can be used in certain cases where extra
numeric parameters are needed. The thread instruction set includex
%ix/* instructions to manipulate these registers. The instructions
that use these registers document which register is used, and what the
numeric value is used for. For example, %assign/m uses index register
3 to select the memory bit to target its bit.
/*
* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
*