luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Add support for << is signal indices.

This commit is contained in:
steve 2001-01-04 04:47:51 +00:00
parent d5ec89813d
commit 8befc6f7c4
2 changed files with 32 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
elab_sig.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT) && !defined(macintosh)
#ident "$Id: elab_sig.cc,v 1.7 2000/12/11 00:31:43 steve Exp $"
#ident "$Id: elab_sig.cc,v 1.8 2001/01/04 04:47:51 steve Exp $"
#endif
# include "Module.h"
@ -325,8 +325,17 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
// If the register has indices, then this is a
// memory. Create the memory object.
verinum*lval = lidx_->eval_const(des, path);
assert(lval);
verinum*rval = ridx_->eval_const(des, path);
if ((lval == 0) || (rval == 0)) {
cerr << get_line() << ": internal error: There is "
<< "a problem evaluating indices for ``"
<< basename << "''." << endl;
des->errors += 1;
return;
}
assert(lval);
assert(rval);
long lnum = lval->as_long();
@ -348,6 +357,9 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
/*
* $Log: elab_sig.cc,v $
* Revision 1.8 2001/01/04 04:47:51 steve
* Add support for << is signal indices.
*
* Revision 1.7 2000/12/11 00:31:43 steve
* Add support for signed reg variables,
* simulate in t-vvm signed comparisons.

19
eval.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT) && !defined(macintosh)
#ident "$Id: eval.cc,v 1.16 2000/12/10 22:01:36 steve Exp $"
#ident "$Id: eval.cc,v 1.17 2001/01/04 04:47:51 steve Exp $"
#endif
# include "PExpr.h"
@ -81,12 +81,26 @@ verinum* PEBinary::eval_const(const Design*des, const string&path) const
res = new verinum(lv % rv, l->len());
break;
}
case 'l': {
assert(r->is_defined());
unsigned long rv = r->as_ulong();
res = new verinum(verinum::V0, l->len());
if (rv < res->len()) {
unsigned cnt = res->len() - rv;
for (unsigned idx = 0 ; idx < cnt ; idx += 1)
res->set(idx+rv, l->get(idx));
}
break;
}
default:
delete l;
delete r;
return 0;
}
delete l;
delete r;
return res;
}
@ -169,6 +183,9 @@ verinum* PEUnary::eval_const(const Design*des, const string&path) const
/*
* $Log: eval.cc,v $
* Revision 1.17 2001/01/04 04:47:51 steve
* Add support for << is signal indices.
*
* Revision 1.16 2000/12/10 22:01:36 steve
* Support decimal constants in behavioral delays.
*