Finally remove the verilog.sh script.
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steve
parent
ff53b60c66
commit
4faec154f0
19
Makefile.in
19
Makefile.in
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@ -16,7 +16,7 @@
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# 59 Temple Place - Suite 330
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# Boston, MA 02111-1307, USA
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#
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#ident "$Id: Makefile.in,v 1.84 2000/12/02 05:30:08 steve Exp $"
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#ident "$Id: Makefile.in,v 1.85 2000/12/02 05:57:46 steve Exp $"
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#
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#
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SHELL = /bin/sh
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@ -65,7 +65,7 @@ check: all
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./check | grep 'Hello, World'
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clean:
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rm -f *.o parse.cc parse.cc.output parse.h dep/*.d lexor.cc lexor_keyword.cc verilog ivl@EXEEXT@ libivl.a
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rm -f *.o parse.cc parse.cc.output parse.h dep/*.d lexor.cc lexor_keyword.cc ivl@EXEEXT@ libivl.a
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cd vvm ; $(MAKE) clean
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cd vpi ; $(MAKE) clean
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cd driver ; $(MAKE) clean
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@ -103,19 +103,6 @@ $(FF) $(TT)
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Makefile: Makefile.in config.status
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./config.status
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# Make the actual verilog program from the script template. This
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# simply invloves editing the substitution strings in the script into
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# the configured copy.
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tmp1 = bindir
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tmp2 = libdir
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tmp3 = includedir
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tmp4 = CXX
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verilog: $(srcdir)/verilog.sh
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sed -e 's;@$(tmp1)@;@bindir@;' \
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-e 's;@$(tmp2)@;@libdir@;' \
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-e 's;@$(tmp3)@;@includedir@;' \
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-e 's;@dllib@;@DLLIB@;' \
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-e 's;@$(tmp4)@;@CXX@;' < $< > $@
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ifeq (@CYGWIN@,yes)
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ivl@EXEEXT@: $O ivl.def
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@ -179,7 +166,7 @@ installdirs: mkinstalldirs
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uninstall:
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rm -f $(libdir)/ivl/ivl@EXEEXT@
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rm -f $(bindir)/verilog@EXEEXT@
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rm -f $(bindir)/verilog
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rm -f $(bindir)/gverilog@EXEEXT@
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rm -f $(includedir)/ivl_target.h
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cd driver ; $(MAKE) uninstall
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133
verilog.sh
133
verilog.sh
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@ -1,133 +0,0 @@
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#!/bin/sh
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# verilog - A wrapper shell script for ivl
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# Copyright (C) 1999 Stefan Petersen (spe@geda.seul.org)
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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# Added support for the -t flag, for odd-ball target types. <steve@icarus.com>
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# Added support for functors, especially for the XNF target. <steve@icarus.com>
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# Setup variables
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execPath=@libdir@/ivl
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execIVLPP=${execPath}/ivlpp
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execIVL=${execPath}/ivl
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execCpp=@CXX@
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tmpDir=/tmp
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tmpPPFile=${tmpDir}/ivl$$.pp
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tmpCCFile=${tmpDir}/ivl$$.cc
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includedir=@includedir@
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libdir=@libdir@
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VPIModulePath=@libdir@/ivl
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target="vvm"
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targetSuffix=""
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functors=""
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flags=""
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# If VPI module path aren't set up, warn at least
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#if test -z "${VPI_MODULE_PATH}" ; then
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# echo "Missing environment variable VPI_MODULE_PATH.";
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# echo "To be able to execute, set VPI_MODULE_PATH to ${VPIModulePath}";
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#fi
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# Try to extract given parameters
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parameter=`getopt D:I:Xxf:m:o:s:t: "$@"`
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eval set -- "${parameter}"
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while true ; do
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case "$1" in
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-D) extDefines="${extDefines} -D$2" ; shift 2 ;;
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-I) extIncPath="${extIncPath} -I $2" ; shift 2 ;;
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-X) target="xnf" ; shift ;;
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-f) flags="$flags -f$2" ; shift 2 ;;
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-m) flags="$flags -m$2" ; shift 2 ;;
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-o) outputFile=$2 ; shift 2 ;;
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-s) topModule="-s $2 " ; shift 2 ;;
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-t) target="$2" ; shift 2 ;;
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-x) execute="true"; shift ;;
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--) shift ; break ;;
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*) echo "Internal error! Arg is $1 " ; exit 1 ;;
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esac
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done
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# The rest is filenames
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verilogFile=$@;
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flags="$flags -fVPI_MODULE_PATH=${VPIModulePath}"
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if test -z "${verilogFile}" ; then
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echo "Missing infile";
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echo "verilog [-Dmacro[=defn]] [-Iincludepath] [-X] [-x] [-o outputfilename] [-s topmodule] sourcefile[s]" ;
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exit 1;
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fi
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# Choose a target file suffix based on the target type.
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case "$target" in
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vvm) targetSuffix="" ;;
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xnf) targetSuffix=".xnf"
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functors="-Fsynth -Fnodangle -Fxnfio" ;;
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*) targetSuffix=".$target" ;;
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esac
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# If no output file is given should we guess one or...?
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# Assumes a few silly things if several files are given
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if test -z "${outputFile}" ; then
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outputFile=`echo ${verilogFile} | sed -e 's;.* ;;' | sed -e 's;\..*$;;'`
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outputFile="${outputFile}${targetSuffix}" ;
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fi
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# Preprocess
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${execIVLPP} ${extDefines} ${extIncPath} -L -o ${tmpPPFile} ${verilogFile}
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if test $? -ne 0 ; then
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echo "Preprocessing failed. Terminating compilation."
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rm -f ${tmpPPFile}
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exit 1
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fi
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# Compile preprocessed verilog file
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${execIVL} -t ${target} -o ${tmpCCFile} ${topModule} ${functors} ${flags} ${tmpPPFile}
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if test $? -ne 0 ; then
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echo "Verilog compilation failed. Terminating compilation."
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rm -f ${tmpCCFile}
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exit 1
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fi
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rm -f ${tmpPPFile}
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case "${target}" in
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"xnf") mv ${tmpCCFile} ${outputFile} ;;
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"vvm") ${execCpp} -rdynamic -I${includedir} -L${libdir} ${tmpCCFile} -o ${outputFile} -lvvm @dllib@ ;
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if test $? -ne 0 ; then
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echo "C++ compilation failed. Terminating compilation."
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rm -f ${tmpCCFile}
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exit 1
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fi
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rm -f ${tmpCCFile} ;;
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*) mv ${tmpCCFile} ${outputFile} ;;
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esac
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if test ${execute} ; then
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./${outputFile}
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fi
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