Move all file manipulation out of target class.
This commit is contained in:
steve
parent
91a462e38c
commit
248baa26e1
17
emit.cc
17
emit.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT) && !defined(macintosh)
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#ident "$Id: emit.cc,v 1.49 2000/08/08 01:50:42 steve Exp $"
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#ident "$Id: emit.cc,v 1.50 2000/08/09 03:43:45 steve Exp $"
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#endif
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/*
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@ -26,7 +26,6 @@
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*/
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# include "target.h"
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# include "netlist.h"
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# include <iostream>
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# include <typeinfo>
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# include <cassert>
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@ -351,10 +350,13 @@ void NetWhile::emit_proc_recurse(struct target_t*tgt) const
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proc_->emit_proc(tgt);
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}
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bool Design::emit(ostream&o, struct target_t*tgt) const
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bool Design::emit(struct target_t*tgt) const
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{
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bool rc = true;
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tgt->start_design(o, this);
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rc = rc && tgt->start_design(this);
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if (rc == false)
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return false;
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// enumerate the scopes
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root_scope_->emit_scope(tgt);
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@ -448,12 +450,12 @@ void NetEUnary::expr_scan(struct expr_scan_t*tgt) const
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tgt->expr_unary(this);
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}
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bool emit(ostream&o, const Design*des, const char*type)
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bool emit(const Design*des, const char*type)
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{
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for (unsigned idx = 0 ; target_table[idx] ; idx += 1) {
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const struct target*tgt = target_table[idx];
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if (tgt->name == type)
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return des->emit(o, tgt->meth);
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return des->emit(tgt->meth);
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}
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}
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@ -461,6 +463,9 @@ bool emit(ostream&o, const Design*des, const char*type)
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/*
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* $Log: emit.cc,v $
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* Revision 1.50 2000/08/09 03:43:45 steve
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* Move all file manipulation out of target class.
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*
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* Revision 1.49 2000/08/08 01:50:42 steve
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* target methods need not take a file stream.
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*
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28
main.cc
28
main.cc
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@ -19,7 +19,7 @@ const char COPYRIGHT[] =
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT) && !defined(macintosh)
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#ident "$Id: main.cc,v 1.36 2000/07/29 17:58:21 steve Exp $"
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#ident "$Id: main.cc,v 1.37 2000/08/09 03:43:45 steve Exp $"
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#endif
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const char NOTICE[] =
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@ -119,7 +119,6 @@ int main(int argc, char*argv[])
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{
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bool help_flag = false;
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const char* net_path = 0;
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const char* out_path = 0;
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const char* pf_path = 0;
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const char* warn_en = "";
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int opt;
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@ -127,6 +126,7 @@ int main(int argc, char*argv[])
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queue<net_func> net_func_queue;
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flags["VPI_MODULE_LIST"] = "system";
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flags["-o"] = "a.out";
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min_typ_max_flag = TYP;
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min_typ_max_warn = 10;
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@ -155,7 +155,7 @@ int main(int argc, char*argv[])
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net_path = optarg;
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break;
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case 'o':
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out_path = optarg;
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flags["-o"] = optarg;
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break;
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case 'P':
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pf_path = optarg;
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@ -295,24 +295,9 @@ int main(int argc, char*argv[])
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}
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bool emit_rc;
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if (out_path) {
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ofstream out;
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out.open(out_path);
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if (! out.is_open()) {
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cerr << "Unable to open " << out_path << " for writing."
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<< endl;
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return 1;
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}
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emit_rc = emit(out, des, target);
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} else {
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emit_rc = emit(cout, des, target);
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}
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bool emit_rc = emit(des, target);
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if (!emit_rc) {
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cerr << "internal error: Code generation had errors." << endl;
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cerr << "error: Code generation had errors." << endl;
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return 1;
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}
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@ -321,6 +306,9 @@ int main(int argc, char*argv[])
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/*
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* $Log: main.cc,v $
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* Revision 1.37 2000/08/09 03:43:45 steve
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* Move all file manipulation out of target class.
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*
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* Revision 1.36 2000/07/29 17:58:21 steve
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* Introduce min:typ:max support.
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*
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT) && !defined(macintosh)
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#ident "$Id: netlist.h,v 1.154 2000/08/08 01:50:42 steve Exp $"
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#ident "$Id: netlist.h,v 1.155 2000/08/09 03:43:45 steve Exp $"
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#endif
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/*
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@ -2650,7 +2650,7 @@ class Design {
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// Iterate over the design...
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void dump(ostream&) const;
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void functor(struct functor_t*);
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bool emit(ostream&, struct target_t*) const;
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bool emit(struct target_t*) const;
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// This is incremented by elaboration when an error is
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// detected. It prevents code being emitted.
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@ -2722,6 +2722,9 @@ extern ostream& operator << (ostream&, NetNet::Type);
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/*
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* $Log: netlist.h,v $
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* Revision 1.155 2000/08/09 03:43:45 steve
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* Move all file manipulation out of target class.
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*
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* Revision 1.154 2000/08/08 01:50:42 steve
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* target methods need not take a file stream.
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*
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT) && !defined(macintosh)
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#ident "$Id: t-null.cc,v 1.14 2000/08/08 01:50:42 steve Exp $"
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#ident "$Id: t-null.cc,v 1.15 2000/08/09 03:43:45 steve Exp $"
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#endif
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# include "netlist.h"
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@ -30,6 +30,7 @@
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static class target_null_t : public target_t {
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public:
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bool start_design(const Design*) { return true; }
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void bufz(const NetBUFZ*) { }
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void event(const NetEvent*) { }
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void func_def(const NetFuncDef*) { }
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@ -53,6 +54,9 @@ static class target_null_t : public target_t {
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extern const struct target tgt_null = { "null", &target_null_obj };
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/*
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* $Log: t-null.cc,v $
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* Revision 1.15 2000/08/09 03:43:45 steve
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* Move all file manipulation out of target class.
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*
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* Revision 1.14 2000/08/08 01:50:42 steve
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* target methods need not take a file stream.
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*
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82
t-verilog.cc
82
t-verilog.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT) && !defined(macintosh)
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#ident "$Id: t-verilog.cc,v 1.12 2000/08/08 01:50:42 steve Exp $"
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#ident "$Id: t-verilog.cc,v 1.13 2000/08/09 03:43:45 steve Exp $"
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#endif
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/*
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@ -28,7 +28,7 @@
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* for debugging.
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*/
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# include <iostream>
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# include <fstream>
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# include <iomanip>
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# include <strstream>
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# include <typeinfo>
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@ -38,7 +38,7 @@ extern const struct target tgt_verilog;
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class target_verilog : public target_t {
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public:
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virtual void start_design(ostream&os, const Design*);
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virtual bool start_design(const Design*);
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virtual void signal(const NetNet*);
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virtual void logic(const NetLogic*);
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virtual void bufz(const NetBUFZ*);
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@ -54,8 +54,7 @@ class target_verilog : public target_t {
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void end_process(const NetProcTop*);
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unsigned indent_;
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ostream*out_;
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# define OS (*out_)
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ofstream out;
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void emit_expr_(ostream&os, const NetExpr*);
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};
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@ -67,11 +66,13 @@ class target_verilog : public target_t {
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* design. Targets can use these hooks to generate header or footer
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* information if desired.
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*/
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void target_verilog::start_design(ostream&os, const Design*)
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bool target_verilog::start_design(const Design*des)
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{
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out.open(des->get_flag("-o").c_str(), ios::out | ios::trunc);
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indent_ = 0;
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os << "module " << "main" << ";" << endl;
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out_ = &os;
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out << "module " << "main" << ";" << endl;
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return true;
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}
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/*
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@ -81,14 +82,14 @@ void target_verilog::start_design(ostream&os, const Design*)
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*/
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void target_verilog::signal(const NetNet*net)
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{
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OS << " " << net->type();
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out << " " << net->type();
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if (net->pin_count() > 1)
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OS << " [" << net->msb() << ":" << net->lsb() << "]";
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out << " [" << net->msb() << ":" << net->lsb() << "]";
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if (net->rise_time())
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OS << " #" << net->rise_time();
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out << " #" << net->rise_time();
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OS << " " << mangle(net->name()) << ";" << endl;
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out << " " << mangle(net->name()) << ";" << endl;
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}
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void target_verilog::logic(const NetLogic*net)
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@ -96,52 +97,52 @@ void target_verilog::logic(const NetLogic*net)
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switch (net->type()) {
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case NetLogic::AND:
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OS << " and";
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out << " and";
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break;
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case NetLogic::NAND:
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OS << " nand";
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out << " nand";
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break;
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case NetLogic::NOR:
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OS << " nor";
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out << " nor";
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break;
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case NetLogic::NOT:
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OS << " not";
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out << " not";
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break;
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case NetLogic::OR:
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OS << " or";
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out << " or";
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break;
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case NetLogic::XNOR:
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OS << " xnor";
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out << " xnor";
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break;
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case NetLogic::XOR:
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OS << " xor";
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out << " xor";
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break;
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}
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OS << " #" << net->rise_time() << " " << mangle(net->name()) << "(";
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out << " #" << net->rise_time() << " " << mangle(net->name()) << "(";
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unsigned sidx;
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const NetNet*sig = find_link_signal(net, 0, sidx);
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OS << mangle(sig->name()) << "[" << sidx << "]";
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out << mangle(sig->name()) << "[" << sidx << "]";
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for (unsigned idx = 1 ; idx < net->pin_count() ; idx += 1) {
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sig = find_link_signal(net, idx, sidx);
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assert(sig);
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OS << ", " << mangle(sig->name()) << "[" << sidx << "]";
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out << ", " << mangle(sig->name()) << "[" << sidx << "]";
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}
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OS << ");" << endl;
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out << ");" << endl;
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}
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void target_verilog::bufz(const NetBUFZ*net)
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{
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assert( net->pin_count() == 2 );
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OS << " assign ";
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out << " assign ";
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unsigned sidx;
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const NetNet*sig = find_link_signal(net, 0, sidx);
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OS << mangle(sig->name()) << "[" << sidx << "] = ";
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out << mangle(sig->name()) << "[" << sidx << "] = ";
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sig = find_link_signal(net, 1, sidx);
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OS << mangle(sig->name()) << "[" << sidx << "];" << endl;
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out << mangle(sig->name()) << "[" << sidx << "];" << endl;
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}
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bool target_verilog::process(const NetProcTop*top)
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@ -156,10 +157,10 @@ void target_verilog::start_process(const NetProcTop*proc)
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{
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switch (proc->type()) {
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case NetProcTop::KINITIAL:
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OS << " initial" << endl;
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out << " initial" << endl;
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break;
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case NetProcTop::KALWAYS:
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OS << " always" << endl;
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out << " always" << endl;
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break;
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}
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@ -194,17 +195,17 @@ void target_verilog::emit_expr_(ostream&os, const NetExpr*expr)
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bool target_verilog::proc_block(const NetBlock*net)
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{
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OS << setw(indent_) << "" << "begin" << endl;
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out << setw(indent_) << "" << "begin" << endl;
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indent_ += 4;
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net->emit_recurse(this);
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indent_ -= 4;
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OS << setw(indent_) << "" << "end" << endl;
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out << setw(indent_) << "" << "end" << endl;
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return true;
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}
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bool target_verilog::proc_delay(const NetPDelay*net)
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{
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OS << setw(indent_) << "" << "#" << net->delay() << endl;
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out << setw(indent_) << "" << "#" << net->delay() << endl;
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indent_ += 4;
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bool flag = net->emit_proc_recurse(this);
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@ -230,18 +231,18 @@ static void vtask_parm(ostream&os, const NetExpr*ex)
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void target_verilog::proc_stask(const NetSTask*net)
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{
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OS << setw(indent_) << "" << net->name();
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out << setw(indent_) << "" << net->name();
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if (net->nparms() > 0) {
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OS << "(";
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vtask_parm(OS, net->parm(0));
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out << "(";
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vtask_parm(out, net->parm(0));
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for (unsigned idx = 1 ; idx < net->nparms() ; idx += 1) {
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OS << ", ";
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vtask_parm(OS, net->parm(idx));
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out << ", ";
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vtask_parm(out, net->parm(idx));
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}
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OS << ")";
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out << ")";
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}
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OS << ";" << endl;
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out << ";" << endl;
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}
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@ -251,7 +252,7 @@ void target_verilog::proc_stask(const NetSTask*net)
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*/
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void target_verilog::end_design(const Design*)
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{
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OS << "endmodule" << endl;
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out << "endmodule" << endl;
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}
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static target_verilog tgt_verilog_obj;
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@ -263,6 +264,9 @@ const struct target tgt_verilog = {
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/*
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* $Log: t-verilog.cc,v $
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* Revision 1.13 2000/08/09 03:43:45 steve
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* Move all file manipulation out of target class.
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*
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* Revision 1.12 2000/08/08 01:50:42 steve
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* target methods need not take a file stream.
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*
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224
t-vvm.cc
224
t-vvm.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT) && !defined(macintosh)
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#ident "$Id: t-vvm.cc,v 1.166 2000/08/08 01:50:42 steve Exp $"
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#ident "$Id: t-vvm.cc,v 1.167 2000/08/09 03:43:45 steve Exp $"
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#endif
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# include <iostream>
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@ -144,7 +144,7 @@ class target_vvm : public target_t {
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target_vvm();
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~target_vvm();
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virtual void start_design(ostream&os, const Design*);
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virtual bool start_design(const Design*);
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virtual void scope(const NetScope*);
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virtual void event(const NetEvent*);
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virtual void signal(const NetNet*);
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@ -202,8 +202,7 @@ class target_vvm : public target_t {
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NumberTable bits_table;
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ostream*out_;
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# define OS (*out_)
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ofstream out;
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// Method definitions go into this file.
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char*defn_name;
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@ -893,9 +892,9 @@ static string emit_parm_rval(target_vvm*tgt, const NetExpr*expr)
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return scan.result;
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}
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void target_vvm::start_design(ostream&os, const Design*mod)
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bool target_vvm::start_design(const Design*mod)
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{
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out_ = &os;
|
||||
out.open(mod->get_flag("-o").c_str(), ios::out | ios::trunc);
|
||||
|
||||
defn_name = tempnam(0, "ivldf");
|
||||
defn.open(defn_name, ios::in | ios::out | ios::trunc);
|
||||
|
|
@ -906,15 +905,15 @@ void target_vvm::start_design(ostream&os, const Design*mod)
|
|||
start_code_name = tempnam(0, "ivlsc");
|
||||
start_code.open(start_code_name, ios::in | ios::out | ios::trunc);
|
||||
|
||||
os << "# include \"vvm.h\"" << endl;
|
||||
os << "# include \"vvm_nexus.h\"" << endl;
|
||||
os << "# include \"vvm_gates.h\"" << endl;
|
||||
os << "# include \"vvm_signal.h\"" << endl;
|
||||
os << "# include \"vvm_func.h\"" << endl;
|
||||
os << "# include \"vvm_calltf.h\"" << endl;
|
||||
os << "# include \"vvm_thread.h\"" << endl;
|
||||
os << "# include \"vpi_user.h\"" << endl;
|
||||
os << "# include \"vpi_priv.h\"" << endl;
|
||||
out << "# include \"vvm.h\"" << endl;
|
||||
out << "# include \"vvm_nexus.h\"" << endl;
|
||||
out << "# include \"vvm_gates.h\"" << endl;
|
||||
out << "# include \"vvm_signal.h\"" << endl;
|
||||
out << "# include \"vvm_func.h\"" << endl;
|
||||
out << "# include \"vvm_calltf.h\"" << endl;
|
||||
out << "# include \"vvm_thread.h\"" << endl;
|
||||
out << "# include \"vpi_user.h\"" << endl;
|
||||
out << "# include \"vpi_priv.h\"" << endl;
|
||||
|
||||
signal_bit_counter = 0;
|
||||
process_counter = 0;
|
||||
|
|
@ -931,13 +930,15 @@ void target_vvm::start_design(ostream&os, const Design*mod)
|
|||
<< mod->get_precision() << ");" << endl;
|
||||
start_code << "static void design_start()" << endl;
|
||||
start_code << "{" << endl;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void target_vvm::scope(const NetScope*scope)
|
||||
{
|
||||
string hname = mangle(scope->name()) + "_scope";
|
||||
OS << "// SCOPE: " << scope->name() << endl;
|
||||
OS << "static struct __vpiScope " << hname << ";" << endl;
|
||||
out << "// SCOPE: " << scope->name() << endl;
|
||||
out << "static struct __vpiScope " << hname << ";" << endl;
|
||||
|
||||
string type_code;
|
||||
switch (scope->type()) {
|
||||
|
|
@ -971,93 +972,93 @@ void target_vvm::scope(const NetScope*scope)
|
|||
void target_vvm::event(const NetEvent*event)
|
||||
{
|
||||
string mname = mangle(event->full_name());
|
||||
OS << "static vvm_sync " << mname << "; // "
|
||||
out << "static vvm_sync " << mname << "; // "
|
||||
<< event->get_line() << ": event " << event->full_name() << endl;
|
||||
}
|
||||
|
||||
void target_vvm::end_design(const Design*mod)
|
||||
{
|
||||
if (string_counter > 0)
|
||||
OS << "static struct __vpiStringConst string_table[" <<
|
||||
out << "static struct __vpiStringConst string_table[" <<
|
||||
string_counter+1 << "];" << endl;
|
||||
if (number_counter > 0)
|
||||
OS << "static struct __vpiNumberConst number_table[" <<
|
||||
out << "static struct __vpiNumberConst number_table[" <<
|
||||
number_counter+1 << "];" << endl;
|
||||
if (nexus_wire_counter > 0)
|
||||
OS << "static vvm_nexus nexus_wire_table[" <<
|
||||
out << "static vvm_nexus nexus_wire_table[" <<
|
||||
nexus_wire_counter << "];" << endl;
|
||||
if (signal_bit_counter > 0)
|
||||
OS << "static vpip_bit_t signal_bit_table[" <<
|
||||
out << "static vpip_bit_t signal_bit_table[" <<
|
||||
signal_bit_counter << "];" << endl;
|
||||
|
||||
if (bits_table.count() > 0) {
|
||||
OS << "static vpip_bit_t const_bits_table[" << bits_table.count()
|
||||
out << "static vpip_bit_t const_bits_table[" << bits_table.count()
|
||||
<< "] = {";
|
||||
|
||||
for (unsigned idx = 0 ; idx < bits_table.count() ; idx += 1) {
|
||||
if (idx%16 == 0) OS << endl;
|
||||
if (idx%16 == 0) out << endl;
|
||||
switch (bits_table.bit(idx)) {
|
||||
case verinum::V0:
|
||||
OS << " St0,";
|
||||
out << " St0,";
|
||||
break;
|
||||
case verinum::V1:
|
||||
OS << " St1,";
|
||||
out << " St1,";
|
||||
break;
|
||||
case verinum::Vx:
|
||||
OS << " StX,";
|
||||
out << " StX,";
|
||||
break;
|
||||
case verinum::Vz:
|
||||
OS << " HiZ,";
|
||||
out << " HiZ,";
|
||||
break;
|
||||
default:
|
||||
OS << " ,";
|
||||
out << " ,";
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
OS << endl << "};" << endl;
|
||||
out << endl << "};" << endl;
|
||||
}
|
||||
|
||||
defn.close();
|
||||
|
||||
OS << "// **** Definition code" << endl;
|
||||
out << "// **** Definition code" << endl;
|
||||
{ ifstream rdefn (defn_name);
|
||||
OS << rdefn.rdbuf();
|
||||
out << rdefn.rdbuf();
|
||||
}
|
||||
unlink(defn_name);
|
||||
free(defn_name);
|
||||
defn_name = 0;
|
||||
OS << "// **** end definition code" << endl;
|
||||
out << "// **** end definition code" << endl;
|
||||
|
||||
|
||||
OS << "// **** init_code" << endl;
|
||||
out << "// **** init_code" << endl;
|
||||
init_code << "}" << endl;
|
||||
init_code.close();
|
||||
{ ifstream rinit_code (init_code_name);
|
||||
OS << rinit_code.rdbuf();
|
||||
out << rinit_code.rdbuf();
|
||||
}
|
||||
unlink(init_code_name);
|
||||
free(init_code_name);
|
||||
init_code_name = 0;
|
||||
OS << "// **** end init_code" << endl;
|
||||
out << "// **** end init_code" << endl;
|
||||
|
||||
|
||||
OS << "// **** start_code" << endl;
|
||||
out << "// **** start_code" << endl;
|
||||
start_code << "}" << endl;
|
||||
start_code.close();
|
||||
{ ifstream rstart_code (start_code_name);
|
||||
OS << rstart_code.rdbuf();
|
||||
out << rstart_code.rdbuf();
|
||||
}
|
||||
unlink(start_code_name);
|
||||
free(start_code_name);
|
||||
start_code_name = 0;
|
||||
OS << "// **** end start_code" << endl;
|
||||
out << "// **** end start_code" << endl;
|
||||
|
||||
|
||||
OS << "main()" << endl << "{" << endl;
|
||||
out << "main()" << endl << "{" << endl;
|
||||
string vpi_module_path = mod->get_flag("VPI_MODULE_PATH");
|
||||
if (vpi_module_path.length() > 0)
|
||||
OS << " vvm_set_module_path(\"" << vpi_module_path <<
|
||||
out << " vvm_set_module_path(\"" << vpi_module_path <<
|
||||
"\");" << endl;
|
||||
|
||||
string vpi_module_list = mod->get_flag("VPI_MODULE_LIST");
|
||||
|
|
@ -1071,19 +1072,21 @@ void target_vvm::end_design(const Design*mod)
|
|||
name = vpi_module_list;
|
||||
vpi_module_list = "";
|
||||
}
|
||||
OS << " vvm_load_vpi_module(\"" << name << ".vpi\");" << endl;
|
||||
out << " vvm_load_vpi_module(\"" << name << ".vpi\");" << endl;
|
||||
}
|
||||
OS << " design_init();" << endl;
|
||||
OS << " design_start();" << endl;
|
||||
OS << " vpip_simulation_run();" << endl;
|
||||
OS << "}" << endl;
|
||||
out << " design_init();" << endl;
|
||||
out << " design_start();" << endl;
|
||||
out << " vpip_simulation_run();" << endl;
|
||||
out << "}" << endl;
|
||||
out.close();
|
||||
|
||||
}
|
||||
|
||||
bool target_vvm::process(const NetProcTop*top)
|
||||
{
|
||||
start_process(OS, top);
|
||||
start_process(out, top);
|
||||
bool rc = top->statement()->emit_proc(this);
|
||||
end_process(OS, top);
|
||||
end_process(out, top);
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
|
@ -1130,7 +1133,7 @@ void target_vvm::signal(const NetNet*sig)
|
|||
}
|
||||
}
|
||||
|
||||
OS << "static vvm_signal_t " << net_name << ";" << endl;
|
||||
out << "static vvm_signal_t " << net_name << ";" << endl;
|
||||
|
||||
init_code << " vpip_make_reg(&" << net_name
|
||||
<< ", \"" << sig->name() << "\", signal_bit_table+"
|
||||
|
|
@ -1177,7 +1180,7 @@ void target_vvm::signal(const NetNet*sig)
|
|||
void target_vvm::memory(const NetMemory*mem)
|
||||
{
|
||||
const string mname = mangle(mem->name());
|
||||
OS << "static vvm_memory_t<" << mem->width() << ", " <<
|
||||
out << "static vvm_memory_t<" << mem->width() << ", " <<
|
||||
mem->count() << "> " << mname << ";"
|
||||
" /* " << mem->name() << " */" << endl;
|
||||
init_code << " vpip_make_memory(&" << mname << ", \"" <<
|
||||
|
|
@ -1192,7 +1195,7 @@ void target_vvm::task_def(const NetTaskDef*def)
|
|||
const string save_thread_class = thread_class_;
|
||||
thread_class_ = name;
|
||||
|
||||
OS << "static bool " << name << "_step_0_(vvm_thread*thr);" << endl;
|
||||
out << "static bool " << name << "_step_0_(vvm_thread*thr);" << endl;
|
||||
|
||||
defn << "static bool " << name << "_step_0_(vvm_thread*thr) {" << endl;
|
||||
|
||||
|
|
@ -1223,8 +1226,8 @@ void target_vvm::func_def(const NetFuncDef*def)
|
|||
assert(! function_def_flag_);
|
||||
function_def_flag_ = true;
|
||||
|
||||
OS << "// Function " << def->name() << endl;
|
||||
OS << "static void " << name << "();" << endl;
|
||||
out << "// Function " << def->name() << endl;
|
||||
out << "static void " << name << "();" << endl;
|
||||
|
||||
defn << "// Function " << def->name() << endl;
|
||||
defn << "static void " << name << "()" << endl;
|
||||
|
|
@ -1306,7 +1309,7 @@ void target_vvm::emit_gate_outputfun_(const NetNode*gate, unsigned gpin)
|
|||
|
||||
void target_vvm::lpm_add_sub(const NetAddSub*gate)
|
||||
{
|
||||
OS << "static vvm_add_sub " <<
|
||||
out << "static vvm_add_sub " <<
|
||||
mangle(gate->name()) << "(" << gate->width() << ");" << endl;
|
||||
|
||||
/* Connect the DataA inputs. */
|
||||
|
|
@ -1378,7 +1381,7 @@ void target_vvm::lpm_clshift(const NetCLShift*gate)
|
|||
{
|
||||
string mname = mangle(gate->name());
|
||||
|
||||
OS << "static vvm_clshift " << mname << "(" <<
|
||||
out << "static vvm_clshift " << mname << "(" <<
|
||||
gate->width() << "," << gate->width_dist() << ");" <<
|
||||
endl;
|
||||
|
||||
|
|
@ -1426,7 +1429,7 @@ void target_vvm::lpm_compare(const NetCompare*gate)
|
|||
{
|
||||
string mname = mangle(gate->name());
|
||||
|
||||
OS << "static vvm_compare " << mname << "(" << gate->width() <<
|
||||
out << "static vvm_compare " << mname << "(" << gate->width() <<
|
||||
");" << endl;
|
||||
|
||||
/* Connect DataA inputs... */
|
||||
|
|
@ -1487,7 +1490,7 @@ void target_vvm::lpm_divide(const NetDivide*mul)
|
|||
{
|
||||
string mname = mangle(mul->name());
|
||||
|
||||
OS << "static vvm_idiv " << mname << "(" << mul->width_r() <<
|
||||
out << "static vvm_idiv " << mname << "(" << mul->width_r() <<
|
||||
"," << mul->width_a() << "," << mul->width_b() << ");" << endl;
|
||||
|
||||
|
||||
|
|
@ -1527,7 +1530,7 @@ void target_vvm::lpm_ff( const NetFF*gate)
|
|||
unsigned ncode;
|
||||
string mname = mangle(gate->name());
|
||||
|
||||
OS << "static vvm_ff " << mname << "(" << gate->width() << ");" << endl;
|
||||
out << "static vvm_ff " << mname << "(" << gate->width() << ");" << endl;
|
||||
|
||||
/* Connect the clock input... */
|
||||
|
||||
|
|
@ -1564,7 +1567,7 @@ void target_vvm::lpm_mult(const NetMult*mul)
|
|||
{
|
||||
string mname = mangle(mul->name());
|
||||
|
||||
OS << "static vvm_mult " << mname << "(" << mul->width_r() <<
|
||||
out << "static vvm_mult " << mname << "(" << mul->width_r() <<
|
||||
"," << mul->width_a() << "," << mul->width_b() << "," <<
|
||||
mul->width_s() << ");" << endl;
|
||||
|
||||
|
|
@ -1603,7 +1606,7 @@ void target_vvm::lpm_mux(const NetMux*mux)
|
|||
{
|
||||
string mname = mangle(mux->name());
|
||||
|
||||
OS << "static vvm_mux " << mname << "(" << mux->width() << ","
|
||||
out << "static vvm_mux " << mname << "(" << mux->width() << ","
|
||||
<< mux->size() << "," << mux->sel_width() << ");" << endl;
|
||||
|
||||
/* Connect the select inputs... */
|
||||
|
|
@ -1643,7 +1646,7 @@ void target_vvm::lpm_ram_dq(const NetRamDq*ram)
|
|||
{
|
||||
string mname = mangle(ram->name());
|
||||
|
||||
OS << "static vvm_ram_dq<" << ram->width() << "," <<
|
||||
out << "static vvm_ram_dq<" << ram->width() << "," <<
|
||||
ram->awidth() << "," << ram->size() << "> " << mname <<
|
||||
"(&" << mangle(ram->mem()->name()) << ");" << endl;
|
||||
|
||||
|
|
@ -1716,46 +1719,46 @@ void target_vvm::logic(const NetLogic*gate)
|
|||
switch (gate->type()) {
|
||||
case NetLogic::AND:
|
||||
if ((gate->pin_count()-1) == 2)
|
||||
OS << "static vvm_and2 ";
|
||||
out << "static vvm_and2 ";
|
||||
else
|
||||
OS << "static vvm_and" << "<" << gate->pin_count()-1 << "> ";
|
||||
out << "static vvm_and" << "<" << gate->pin_count()-1 << "> ";
|
||||
break;
|
||||
case NetLogic::BUF:
|
||||
OS << "static vvm_buf ";
|
||||
out << "static vvm_buf ";
|
||||
break;
|
||||
case NetLogic::BUFIF0:
|
||||
OS << "static vvm_bufif0 ";
|
||||
out << "static vvm_bufif0 ";
|
||||
break;
|
||||
case NetLogic::BUFIF1:
|
||||
OS << "static vvm_bufif1 ";
|
||||
out << "static vvm_bufif1 ";
|
||||
break;
|
||||
case NetLogic::NAND:
|
||||
OS << "static vvm_nand" << "<" << gate->pin_count()-1 << "> ";
|
||||
out << "static vvm_nand" << "<" << gate->pin_count()-1 << "> ";
|
||||
break;
|
||||
case NetLogic::NOR:
|
||||
if ((gate->pin_count()-1) == 2)
|
||||
OS << "static vvm_nor2 ";
|
||||
out << "static vvm_nor2 ";
|
||||
else
|
||||
OS << "static vvm_nor" << "<" << gate->pin_count()-1 << "> ";
|
||||
out << "static vvm_nor" << "<" << gate->pin_count()-1 << "> ";
|
||||
break;
|
||||
case NetLogic::NOT:
|
||||
OS << "static vvm_not ";
|
||||
out << "static vvm_not ";
|
||||
break;
|
||||
case NetLogic::OR:
|
||||
OS << "static vvm_or" << "<" << gate->pin_count()-1 << "> ";
|
||||
out << "static vvm_or" << "<" << gate->pin_count()-1 << "> ";
|
||||
break;
|
||||
case NetLogic::XNOR:
|
||||
OS << "static vvm_xnor" << "<" << gate->pin_count()-1 << "> ";
|
||||
out << "static vvm_xnor" << "<" << gate->pin_count()-1 << "> ";
|
||||
break;
|
||||
case NetLogic::XOR:
|
||||
OS << "static vvm_xor" << "<" << gate->pin_count()-1 << "> ";
|
||||
out << "static vvm_xor" << "<" << gate->pin_count()-1 << "> ";
|
||||
break;
|
||||
default:
|
||||
OS << "#error \"internal ivl error:bad gate type for " <<
|
||||
out << "#error \"internal ivl error:bad gate type for " <<
|
||||
gate->name() << "\"" << endl;
|
||||
}
|
||||
|
||||
OS << mname << " (" << gate->rise_time() << ");" << endl;
|
||||
out << mname << " (" << gate->rise_time() << ");" << endl;
|
||||
|
||||
/* Write the code to invoke startup for this object. */
|
||||
|
||||
|
|
@ -1811,7 +1814,7 @@ void target_vvm::bufz(const NetBUFZ*gate)
|
|||
string nexus;
|
||||
unsigned ncode;
|
||||
|
||||
OS << "static vvm_bufz " << mname << ";" << endl;
|
||||
out << "static vvm_bufz " << mname << ";" << endl;
|
||||
|
||||
nexus = gate->pin(0).nexus()->name();
|
||||
ncode = nexus_wire_map[nexus];
|
||||
|
|
@ -1855,18 +1858,18 @@ void target_vvm::udp_comb(const NetUDP_COMB*gate)
|
|||
unsigned ncode;
|
||||
|
||||
|
||||
OS << "static const char*" << mname << "_ctab =" << endl;
|
||||
out << "static const char*" << mname << "_ctab =" << endl;
|
||||
|
||||
string inp;
|
||||
char outc;
|
||||
for (bool rc = gate->first(inp, outc)
|
||||
; rc ; rc = gate->next(inp,outc)) {
|
||||
|
||||
OS << " \"" << inp << outc << "\"" << endl;
|
||||
out << " \"" << inp << outc << "\"" << endl;
|
||||
}
|
||||
OS << " ;" << endl;
|
||||
out << " ;" << endl;
|
||||
|
||||
OS << "static vvm_udp_comb " << mname << "("
|
||||
out << "static vvm_udp_comb " << mname << "("
|
||||
<< (gate->pin_count()-1) << ", " << mname<<"_ctab);" << endl;
|
||||
|
||||
/* Connect the output of the device... */
|
||||
|
|
@ -1905,7 +1908,7 @@ static string state_to_string(unsigned state, unsigned npins)
|
|||
void target_vvm::udp(const NetUDP*gate)
|
||||
{
|
||||
assert(gate->is_sequential());
|
||||
udp_sequ_(OS, gate);
|
||||
udp_sequ_(out, gate);
|
||||
}
|
||||
|
||||
void target_vvm::udp_sequ_(ostream&os, const NetUDP*gate)
|
||||
|
|
@ -1977,7 +1980,7 @@ void target_vvm::net_case_cmp(const NetCaseCmp*gate)
|
|||
unsigned ncode;
|
||||
|
||||
assert(gate->pin_count() == 3);
|
||||
OS << "static vvm_eeq " << mname << "(" <<
|
||||
out << "static vvm_eeq " << mname << "(" <<
|
||||
gate->rise_time() << ");" << endl;
|
||||
|
||||
/* Connect the output pin */
|
||||
|
|
@ -2011,7 +2014,7 @@ bool target_vvm::net_cassign(const NetCAssign*dev)
|
|||
{
|
||||
string mname = mangle(dev->name());
|
||||
|
||||
OS << "static vvm_force " << mname << "(" << dev->pin_count()
|
||||
out << "static vvm_force " << mname << "(" << dev->pin_count()
|
||||
<< ");" << endl;
|
||||
|
||||
for (unsigned idx = 0 ; idx < dev->pin_count() ; idx += 1) {
|
||||
|
|
@ -2035,7 +2038,7 @@ void target_vvm::net_const(const NetConst*gate)
|
|||
{
|
||||
const string mname = mangle(gate->name());
|
||||
|
||||
OS << "static vvm_nexus::drive_t " << mname
|
||||
out << "static vvm_nexus::drive_t " << mname
|
||||
<< "[" << gate->pin_count() << "];" << endl;
|
||||
|
||||
for (unsigned idx = 0 ; idx < gate->pin_count() ; idx += 1) {
|
||||
|
|
@ -2059,7 +2062,7 @@ bool target_vvm::net_force(const NetForce*dev)
|
|||
{
|
||||
string mname = mangle(dev->name());
|
||||
|
||||
OS << "static vvm_force " << mname << "(" << dev->pin_count()
|
||||
out << "static vvm_force " << mname << "(" << dev->pin_count()
|
||||
<< ");" << endl;
|
||||
|
||||
for (unsigned idx = 0 ; idx < dev->pin_count() ; idx += 1) {
|
||||
|
|
@ -2081,19 +2084,19 @@ void target_vvm::net_probe(const NetEvProbe*net)
|
|||
switch (net->edge()) {
|
||||
case NetEvProbe::POSEDGE:
|
||||
assert(net->pin_count() == 1);
|
||||
OS << "static vvm_posedge " << mname
|
||||
out << "static vvm_posedge " << mname
|
||||
<< "(&" << mevent << ");" << endl;
|
||||
break;
|
||||
|
||||
case NetEvProbe::NEGEDGE:
|
||||
assert(net->pin_count() == 1);
|
||||
OS << "static vvm_negedge " << mname
|
||||
out << "static vvm_negedge " << mname
|
||||
<< "(&" << mevent << ");" << endl;
|
||||
break;
|
||||
|
||||
|
||||
case NetEvProbe::ANYEDGE:
|
||||
OS << "static vvm_anyedge " << mname
|
||||
out << "static vvm_anyedge " << mname
|
||||
<< "(&" << mevent << ", " << net->pin_count() << ");" << endl;
|
||||
break;
|
||||
}
|
||||
|
|
@ -2390,7 +2393,7 @@ bool target_vvm::proc_block(const NetBlock*net)
|
|||
|
||||
// Declare the exit step...
|
||||
|
||||
OS << "static bool " << thread_class_ << "_step_" << exit_step
|
||||
out << "static bool " << thread_class_ << "_step_" << exit_step
|
||||
<< "_(vvm_thread*thr);" << endl;
|
||||
|
||||
|
||||
|
|
@ -2399,7 +2402,7 @@ bool target_vvm::proc_block(const NetBlock*net)
|
|||
|
||||
for (cur = net->proc_first() ; cur ; cur = net->proc_next(cur)) {
|
||||
cnt += 1;
|
||||
OS << "static bool " << thread_class_ << "_step_"
|
||||
out << "static bool " << thread_class_ << "_step_"
|
||||
<< (exit_step+cnt) << "_(vvm_thread*thr);" << endl;
|
||||
}
|
||||
|
||||
|
|
@ -2471,7 +2474,7 @@ bool target_vvm::proc_block(const NetBlock*net)
|
|||
void target_vvm::proc_case(const NetCase*net)
|
||||
{
|
||||
if (function_def_flag_) {
|
||||
proc_case_fun(OS, net);
|
||||
proc_case_fun(out, net);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -2550,7 +2553,7 @@ void target_vvm::proc_case(const NetCase*net)
|
|||
|
||||
step_num += 1;
|
||||
|
||||
OS << "static bool " << thread_class_ << "_step_"
|
||||
out << "static bool " << thread_class_ << "_step_"
|
||||
<< step_num << "_(vvm_thread*thr);" << endl;
|
||||
|
||||
defn << "static bool " << thread_class_ << "_step_"
|
||||
|
|
@ -2567,7 +2570,7 @@ void target_vvm::proc_case(const NetCase*net)
|
|||
if (default_idx < net->nitems()) {
|
||||
step_num += 1;
|
||||
|
||||
OS << "static bool " << thread_class_ << "_step_"
|
||||
out << "static bool " << thread_class_ << "_step_"
|
||||
<< step_num << "_(vvm_thread*thr);" << endl;
|
||||
|
||||
defn << "static bool " << thread_class_ << "_step_"
|
||||
|
|
@ -2582,7 +2585,7 @@ void target_vvm::proc_case(const NetCase*net)
|
|||
|
||||
/* Finally, start the exit step. */
|
||||
|
||||
OS << "static bool " << thread_class_ << "_step_"
|
||||
out << "static bool " << thread_class_ << "_step_"
|
||||
<< exit_step << "_(vvm_thread*thr);" << endl;
|
||||
|
||||
defn << "static bool " << thread_class_ << "_step_"
|
||||
|
|
@ -2662,7 +2665,7 @@ bool target_vvm::proc_cassign(const NetCAssign*dev)
|
|||
void target_vvm::proc_condit(const NetCondit*net)
|
||||
{
|
||||
if (function_def_flag_) {
|
||||
proc_condit_fun(OS, net);
|
||||
proc_condit_fun(out, net);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -2674,13 +2677,13 @@ void target_vvm::proc_condit(const NetCondit*net)
|
|||
|
||||
/* Declare new steps that I am going to create. */
|
||||
|
||||
OS << "static bool " << thread_class_ << "_step_"
|
||||
out << "static bool " << thread_class_ << "_step_"
|
||||
<< if_step << "_(vvm_thread*thr);" << endl;
|
||||
|
||||
OS << "static bool " << thread_class_ << "_step_"
|
||||
out << "static bool " << thread_class_ << "_step_"
|
||||
<< else_step << "_(vvm_thread*thr);" << endl;
|
||||
|
||||
OS << "static bool " << thread_class_ << "_step_"
|
||||
out << "static bool " << thread_class_ << "_step_"
|
||||
<< out_step << "_(vvm_thread*thr);" << endl;
|
||||
|
||||
defn << " if (B_IS1(" << expr << "[0]))" << endl;
|
||||
|
|
@ -2771,7 +2774,7 @@ void target_vvm::proc_forever(const NetForever*net)
|
|||
defn << " return true;" << endl;
|
||||
defn << "}" << endl;
|
||||
|
||||
OS << "static bool " << thread_class_ << "_step_"
|
||||
out << "static bool " << thread_class_ << "_step_"
|
||||
<< top_step << "_(vvm_thread*thr);" << endl;
|
||||
|
||||
defn << "static bool " << thread_class_ << "_step_"
|
||||
|
|
@ -2786,7 +2789,7 @@ void target_vvm::proc_forever(const NetForever*net)
|
|||
/* Generate a loop out step to catch unreachable stuff afer
|
||||
the loop. */
|
||||
|
||||
OS << "static bool " << thread_class_ << "_step_"
|
||||
out << "static bool " << thread_class_ << "_step_"
|
||||
<< out_step << "_(vvm_thread*thr);" << endl;
|
||||
|
||||
defn << "static bool " << thread_class_ << "_step_"
|
||||
|
|
@ -2827,15 +2830,15 @@ void target_vvm::proc_repeat( const NetRepeat*net)
|
|||
}
|
||||
|
||||
/* Declare a variable to use as a loop index. */
|
||||
OS << "static unsigned " << thread_class_ << "_step_"
|
||||
out << "static unsigned " << thread_class_ << "_step_"
|
||||
<< top_step << "_idx_;" << endl;
|
||||
|
||||
/* Declare the top step. */
|
||||
OS << "static bool " << thread_class_ << "_step_"
|
||||
out << "static bool " << thread_class_ << "_step_"
|
||||
<< top_step << "_(vvm_thread*thr);" << endl;
|
||||
|
||||
/* Declare the exit step. */
|
||||
OS << "static bool " << thread_class_ << "_step_"
|
||||
out << "static bool " << thread_class_ << "_step_"
|
||||
<< out_step << "_(vvm_thread*thr);" << endl;
|
||||
|
||||
|
||||
|
|
@ -2927,7 +2930,7 @@ void target_vvm::proc_utask(const NetUTask*net)
|
|||
unsigned out_step = ++thread_step_;
|
||||
const string name = mangle(net->name());
|
||||
|
||||
OS << "static bool " << thread_class_ << "_step_"
|
||||
out << "static bool " << thread_class_ << "_step_"
|
||||
<< out_step << "_(vvm_thread*thr);" << endl;
|
||||
|
||||
defn << " assert(thr->callee_ == 0);" << endl;
|
||||
|
|
@ -2967,7 +2970,7 @@ bool target_vvm::proc_wait(const NetEvWait*wait)
|
|||
source vvm_sync objects. Then, wait on the selector
|
||||
object instead. */
|
||||
unsigned id = selector_counter++;
|
||||
OS << "static vvm_sync selector_" << id << ";" << endl;
|
||||
out << "static vvm_sync selector_" << id << ";" << endl;
|
||||
|
||||
for (unsigned idx = 0 ; idx < wait->nevents() ; idx+= 1) {
|
||||
const NetEvent*ev = wait->event(idx);
|
||||
|
|
@ -2986,7 +2989,7 @@ bool target_vvm::proc_wait(const NetEvWait*wait)
|
|||
defn << " return false;" << endl;
|
||||
defn << "}" << endl;
|
||||
|
||||
OS << "static bool " << thread_class_ << "_step_" << out_step
|
||||
out << "static bool " << thread_class_ << "_step_" << out_step
|
||||
<< "_(vvm_thread*thr);" << endl;
|
||||
|
||||
defn << "bool " << thread_class_ << "_step_" << out_step
|
||||
|
|
@ -3013,10 +3016,10 @@ void target_vvm::proc_while(const NetWhile*net)
|
|||
unsigned head_step = ++thread_step_;
|
||||
unsigned out_step = ++thread_step_;
|
||||
|
||||
OS << "static bool " << thread_class_ << "_step_"
|
||||
out << "static bool " << thread_class_ << "_step_"
|
||||
<< head_step << "_(vvm_thread*thr);" << endl;
|
||||
|
||||
OS << "static bool " << thread_class_ << "_step_"
|
||||
out << "static bool " << thread_class_ << "_step_"
|
||||
<< out_step << "_(vvm_thread*thr);" << endl;
|
||||
|
||||
defn << " thr->step_ = &" << thread_class_ << "_step_"
|
||||
|
|
@ -3080,7 +3083,7 @@ bool target_vvm::proc_delay(const NetPDelay*proc)
|
|||
defn << "}" << endl;
|
||||
}
|
||||
|
||||
OS << "static bool " << thread_class_ << "_step_"
|
||||
out << "static bool " << thread_class_ << "_step_"
|
||||
<< thread_step_ << "_(vvm_thread*thr);" << endl;
|
||||
|
||||
defn << "static bool " << thread_class_ << "_step_" << thread_step_
|
||||
|
|
@ -3112,6 +3115,9 @@ extern const struct target tgt_vvm = {
|
|||
};
|
||||
/*
|
||||
* $Log: t-vvm.cc,v $
|
||||
* Revision 1.167 2000/08/09 03:43:45 steve
|
||||
* Move all file manipulation out of target class.
|
||||
*
|
||||
* Revision 1.166 2000/08/08 01:50:42 steve
|
||||
* target methods need not take a file stream.
|
||||
*
|
||||
|
|
|
|||
152
t-xnf.cc
152
t-xnf.cc
|
|
@ -17,7 +17,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#if !defined(WINNT) && !defined(macintosh)
|
||||
#ident "$Id: t-xnf.cc,v 1.33 2000/08/08 01:50:42 steve Exp $"
|
||||
#ident "$Id: t-xnf.cc,v 1.34 2000/08/09 03:43:45 steve Exp $"
|
||||
#endif
|
||||
|
||||
/* XNF BACKEND
|
||||
|
|
@ -94,7 +94,7 @@ verinum::V link_get_ival(const Link&lnk)
|
|||
class target_xnf : public target_t {
|
||||
|
||||
public:
|
||||
void start_design(ostream&os, const Design*);
|
||||
bool start_design(const Design*);
|
||||
void end_design(const Design*);
|
||||
void memory(const NetMemory*);
|
||||
void signal(const NetNet*);
|
||||
|
|
@ -125,8 +125,7 @@ class target_xnf : public target_t {
|
|||
static void draw_carry(ostream&os, const NetAddSub*, unsigned idx,
|
||||
enum adder_type);
|
||||
|
||||
ostream*out_;
|
||||
#define OS (*out_)
|
||||
ofstream out_;
|
||||
ofstream ncf_;
|
||||
};
|
||||
|
||||
|
|
@ -219,25 +218,29 @@ void target_xnf::draw_sym_with_lcaname(ostream&os, string lca,
|
|||
os << "END" << endl;
|
||||
}
|
||||
|
||||
void target_xnf::start_design(ostream&os, const Design*des)
|
||||
bool target_xnf::start_design(const Design*des)
|
||||
{
|
||||
out_.open(des->get_flag("-o").c_str(), ios::out | ios::trunc);
|
||||
|
||||
string ncfpath = des->get_flag("ncf");
|
||||
if (ncfpath != "")
|
||||
ncf_.open(ncfpath.c_str());
|
||||
|
||||
os << "LCANET,6" << endl;
|
||||
os << "PROG,verilog,0.2PRE,\"Icarus Verilog\"" << endl;
|
||||
out_ << "LCANET,6" << endl;
|
||||
out_ << "PROG,verilog,0.2PRE,\"Icarus Verilog\"" << endl;
|
||||
ncf_ << "# Generated by Icarus Verilog 0.2PRE" << endl;
|
||||
|
||||
if (des->get_flag("part") != "") {
|
||||
os << "PART," << des->get_flag("part") << endl;
|
||||
out_ << "PART," << des->get_flag("part") << endl;
|
||||
ncf_ << "CONFIG PART=" << des->get_flag("part") << ";" << endl;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void target_xnf::end_design(const Design*)
|
||||
{
|
||||
OS << "EOF" << endl;
|
||||
out_ << "EOF" << endl;
|
||||
ncf_.close();
|
||||
}
|
||||
|
||||
|
|
@ -318,11 +321,11 @@ void target_xnf::signal(const NetNet*net)
|
|||
string pname = mname.substr(mname.find('/')+1, mname.length());
|
||||
|
||||
if (net->pin_count() == 1) {
|
||||
OS << "SIG, " << mangle(net->name()) << ", PIN="
|
||||
out_ << "SIG, " << mangle(net->name()) << ", PIN="
|
||||
<< pname << endl;
|
||||
|
||||
} else for (unsigned idx = 0; idx < net->pin_count(); idx += 1) {
|
||||
OS << "SIG, " << mangle(net->name()) << "<" << idx
|
||||
out_ << "SIG, " << mangle(net->name()) << "<" << idx
|
||||
<< ">, PIN=" << pname << idx << endl;
|
||||
}
|
||||
|
||||
|
|
@ -345,7 +348,7 @@ void target_xnf::signal(const NetNet*net)
|
|||
char dir;
|
||||
unsigned num;
|
||||
scrape_pad_info(pad, dir, num);
|
||||
OS << "EXT, " << mangle(net->name()) << ", " << dir
|
||||
out_ << "EXT, " << mangle(net->name()) << ", " << dir
|
||||
<< ", " << num << endl;
|
||||
|
||||
ncf_ << "# Assignment to pin " << num << " (DIR=" << dir <<
|
||||
|
|
@ -479,13 +482,13 @@ void target_xnf::lpm_add_sub(const NetAddSub*gate)
|
|||
bits of the carry chain. Label this with the width instead
|
||||
of the bit position so that symbols don't clash. */
|
||||
|
||||
draw_carry(OS, gate, width+1, FORCE0);
|
||||
draw_carry(out_, gate, width+1, FORCE0);
|
||||
|
||||
|
||||
/* Now make the 2 bit adders that chain from the cin
|
||||
initializer and up. Save the tail bits for later. */
|
||||
for (unsigned idx = 0 ; idx < width-2 ; idx += 2)
|
||||
draw_carry(OS, gate, idx, DOUBLE);
|
||||
draw_carry(out_, gate, idx, DOUBLE);
|
||||
|
||||
/* Always have one or two tail bits. The situation gets a
|
||||
little tricky if we want the carry output, so handle that
|
||||
|
|
@ -509,23 +512,23 @@ void target_xnf::lpm_add_sub(const NetAddSub*gate)
|
|||
|
||||
if (gate->pin_Cout().is_linked()) {
|
||||
if (width%2 == 0) {
|
||||
draw_carry(OS, gate, width-2, DOUBLE);
|
||||
draw_carry(OS, gate, width, EXAMINE_CI);
|
||||
draw_carry(out_, gate, width-2, DOUBLE);
|
||||
draw_carry(out_, gate, width, EXAMINE_CI);
|
||||
} else {
|
||||
draw_carry(OS, gate, width-1, LOWER_W_CO);
|
||||
draw_carry(out_, gate, width-1, LOWER_W_CO);
|
||||
}
|
||||
|
||||
} else {
|
||||
if (width%2 == 0)
|
||||
draw_carry(OS, gate, width-2, LOWER);
|
||||
draw_carry(out_, gate, width-2, LOWER);
|
||||
else
|
||||
draw_carry(OS, gate, width-1, LOWER);
|
||||
draw_carry(out_, gate, width-1, LOWER);
|
||||
}
|
||||
|
||||
/* Now draw all the single bit (plus carry in) adders from XOR
|
||||
gates. This puts the F and G units to use. */
|
||||
for (unsigned idx = 0 ; idx < width ; idx += 1)
|
||||
draw_xor(OS, gate, idx);
|
||||
draw_xor(out_, gate, idx);
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -537,17 +540,17 @@ void target_xnf::lpm_add_sub(const NetAddSub*gate)
|
|||
void target_xnf::lpm_compare(const NetCompare*dev)
|
||||
{
|
||||
if (dev->pin_AEB().is_linked()) {
|
||||
lpm_compare_eq_(OS, dev);
|
||||
lpm_compare_eq_(out_, dev);
|
||||
return;
|
||||
}
|
||||
|
||||
if (dev->pin_AGEB().is_linked()) {
|
||||
lpm_compare_ge_(OS, dev);
|
||||
lpm_compare_ge_(out_, dev);
|
||||
return;
|
||||
}
|
||||
|
||||
if (dev->pin_ALEB().is_linked()) {
|
||||
lpm_compare_le_(OS, dev);
|
||||
lpm_compare_le_(out_, dev);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -651,7 +654,7 @@ void target_xnf::lpm_ff(const NetFF*net)
|
|||
|
||||
string lcaname = net->attribute("XNF-LCA");
|
||||
if (lcaname != "") {
|
||||
draw_sym_with_lcaname(OS, lcaname, net);
|
||||
draw_sym_with_lcaname(out_, lcaname, net);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -667,30 +670,30 @@ void target_xnf::lpm_ff(const NetFF*net)
|
|||
|
||||
verinum::V ival = link_get_ival(net->pin_Q(idx));
|
||||
|
||||
OS << "SYM, " << mangle(net->name()) << "<" << idx << ">, DFF, ";
|
||||
out_ << "SYM, " << mangle(net->name()) << "<" << idx << ">, DFF, ";
|
||||
|
||||
switch (ival) {
|
||||
case verinum::V0:
|
||||
OS << "INIT=R, ";
|
||||
out_ << "INIT=R, ";
|
||||
break;
|
||||
case verinum::V1:
|
||||
OS << "INIT=S, ";
|
||||
out_ << "INIT=S, ";
|
||||
break;
|
||||
}
|
||||
|
||||
OS << "LIBVER=2.0.0" << endl;
|
||||
draw_pin(OS, "Q", net->pin_Q(idx));
|
||||
draw_pin(OS, "D", net->pin_Data(idx));
|
||||
out_ << "LIBVER=2.0.0" << endl;
|
||||
draw_pin(out_, "Q", net->pin_Q(idx));
|
||||
draw_pin(out_, "D", net->pin_Data(idx));
|
||||
|
||||
if (net->attribute("Clock:LPM_Polarity") == "INVERT")
|
||||
draw_pin(OS, "~C", net->pin_Clock());
|
||||
draw_pin(out_, "~C", net->pin_Clock());
|
||||
else
|
||||
draw_pin(OS, "C", net->pin_Clock());
|
||||
draw_pin(out_, "C", net->pin_Clock());
|
||||
|
||||
if (count_outputs(net->pin_Enable()) > 0)
|
||||
draw_pin(OS, "CE", net->pin_Enable());
|
||||
draw_pin(out_, "CE", net->pin_Enable());
|
||||
|
||||
OS << "END" << endl;
|
||||
out_ << "END" << endl;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -708,15 +711,15 @@ void target_xnf::lpm_mux(const NetMux*net)
|
|||
|
||||
for (unsigned idx = 0 ; idx < net->width() ; idx += 1) {
|
||||
|
||||
OS << "SYM, " << mangle(net->name()) << "<" << idx << ">,"
|
||||
out_ << "SYM, " << mangle(net->name()) << "<" << idx << ">,"
|
||||
<< " EQN, EQN=(I0 * I2) + (~I0 * I1)" << endl;
|
||||
|
||||
draw_pin(OS, "I0", net->pin_Sel(0));
|
||||
draw_pin(OS, "I1", net->pin_Data(idx,0));
|
||||
draw_pin(OS, "I2", net->pin_Data(idx,1));
|
||||
draw_pin(OS, "O", net->pin_Result(idx));
|
||||
draw_pin(out_, "I0", net->pin_Sel(0));
|
||||
draw_pin(out_, "I1", net->pin_Data(idx,0));
|
||||
draw_pin(out_, "I2", net->pin_Data(idx,1));
|
||||
draw_pin(out_, "O", net->pin_Result(idx));
|
||||
|
||||
OS << "END" << endl;
|
||||
out_ << "END" << endl;
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -728,20 +731,20 @@ void target_xnf::lpm_ram_dq(const NetRamDq*ram)
|
|||
const NetMemory*mem = ram->mem();
|
||||
|
||||
for (unsigned idx = 0 ; idx < ram->width() ; idx += 1) {
|
||||
OS << "SYM, " << mangle(ram->name())
|
||||
out_ << "SYM, " << mangle(ram->name())
|
||||
<< "<" << idx << ">, RAMS" << endl;
|
||||
|
||||
draw_pin(OS, "O", ram->pin_Q(idx));
|
||||
draw_pin(OS, "D", ram->pin_Data(idx));
|
||||
draw_pin(OS, "WE", ram->pin_WE());
|
||||
draw_pin(OS, "WCLK", ram->pin_InClock());
|
||||
draw_pin(out_, "O", ram->pin_Q(idx));
|
||||
draw_pin(out_, "D", ram->pin_Data(idx));
|
||||
draw_pin(out_, "WE", ram->pin_WE());
|
||||
draw_pin(out_, "WCLK", ram->pin_InClock());
|
||||
for (unsigned adr = 0 ; adr < ram->awidth() ; adr += 1) {
|
||||
strstream tmp;
|
||||
tmp << "A" << adr << ends;
|
||||
draw_pin(OS, tmp.str(), ram->pin_Address(adr));
|
||||
draw_pin(out_, tmp.str(), ram->pin_Address(adr));
|
||||
}
|
||||
|
||||
OS << "END" << endl;
|
||||
out_ << "END" << endl;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -756,7 +759,7 @@ void target_xnf::net_const(const NetConst*c)
|
|||
unsigned cpin;
|
||||
const NetObj*cur;
|
||||
|
||||
OS << " PWR, " << v << ", " << choose_sig_name(&lnk) << endl;
|
||||
out_ << " PWR, " << v << ", " << choose_sig_name(&lnk) << endl;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -770,48 +773,48 @@ void target_xnf::logic(const NetLogic*net)
|
|||
// about this object.
|
||||
string lca = net->attribute("XNF-LCA");
|
||||
if (lca != "") {
|
||||
draw_sym_with_lcaname(OS, lca, net);
|
||||
draw_sym_with_lcaname(out_, lca, net);
|
||||
return;
|
||||
}
|
||||
|
||||
OS << "SYM, " << mangle(net->name()) << ", ";
|
||||
out_ << "SYM, " << mangle(net->name()) << ", ";
|
||||
switch (net->type()) {
|
||||
case NetLogic::AND:
|
||||
OS << "AND";
|
||||
out_ << "AND";
|
||||
break;
|
||||
case NetLogic::BUF:
|
||||
OS << "BUF";
|
||||
out_ << "BUF";
|
||||
break;
|
||||
case NetLogic::NAND:
|
||||
OS << "NAND";
|
||||
out_ << "NAND";
|
||||
break;
|
||||
case NetLogic::NOR:
|
||||
OS << "NOR";
|
||||
out_ << "NOR";
|
||||
break;
|
||||
case NetLogic::NOT:
|
||||
OS << "INV";
|
||||
out_ << "INV";
|
||||
break;
|
||||
case NetLogic::OR:
|
||||
OS << "OR";
|
||||
out_ << "OR";
|
||||
break;
|
||||
case NetLogic::XNOR:
|
||||
OS << "XNOR";
|
||||
out_ << "XNOR";
|
||||
break;
|
||||
case NetLogic::XOR:
|
||||
OS << "XOR";
|
||||
out_ << "XOR";
|
||||
break;
|
||||
case NetLogic::BUFIF0:
|
||||
case NetLogic::BUFIF1:
|
||||
OS << "TBUF";
|
||||
out_ << "TBUF";
|
||||
break;
|
||||
default:
|
||||
cerr << "internal error: XNF: Unhandled logic type." << endl;
|
||||
break;
|
||||
}
|
||||
OS << ", LIBVER=2.0.0" << endl;
|
||||
out_ << ", LIBVER=2.0.0" << endl;
|
||||
|
||||
/* All of these kinds of devices have an output on pin 0. */
|
||||
draw_pin(OS, "O", net->pin(0));
|
||||
draw_pin(out_, "O", net->pin(0));
|
||||
|
||||
/* Most devices have inputs called I<N> for all the remaining
|
||||
pins. The TBUF devices are slightly different, but
|
||||
|
|
@ -820,29 +823,29 @@ void target_xnf::logic(const NetLogic*net)
|
|||
|
||||
case NetLogic::BUFIF0:
|
||||
assert(net->pin_count() == 3);
|
||||
draw_pin(OS, "I", net->pin(1));
|
||||
draw_pin(OS, "~T", net->pin(2));
|
||||
draw_pin(out_, "I", net->pin(1));
|
||||
draw_pin(out_, "~T", net->pin(2));
|
||||
break;
|
||||
|
||||
case NetLogic::BUFIF1:
|
||||
assert(net->pin_count() == 3);
|
||||
draw_pin(OS, "I", net->pin(1));
|
||||
draw_pin(OS, "T", net->pin(2));
|
||||
draw_pin(out_, "I", net->pin(1));
|
||||
draw_pin(out_, "T", net->pin(2));
|
||||
break;
|
||||
|
||||
default:
|
||||
if (net->pin_count() == 2) {
|
||||
draw_pin(OS, "I", net->pin(1));
|
||||
draw_pin(out_, "I", net->pin(1));
|
||||
} else for (unsigned idx = 1; idx < net->pin_count(); idx += 1) {
|
||||
string name = "I";
|
||||
assert(net->pin_count() <= 11);
|
||||
name += (char)('0'+idx-1);
|
||||
draw_pin(OS, name, net->pin(idx));
|
||||
draw_pin(out_, name, net->pin(idx));
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
OS << "END" << endl;
|
||||
out_ << "END" << endl;
|
||||
}
|
||||
|
||||
void target_xnf::bufz(const NetBUFZ*net)
|
||||
|
|
@ -853,11 +856,11 @@ void target_xnf::bufz(const NetBUFZ*net)
|
|||
<< endl;
|
||||
warned_once=1;
|
||||
}
|
||||
OS << "SYM, " << mangle(net->name()) << ", BUF, LIBVER=2.0.0" << endl;
|
||||
out_ << "SYM, " << mangle(net->name()) << ", BUF, LIBVER=2.0.0" << endl;
|
||||
assert(net->pin_count() == 2);
|
||||
draw_pin(OS, "O", net->pin(0));
|
||||
draw_pin(OS, "I", net->pin(1));
|
||||
OS << "END" << endl;
|
||||
draw_pin(out_, "O", net->pin(0));
|
||||
draw_pin(out_, "I", net->pin(1));
|
||||
out_ << "END" << endl;
|
||||
}
|
||||
|
||||
void target_xnf::udp(const NetUDP*net)
|
||||
|
|
@ -871,7 +874,7 @@ void target_xnf::udp(const NetUDP*net)
|
|||
return;
|
||||
}
|
||||
|
||||
draw_sym_with_lcaname(OS, lca, net);
|
||||
draw_sym_with_lcaname(out_, lca, net);
|
||||
}
|
||||
|
||||
static target_xnf target_xnf_obj;
|
||||
|
|
@ -880,6 +883,9 @@ extern const struct target tgt_xnf = { "xnf", &target_xnf_obj };
|
|||
|
||||
/*
|
||||
* $Log: t-xnf.cc,v $
|
||||
* Revision 1.34 2000/08/09 03:43:45 steve
|
||||
* Move all file manipulation out of target class.
|
||||
*
|
||||
* Revision 1.33 2000/08/08 01:50:42 steve
|
||||
* target methods need not take a file stream.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#if !defined(WINNT) && !defined(macintosh)
|
||||
#ident "$Id: target.cc,v 1.42 2000/08/08 01:50:42 steve Exp $"
|
||||
#ident "$Id: target.cc,v 1.43 2000/08/09 03:43:45 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "target.h"
|
||||
|
|
@ -27,10 +27,6 @@ target_t::~target_t()
|
|||
{
|
||||
}
|
||||
|
||||
void target_t::start_design(ostream&os, const Design*)
|
||||
{
|
||||
}
|
||||
|
||||
void target_t::scope(const NetScope*)
|
||||
{
|
||||
}
|
||||
|
|
@ -398,6 +394,9 @@ void expr_scan_t::expr_binary(const NetEBinary*ex)
|
|||
|
||||
/*
|
||||
* $Log: target.cc,v $
|
||||
* Revision 1.43 2000/08/09 03:43:45 steve
|
||||
* Move all file manipulation out of target class.
|
||||
*
|
||||
* Revision 1.42 2000/08/08 01:50:42 steve
|
||||
* target methods need not take a file stream.
|
||||
*
|
||||
|
|
|
|||
10
target.h
10
target.h
|
|
@ -19,11 +19,10 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#if !defined(WINNT) && !defined(macintosh)
|
||||
#ident "$Id: target.h,v 1.41 2000/08/08 01:50:42 steve Exp $"
|
||||
#ident "$Id: target.h,v 1.42 2000/08/09 03:43:45 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "netlist.h"
|
||||
class ostream;
|
||||
|
||||
/*
|
||||
* This header file describes the types and constants used to describe
|
||||
|
|
@ -54,7 +53,7 @@ struct target_t {
|
|||
|
||||
/* Start the design. This sets the main output file stream
|
||||
that the target should use. */
|
||||
virtual void start_design(ostream&os, const Design*);
|
||||
virtual bool start_design(const Design*) =0;
|
||||
|
||||
/* This is called once for each scope in the design, before
|
||||
anything else is called. */
|
||||
|
|
@ -148,7 +147,7 @@ struct expr_scan_t {
|
|||
/* The emit functions take a design and emit it to the output stream
|
||||
using the specified target. If the target is given by name, it is
|
||||
located in the target_table and used. */
|
||||
extern bool emit(ostream&o, const Design*des, const char*type);
|
||||
extern bool emit(const Design*des, const char*type);
|
||||
|
||||
/* This function takes a fully qualified verilog name (which may have,
|
||||
for example, dots in it) and produces a mangled version that can be
|
||||
|
|
@ -161,6 +160,9 @@ extern const struct target *target_table[];
|
|||
|
||||
/*
|
||||
* $Log: target.h,v $
|
||||
* Revision 1.42 2000/08/09 03:43:45 steve
|
||||
* Move all file manipulation out of target class.
|
||||
*
|
||||
* Revision 1.41 2000/08/08 01:50:42 steve
|
||||
* target methods need not take a file stream.
|
||||
*
|
||||
|
|
|
|||
Loading…
Reference in New Issue