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OpenRAM
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1013 Commits

Author SHA1 Message Date
mrg 5e546ee974 New power strapping mostly working. 
Each module uses M3/M4 power straps with pins on the ends.
Works in all technologies for a single no mux, dual port SRAM.
 2022-04-05 13:51:55 -07:00
mrg 01a73b31e1 Fix power ring routing boundary bug. 2022-03-18 10:32:25 -07:00
mrg 7e7670581c Add some vertical/horizontal pins for sky130 only 2022-03-16 07:58:29 -07:00
mrg 8c911f70b9 Build changes. 
Don't pull docker since it will be build by CI.
Shuffle tests to stagger technologies and test types.
 2022-03-06 10:31:43 -08:00
mrg d69e55c2e3 Power routing changes. 
Make the power rails an "experimental_power" option and conditional.
Rename route_vdd_gnd to route_supplies everywhere for consistency.
 2022-03-06 09:56:00 -08:00
mrg 8b3c10ae79 Improvements to power routing. 
Improved the route horizontal and vertical pin functions to
create a single pin at the end.
Swapped A and B on wordline driver input for cleaner routing
in most technologies.
Fixed vertical supply routing in port_address.
 2022-03-04 15:44:07 -08:00
mrg e139b4aa81 Swap A and B pins in wordline driver. 2022-03-03 09:53:24 -08:00
mrg 7654cd7295 Allow supply pins on m4 too 2022-03-02 16:47:17 -08:00
mrg 51ba88d896 Port address with vertical power stripes 2022-03-02 16:29:43 -08:00
mrg f7e3672c89 Route horizontal supplies in write driver. 2022-03-01 14:37:51 -08:00
mrg 2520d9f590 Remove commented code in precharge array 2022-02-25 16:21:12 -08:00
mrg 7b77378927 Add layer to horizontal pin help and use in precharge 2022-02-25 10:45:25 -08:00
mrg 5376b5bf20 Fix offset to center select signal between bitlines 2022-02-23 15:38:11 -08:00
mrg baf369fc96 Convert power to rails rather than pins in sense amp and precharge 2022-02-23 14:06:49 -08:00
mrg 5451a8d07a Don't make internal bus pins because magic will extract ports 2022-02-23 14:06:01 -08:00
Jesse Cirimelli-Low 1a0861539a Merge branch 'opc_fix' into dev 2022-02-15 14:38:20 -08:00
Jesse Cirimelli-Low a54eb90371 place decoder rail contacts at least m2 min spacing away 2022-02-15 14:37:07 -08:00
Jesse Cirimelli-Low c24c37a15a Merge branch 'dev' into lvs 2021-12-22 15:46:09 -08:00
Jesse Cirimelli-Low 8879820af4 replica col lvs fix 2021-12-15 14:19:52 -08:00
mrg 0c3ee643ab Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
Jesse Cirimelli-Low 2fb08af684 change col mux array poly routing from straight to 'L' 2021-11-17 17:22:03 -08:00
Jesse Cirimelli-Low 5792256db1 route spare col 2021-10-05 15:28:20 -07:00
Hunter Nichols 39ae1270d7 Merge branch 'dev' into cacti_model 2021-09-20 17:01:50 -07:00
mrg 8d9a4cc27b PEP8 cleanup 2021-09-07 16:49:44 -07:00
mrg 3f031a90db Specify two stage wl_en driver to prevent race condition 2021-09-03 12:52:17 -07:00
Hunter Nichols 1e08005639 Merge branch 'dev' into cacti_model 2021-07-26 14:35:47 -07:00
Hunter Nichols e9bea4f0b6 Changed names of some functions in base CACTI delay function. Removed unused analytical delay functions. 2021-07-12 13:02:22 -07:00
Jesse Cirimelli-Low 1a7adcfdad fix vnb and vpb routing in rba 2021-07-08 18:31:55 -07:00
Jesse Cirimelli-Low e280efda7b don't copy pwell pin onto nwell 2021-07-01 15:19:59 -07:00
Jesse Cirimelli-Low bcc956ecdc merge dev 2021-06-29 11:42:32 -07:00
Jesse Cirimelli-Low 24e42d7cbe refactor adding bias pins 2021-06-29 11:37:07 -07:00
mrg 930cc48e16 Add vdd/gnd for all bitcells 2021-06-29 09:37:30 -07:00
Jesse Cirimelli-Low c36f471333 add vnb/vpb lvs correspondence points 2021-06-29 02:31:56 -07:00
Hunter Nichols 294ccf602e Merged with dev, addressed conflict in port data 2021-06-21 17:23:32 -07:00
Hunter Nichols 470317eaa4 Changed bitcell exclusion to instead exclude array instances to prevent issues of module exclusion affecting other modules. 2021-06-21 17:20:25 -07:00
Jesse Cirimelli-Low 2760beae34 swap sky130 replica bitcell array power bias routing 2021-06-21 15:22:31 -07:00
Jesse Cirimelli-Low 0008df0204 catch where strap size is zero 2021-06-18 15:24:24 -07:00
Jesse Cirimelli-Low 8ceece2af6 check for valid dimensions instead of recalcuating 2021-06-18 14:21:02 -07:00
Jesse Cirimelli-Low d9afe89770 remove print statement 2021-06-17 03:23:46 -07:00
Jesse Cirimelli-Low 1ce6b4d41a fix freepdk45 2021-06-17 03:21:01 -07:00
mrg 1e486cd344 Use local spacing rule 2021-06-16 18:41:39 -07:00
Hunter Nichols 16e658726e When determining bitline names, added a technology check for sky130. 2021-06-16 17:04:02 -07:00
Jesse Cirimelli-Low 25bc178132 extend input rail 2021-06-14 15:13:17 -07:00
Hunter Nichols 74b55ea83b Added a graph exclusion clear for the mux to prevent previous graph creations causing bugs. 2021-06-14 14:39:54 -07:00
Hunter Nichols 7df36a916b Added an exclusion for unused column mux paths to prevent multiple outputs paths in graph. 2021-06-14 13:51:52 -07:00
Jesse Cirimelli-Low bee9b07516 fix decoder routing 2021-06-11 18:19:07 -07:00
Jesse Cirimelli-Low 2e72da0e53 rotate input to rail contacts for drc 2021-06-10 14:01:28 -07:00
Jesse Cirimelli-Low 247a388ab5 Merge branch 'dev' into laptop_checkpoint 2021-06-09 18:25:45 -07:00
Jesse Cirimelli-Low 10f561648f remove hierarchical decoder vertial m1 above pins 2021-06-09 18:24:21 -07:00
mrg cf61096936 Merge branch 'laptop_checkpoint' into dev 2021-06-04 15:22:37 -07:00
mrg 53791d79c8 spacing must be two extensions (one for each cell) 2021-06-04 08:56:06 -07:00
Jesse Cirimelli-Low 6705f99855 merge in dev 2021-05-28 14:06:23 -07:00
Jesse Cirimelli-Low 1a894a99dd push bias pins to top level power routing 2021-05-28 13:41:58 -07:00
Jesse Cirimelli-Low f9eae3fb80 route bias pisn 2021-05-24 02:42:04 -07:00
mrg 3abebe4068 Add hierarchical seperator option to work with Xyce measurements. 2021-05-14 16:16:25 -07:00
Jesse Cirimelli-Low 0ba229afe5 Merge branch 'dev' into laptop_checkpoint 2021-05-07 19:06:17 -07:00
Jesse Cirimelli-Low 6d8411d19f use consistent amp spacing 2021-05-07 11:29:43 -07:00
mrg e995e61ea4 Fix Verilog module typo. Adjust RBL route. 2021-05-06 14:32:47 -07:00
mrg c057490923 Delay chain should have same height cells as control logic to align supplies. 2021-05-05 15:45:28 -07:00
mrg f677c8a88d Fix predecoder offset after relocating bank offset 2021-05-05 14:44:05 -07:00
mrg 120c4de5ad Fix placement of delay chain to align with control logic rows. 2021-05-05 14:21:53 -07:00
mrg 19ea33d43d Move delay line module down. 2021-05-04 16:42:42 -07:00
Jesse Cirimelli-Low 1b53d12df2 don't double count spare col 2021-05-04 01:52:51 -07:00
Jesse Cirimelli-Low d0e9de1f13 fix port data spare col 2021-05-04 00:41:20 -07:00
Jesse Cirimelli-Low 93b264bc4c allow spare col number override 2021-05-03 21:59:05 -07:00
Jesse Cirimelli-Low 14e087a5eb offset bank coordinates 2021-05-03 15:51:53 -07:00
Jesse Cirimelli-Low 4377619bf6 fixed port_data typo 2021-05-03 14:39:51 -07:00
Jesse Cirimelli-Low d3199ea70e Merge branch 'dev' into laptop_checkpoint 2021-05-03 12:53:31 -07:00
Jesse Cirimelli-Low 3a3da9e0d7 56 drc errors on col mux 1port 2021-05-02 21:49:09 -07:00
mrg fc6e6e1ec7 Add via when write driver supply is different layer 2021-04-28 15:16:26 -07:00
mrg 03e0c14ab2 Move write driver supply to m1 rather than pin layer 2021-04-28 10:13:33 -07:00
Jesse Cirimelli-Low 33e8bce79d dynamic predecode working 2021-04-25 01:22:36 -07:00
Jesse Cirimelli-Low 6ea4bdc5e5 Merge branch 'dev' into laptop_checkpoint 2021-04-23 22:50:23 -07:00
Jesse Cirimelli-Low 4ea0fcd068 support multi cell wide precharge cells 2021-04-23 22:49:29 -07:00
mrg 35fcb3f631 Abstracted LEF added. Params for array wordline layers. 2021-04-22 09:44:25 -07:00
mrg 15b0583ff2 Add custom parameter for wordline layer 2021-04-22 09:42:49 -07:00
mrg 419836411c Fix missing via for global wordlines. 2021-04-21 11:33:18 -07:00
mrg f45efe3db6 Abstracted LEF added. Params for array wordline layers. 2021-04-21 11:04:01 -07:00
mrg 584349c911 Add custom parameter for wordline layer 2021-04-21 11:04:01 -07:00
mrg 439003e203 Respect the bus spacing parameter in predecoder. 2021-04-19 10:51:16 -07:00
Jesse Cirimelli-Low e976c4043b Merge branch 'dev' into laptop_checkpoint 2021-04-14 15:58:06 -07:00
Jesse Cirimelli-Low 2f1d7b879f make bank compatable with sky130 2021-04-14 15:09:25 -07:00
mrg d609e4ea04 Reimplement trim options (except on unit tests). 
Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.
 2021-04-07 16:07:56 -07:00
mrg 31d3e6cb26 Change LWL layers 2021-04-07 16:07:56 -07:00
mrg 6e2f60353c Add wells to driver stages. Remove unnecessary height/center in control logic. 2021-03-25 10:00:24 -07:00
mrg 4a40e96f6d Control logic route changes. 
Move wl_en to top control signal.
Route wl_en directly to port_address.
Reorder input bus to bank.
 2021-03-24 14:32:10 -07:00
mrg 671470f5f2 Skywater changes. 
Default 1 thread and no temp subdirectory.
Add skywater setup/hold golden data
Add CLI option for simulation threads (-m)
Add compatibility mode option and nomodcheck for ngspice to speed up sky130 model loading.
Make subdir when using default /tmp dir.
Pass num_threads so temp subdirs are created.
 2021-03-22 15:48:14 -07:00
mrg b6f3fbdd1f Use OPTS.precharge instead of hard coded precharge. 2021-03-15 09:44:14 -07:00
mrg 1c6de4591d Remove vertical power pin vias. 2021-02-23 13:32:00 -08:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg 3ef56a29ea Bug fix 2021-01-13 13:56:22 -08:00
mrg bc9ab086e5 Clean up imports 2021-01-13 13:01:33 -08:00
mrg 01d312d65c Refactor add power pins 2021-01-13 10:57:12 -08:00
mrg 4fc0357282 Small readability edit to dff_buf 2021-01-04 13:16:23 -08:00
mrg 946ad66e7a Make width based on bitcell offsets, not number of columns 2020-12-18 09:22:10 -08:00
mrg 29880a0b5a Write mask and array supply pins on the ends 2020-12-17 15:25:19 -08:00
mrg e6ff73dbc1 Move supply pins for wmask and array to edge to avoid channel route congestion 2020-12-17 11:48:08 -08:00
mrg da48b8d98c Fix replica column bit index 2020-12-14 14:18:39 -08:00
mrg 47cc4cbfca Remove extra debug statement 2020-12-08 11:55:53 -08:00
mrg 0100ae57a3 Fix mirror with odd number of rows 2020-12-08 10:31:22 -08:00
mrg bad1274bdb Use internal name for col/row caps. gds ordered read enabled. 2020-12-03 10:03:47 -08:00
mrg 705d8e3105 Fix wrong via starting layer 2020-12-01 17:12:35 -08:00
mrg 583a70c24e Fix select layer for column mux array 2020-12-01 15:20:44 -08:00
mrg a31e0dab02 Remove via-to-via path width hack 2020-12-01 13:27:32 -08:00
mrg a5b5f7c22b Change layer away from wordlines 2020-12-01 11:33:55 -08:00
mrg 3829213afe Use and2_dec instead of buf_dec for better wldriver layout 2020-12-01 11:19:12 -08:00
mrg 4e10f6d8a6 Make cell/bitcell custom cell external accessible. 2020-11-24 12:01:00 -08:00
mrg 5ee3f4cc66 Many edits. 
Use internal vdd/gnd names.
Refactor getters in bitcell to base class.
Add BIAS signal type.
 2020-11-22 08:24:47 -08:00
mrg aa03eec943 Fix syntax error. 2020-11-21 07:16:45 -08:00
mrg 4c75bc003e Fix bounding box of replica array to include wordline grounds. 2020-11-21 07:03:59 -08:00
mrg 718c327527 Fix iteration bug with new type 2020-11-20 17:33:15 -08:00
mrg f729e9fca7 Fix new replica_bitcell_array refactor with end caps. Remove single port end cap exceptions. 2020-11-20 16:56:07 -08:00
mrg 27a652ac1b Fix bounding box of cap arrays 2020-11-20 16:54:53 -08:00
mrg 033111a5f3 Default to no hierarchical word lines. 2020-11-19 10:48:35 -08:00
mrg 86799ae3ff Small bug fixes related to new name mapping. 2020-11-16 13:42:42 -08:00
mrg 1d729e8f02 Move pin name mapping to layout class. 2020-11-16 11:04:03 -08:00
mrg 93e94e26ec Get vdd/gnd from properties if it is defined. 2020-11-16 10:14:37 -08:00
mrg 2f994b8c0a Change custom cells to use set_ports setter 2020-11-14 07:15:27 -08:00
mrg 1624d50ca9 Fix props bug again. 2020-11-13 20:35:19 -08:00
mrg e9420d57c2 Fix missing attributes 2020-11-13 19:04:26 -08:00
mrg a2b17a271c Port type order generated on the fly 2020-11-13 16:41:02 -08:00
mrg 01d191da40 clk_pin is redundant in DFFs 2020-11-13 16:23:27 -08:00
mrg 620e271562 Fix various typos and errors 2020-11-13 16:04:07 -08:00
mrg 8021430122 Fix pbitcell erros 2020-11-13 15:55:55 -08:00
mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 2020-11-13 10:07:40 -08:00
mrg bdda7c4f5f Add bl/br pins to dummy array 2020-11-12 12:38:09 -08:00
mrg 8be1436d51 Use OPTS.bitcell everywhere 2020-11-05 16:55:08 -08:00
mrg 1890385be1 Use custom cells when needed. 2020-11-03 11:58:25 -08:00
mrg cb3e9517bb Use cell_properties to override cell names 2020-11-03 07:06:01 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg fa89b73ef8 PR from mithro + other changable GDS file names 2020-11-02 16:00:16 -08:00
mrg 857f5cb136 Fix copy pasta: decoder to predecode 2020-10-28 15:46:10 -07:00
mrg 00cb8a28d9 Fix supply layer query 2020-10-28 10:36:13 -07:00
mrg acfec369d6 Add ptx cell properties 2020-10-28 09:54:15 -07:00
mrg 25495f3d94 getattr for bank parameters 2020-10-28 09:21:36 -07:00
mrg 611a4155b9 Add initial custom layer properties. 2020-10-27 15:11:04 -07:00
mrg dc991cbcab Use pin of pgate to figure out supply layer. 2020-10-26 15:54:16 -07:00
mrg 38ba5fc10d Use pin of pgate to figure out supply layer. 2020-10-26 15:53:22 -07:00
mrg 804814d18d Add bitlines to dummy modules 2020-10-16 13:43:56 -07:00
mrg 20be7caf98 Make conditional wl and bl for dummy rows/cols. 2020-10-15 13:56:37 -07:00
mrg 6a1f12b62d Refactored to utilize OOP 2020-10-13 11:07:31 -07:00
mrg 68d74737f7 Different bitcell and array supply pins 2020-10-13 07:41:21 -07:00
jcirimel 05667d784f move sky130 specific stuff to tech module lib 2020-10-13 04:48:10 -07:00
mrg c3d6be27be Fix argument name bug for remove wordlines 2020-10-08 16:58:38 -07:00
mrg 8d5db50062 Fix missing update for left RBL offset 2020-10-08 16:40:53 -07:00
mrg b0b15e8151 Fix indent bug that failed to create rbl wl pin labels. 2020-10-08 15:28:01 -07:00
mrg 01fe02bd90 Fixes to replica bitline array. 
Copy pasta error for right dummy column offset.
Put end_caps in try/except block.
PEP 8 formatting
 2020-10-08 14:53:44 -07:00
jcirimel 1e7ae06b7e fix extra wl in col end, work on bring wl pins out to row end array, TODO: mirror alternating row end 2020-10-08 05:32:03 -07:00
jcirimel d40c3588ed no wl for col end 2020-10-08 03:34:16 -07:00
jcirimel 4a1a7e637e merge in dev 2020-10-07 11:54:07 -07:00