mirror of https://github.com/VLSIDA/OpenRAM.git
PEP8 cleanup
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@ -5,10 +5,11 @@
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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import math
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import tech
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class vector():
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"""
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This is the vector class to represent the coordinate
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@ -369,11 +369,9 @@ class bank(design.design):
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3 * self.m2_pitch,
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drc("nwell_to_nwell"))
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def add_modules(self):
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""" Add all the modules using the class loader """
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local_array_size = OPTS.local_array_size
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if local_array_size > 0:
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@ -705,7 +703,7 @@ class bank(design.design):
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pitch=self.m3_pitch)
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self.copy_layout_pin(self.port_address_inst[0], "wl_en", self.prefix + "wl_en0")
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# Port 1
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if len(self.all_ports)==2:
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# The other control bus is routed up to two pitches above the bitcell array
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@ -302,4 +302,3 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
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Clears the bit exclusions
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"""
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self.bitcell_array.clear_exclude_bits()
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