mirror of https://github.com/VLSIDA/OpenRAM.git
Changed bitcell exclusion to instead exclude array instances to prevent issues of module exclusion affecting other modules.
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b408a871f9
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@ -473,7 +473,6 @@ class simulation():
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if not OPTS.use_pex or (OPTS.use_pex and OPTS.pex_exe[0] == "calibre"):
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self.graph.get_all_paths('{}{}'.format("clk", port),
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'{}{}_{}'.format(self.dout_name, port, self.probe_data))
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sen_with_port = self.get_sen_name(self.graph.all_paths)
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if sen_with_port.endswith(str(port)):
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self.sen_name = sen_with_port[:-len(str(port))]
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@ -530,9 +529,10 @@ class simulation():
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Creates timing graph to generate the timing paths for the SRAM output.
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"""
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#Make exclusions dependent on the bit being tested.
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self.sram.clear_exclude_bits() # Removes previous bit exclusions
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self.sram.graph_exclude_bits(self.wordline_row, self.bitline_column)
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port=0 #FIXME, port_data requires a port specification, assuming single port for now
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port=self.read_ports[0] #FIXME, port_data requires a port specification, assuming single port for now
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if self.words_per_row > 1:
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self.sram.graph_clear_column_mux(port)
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self.sram.graph_exclude_column_mux(self.bitline_column, port)
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@ -296,12 +296,12 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
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# We must also translate the global array column number to the local array column number
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local_col = targ_col - self.col_offsets[i - 1]
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for mod in self.local_mods:
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for mod, inst in zip(self.local_mods, self.local_insts):
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if mod == local_array:
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mod.graph_exclude_bits(targ_row, local_col)
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else:
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# Otherwise, we exclude ALL of the rows/columns
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mod.graph_exclude_bits()
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# Otherwise, exclude the local array inst
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self.graph_inst_exclude.add(inst)
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def graph_exclude_replica_col_bits(self):
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"""
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@ -338,6 +338,7 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
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"""
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for mod in self.local_mods:
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mod.clear_exclude_bits()
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self.init_graph_params()
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def graph_exclude_dffs(self):
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"""Exclude dffs from graph as they do not represent critical path"""
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