mirror of https://github.com/VLSIDA/OpenRAM.git
add vnb/vpb lvs correspondence points
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c599d8f62c
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@ -53,7 +53,6 @@ class design(hierarchy_design):
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(width, height) = utils.get_libcell_size(self.cell_name,
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GDS["unit"],
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layer[prop.boundary_layer])
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self.pin_map = utils.get_libcell_pins(self.pins,
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self.cell_name,
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GDS["unit"])
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@ -749,6 +749,7 @@ class VlsiLayout:
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Find all text labels and create a map to a list of shapes that
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they enclose on the given layer.
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"""
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# Get the labels on a layer in the root level
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labels = self.getTexts(lpp)
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@ -760,6 +761,12 @@ class VlsiLayout:
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label_coordinate = label.coordinates[0]
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user_coordinate = [x*self.units[0] for x in label_coordinate]
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pin_shapes = []
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try:
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from tech import layer_override
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if layer_override[label.textString]:
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shapes = self.getAllShapes((layer_override[label.textString], None))
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except:
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pass
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for boundary in shapes:
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if self.labelInRectangle(user_coordinate, boundary):
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pin_shapes.append((lpp, boundary))
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@ -161,8 +161,20 @@ class bitcell_base_array(design.design):
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row, col]
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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if row == 2: #add only 1 label per col
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for pin_name in ["vdd", "gnd"]:
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self.copy_layout_pin(inst, pin_name)
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if 'VPB' in self.cell_inst[row, col].mod.pins:
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self.add_label("gnd", inst.get_pin("vpb").layer, inst.get_pin("vpb").ll())
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if 'VNB' in self.cell_inst[row, col].mod.pins:
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try:
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from tech import layer_override
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if layer_override['VNB\x00']:
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inst.get_pin("vnb").layer = layer_override['VNB\x00']
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except:
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pass
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self.add_label("vdd", inst.get_pin("vnb").layer, inst.get_pin("vnb").ll())
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def _adjust_x_offset(self, xoffset, col, col_offset):
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tempx = xoffset
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