mirror of https://github.com/VLSIDA/OpenRAM.git
change col mux array poly routing from straight to 'L'
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@ -177,13 +177,16 @@ class column_mux_array(design.design):
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# height to connect the gate to the correct horizontal row
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# sel_height = self.get_pin("sel_{}".format(sel_index)).by()
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# use the y offset from the sel pin and the x offset from the gate
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offset = vector(gate_offset.x,
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self.get_pin("sel_{}".format(sel_index)).cy())
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bl_offset = offset + vector((self.mux_inst[col].get_pin("br_out").bc().x - self.mux_inst[col].get_pin("bl_out").bc().x)/2, 0)
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self.add_via_stack_center(from_layer="poly",
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to_layer=self.sel_layer,
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offset=offset,
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offset=bl_offset,
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directions=self.via_directions)
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self.add_path("poly", [offset, gate_offset])
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self.add_path("poly", [offset, gate_offset, bl_offset])
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def route_bitlines(self):
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""" Connect the output bit-lines to form the appropriate width mux """
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