merge in dev

README.md

@@ -29,7 +29,7 @@ things that need to be fixed.
 ## Dependencies
 
 The OpenRAM compiler has very few dependencies:
-+ [Ngspice] 26 (or later) or HSpice I-2013.12-1 (or later) or CustomSim 2017 (or later)
++ [Ngspice] 26 (or later) or HSpice I-2013.12-1 (or later) or CustomSim 2017 (or later) or [Xyce] 7.2 (or later)
 + Python 3.5 or higher
 + Various Python packages (pip install -r requirements.txt)
 
@@ -214,6 +214,7 @@ If I forgot to add you, please let me know!
 [Netgen]:                http://opencircuitdesign.com/netgen/
 [Qflow]:                 http://opencircuitdesign.com/qflow/history.html
 [Ngspice]:               http://ngspice.sourceforge.net/
+[Xyce]:                  http://xyce.sandia.gov/
 
 [OSUPDK]:                https://vlsiarch.ecen.okstate.edu/flow/
 [FreePDK45]:             https://www.eda.ncsu.edu/wiki/FreePDK45:Contents

compiler/Makefile

@@ -1,8 +1,8 @@
-TECH = scn4m_subm
+TECH = freepdk45
 CUR_DIR = $(shell pwd)
 TEST_DIR = ${CUR_DIR}/tests
 
-MAKEFLAGS += -j 1
+#MAKEFLAGS += -j 1
 
 # Library test
 LIBRARY_TESTS = $(shell find ${TEST_DIR} -name 0[1-2]*_test.py)
@@ -64,7 +64,35 @@ usage: ${USAGE_TESTS}
 
 $(ALL_TESTS):
 	python3 $@ -t ${TECH}
+OPENRAM_TECHS = $(subst :, ,$(OPENRAM_TECH))
+TECH_DIR := $(word 1, $(foreach dir,$(OPENRAM_TECHS),$(wildcard $(dir)/$(TECH))))
+CONFIG_DIR = $(OPENRAM_HOME)/model_configs
+MODEL_CONFIGS = $(wildcard $(CONFIG_DIR)/*.py)
+SIM_DIR = $(OPENRAM_HOME)/model_data/$(TECH)
+CSV_DIR = $(TECH_DIR)/sim_data
+OPTS = 
+# Characterize and perform DRC/LVS
+OPTS += -c 
+# Do not characterize or perform DRC/LVS
+OPTS += -n
+# Verbosity
+#OPTS += -v
+# Spice
+OPTS += -s hspice
 
+.PHONY: ${MODEL_CONFIGS}
+
+.PHONY: model
+
+model: $(MODEL_CONFIGS)
+	mkdir -p $(CSV_DIR)
+	python3 $(OPENRAM_HOME)/model_data_util.py $(SIM_DIR) $(CSV_DIR)
+	
+$(MODEL_CONFIGS):
+	$(eval bname=$(basename $(notdir $@)))
+	mkdir -p $(SIM_DIR)/$(bname)
+	-python3 $(OPENRAM_HOME)/openram.py $(OPTS) -p $(SIM_DIR)/$(bname) -o $(bname) -t $(TECH) $@ 2>&1 > /dev/null
+	
 clean:
 	find . -name \*.pyc -exec rm {} \;
 	find . -name \*~ -exec rm {} \;

compiler/base/hierarchy_design.py

@@ -132,7 +132,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
         for subinst, conns in zip(self.insts, self.conns):
             if subinst in self.graph_inst_exclude:
                 continue
-            subinst_name = inst_name + '.X' + subinst.name
+            subinst_name = inst_name + "{}x".format(OPTS.hier_seperator) + subinst.name
             subinst_ports = self.translate_nets(conns, port_dict, inst_name)
             subinst.mod.build_graph(graph, subinst_name, subinst_ports)
 
@@ -148,7 +148,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
         port_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
         debug.info(3, "Instance name={}".format(inst_name))
         for subinst, conns in zip(self.insts, self.conns):
-            subinst_name = inst_name + '.X' + subinst.name
+            subinst_name = inst_name + "{}x".format(OPTS.hier_seperator) + subinst.name
             subinst_ports = self.translate_nets(conns, port_dict, inst_name)
             for si_port, conn in zip(subinst_ports, conns):
                 # Only add for first occurrence
@@ -166,7 +166,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
             if conn in port_dict:
                 converted_conns.append(port_dict[conn])
             else:
-                converted_conns.append("{}.{}".format(inst_name, conn))
+                converted_conns.append("{0}{2}{1}".format(inst_name, conn, OPTS.hier_seperator))
         return converted_conns
 
     def add_graph_edges(self, graph, port_nets):

compiler/base/hierarchy_layout.py

@@ -41,7 +41,8 @@ class layout():
         
         self.width = None
         self.height = None
-        self.bounding_box = None
+        self.bounding_box = None # The rectangle shape
+        self.bbox = None # The ll, ur coords
         # Holds module/cell layout instances
         self.insts = []
         # Set of names to check for duplicates
@@ -1161,6 +1162,59 @@ class layout():
                                                   height=ur.y - ll.y,
                                                   width=ur.x - ll.x)
 
+        self.bbox = [self.bounding_box.ll(), self.bounding_box.ur()]
+
+    def get_bbox(self, side="all", big_margin=0, little_margin=0):
+        """
+        Get the bounding box from the GDS
+        """
+        gds_filename = OPTS.openram_temp + "temp.gds"
+        # If didn't specify a gds blockage file, write it out to read the gds
+        # This isn't efficient, but easy for now
+        # Load the gds file and read in all the shapes
+        self.gds_write(gds_filename)
+        layout = gdsMill.VlsiLayout(units=GDS["unit"])
+        reader = gdsMill.Gds2reader(layout)
+        reader.loadFromFile(gds_filename)
+        top_name = layout.rootStructureName
+
+        if not self.bbox:
+            # The boundary will determine the limits to the size
+            # of the routing grid
+            boundary = layout.measureBoundary(top_name)
+            # These must be un-indexed to get rid of the matrix type
+            ll = vector(boundary[0][0], boundary[0][1])
+            ur = vector(boundary[1][0], boundary[1][1])
+        else:
+            ll, ur = self.bbox
+
+        ll_offset = vector(0, 0)
+        ur_offset = vector(0, 0)
+        if side in ["ring", "top", "all"]:
+            ur_offset += vector(0, big_margin)
+        else:
+            ur_offset += vector(0, little_margin)
+        if side in ["ring", "bottom", "all"]:
+            ll_offset += vector(0, big_margin)
+        else:
+            ll_offset += vector(0, little_margin)
+        if side in ["ring", "left", "all"]:
+            ll_offset += vector(big_margin, 0)
+        else:
+            ll_offset += vector(little_margin, 0)
+        if side in ["ring", "right", "all"]:
+            ur_offset += vector(big_margin, 0)
+        else:
+            ur_offset += vector(little_margin, 0)
+        bbox = (ll - ll_offset, ur + ur_offset)
+        size = ur - ll
+        debug.info(1, "Size: {0} x {1} with perimeter big margin {2} little margin {3}".format(size.x,
+                                                                                               size.y,
+                                                                                               big_margin,
+                                                                                               little_margin))
+
+        return bbox
+
     def add_enclosure(self, insts, layer="nwell", extend=0, leftx=None, rightx=None, topy=None, boty=None):
         """
         Add a layer that surrounds the given instances. Useful
@@ -1345,7 +1399,182 @@ class layout():
                                                layer=layer,
                                                offset=peri_pin_loc)
 
-    def add_power_ring(self, bbox):
+    def add_dnwell(self, bbox=None, inflate=1):
+        """ Create a dnwell, along with nwell moat at border. """
+
+        if "dnwell" not in techlayer:
+            return
+
+        if not bbox:
+            bbox =  [self.find_lowest_coords(),
+                     self.find_highest_coords()]
+
+        # Find the corners
+        [ll, ur] = bbox
+
+        # Possibly inflate the bbox
+        nwell_offset = vector(self.nwell_width, self.nwell_width)
+        ll -= nwell_offset.scale(inflate, inflate)
+        ur += nwell_offset.scale(inflate, inflate)
+
+        # Other corners
+        ul = vector(ll.x, ur.y)
+        lr = vector(ur.x, ll.y)
+
+        # Add the dnwell
+        self.add_rect("dnwell",
+                      offset=ll,
+                      height=ur.y - ll.y,
+                      width=ur.x - ll.x)
+
+        # Add the moat
+        self.add_path("nwell", [ll, lr, ur, ul, ll - vector(0, 0.5 * self.nwell_width)])
+
+        # Add the taps
+        layer_stack = self.active_stack
+        tap_spacing = 2
+        nwell_offset = vector(self.nwell_width, self.nwell_width)
+
+        # Every nth tap is connected to gnd
+        period = 5
+
+        # BOTTOM
+        count = 0
+        loc = ll + nwell_offset.scale(tap_spacing, 0)
+        end_loc = lr - nwell_offset.scale(tap_spacing, 0)
+        while loc.x < end_loc.x:
+            self.add_via_center(layers=layer_stack,
+                                offset=loc,
+                                implant_type="n",
+                                well_type="n")
+            if count % period:
+                self.add_via_stack_center(from_layer="li",
+                                          to_layer="m1",
+                                          offset=loc)
+            else:
+                self.add_power_pin(name="gnd",
+                                   loc=loc,
+                                   start_layer="li")
+            count += 1
+            loc += nwell_offset.scale(tap_spacing, 0)
+
+        # TOP
+        count = 0
+        loc = ul + nwell_offset.scale(tap_spacing, 0)
+        end_loc = ur - nwell_offset.scale(tap_spacing, 0)
+        while loc.x < end_loc.x:
+            self.add_via_center(layers=layer_stack,
+                                offset=loc,
+                                implant_type="n",
+                                well_type="n")
+            if count % period:
+                self.add_via_stack_center(from_layer="li",
+                                          to_layer="m1",
+                                          offset=loc)
+            else:
+                self.add_power_pin(name="gnd",
+                                   loc=loc,
+                                   start_layer="li")
+            count += 1
+            loc += nwell_offset.scale(tap_spacing, 0)
+
+        # LEFT
+        count = 0
+        loc = ll + nwell_offset.scale(0, tap_spacing)
+        end_loc = ul - nwell_offset.scale(0, tap_spacing)
+        while loc.y < end_loc.y:
+            self.add_via_center(layers=layer_stack,
+                                offset=loc,
+                                implant_type="n",
+                                well_type="n")
+            if count % period:
+                self.add_via_stack_center(from_layer="li",
+                                          to_layer="m2",
+                                          offset=loc)
+            else:
+                self.add_power_pin(name="gnd",
+                                   loc=loc,
+                                   start_layer="li")
+            count += 1
+            loc += nwell_offset.scale(0, tap_spacing)
+
+        # RIGHT
+        count = 0
+        loc = lr + nwell_offset.scale(0, tap_spacing)
+        end_loc = ur - nwell_offset.scale(0, tap_spacing)
+        while loc.y < end_loc.y:
+            self.add_via_center(layers=layer_stack,
+                                offset=loc,
+                                implant_type="n",
+                                well_type="n")
+            if count % period:
+                self.add_via_stack_center(from_layer="li",
+                                          to_layer="m2",
+                                          offset=loc)
+            else:
+                self.add_power_pin(name="gnd",
+                                   loc=loc,
+                                   start_layer="li")
+            count += 1
+            loc += nwell_offset.scale(0, tap_spacing)
+
+        # Add the gnd ring
+        self.add_ring([ll, ur])
+
+    def add_ring(self, bbox=None, width_mult=8, offset=0):
+        """
+        Add a ring around the bbox
+        """
+        # Ring size/space/pitch
+        wire_width = self.m2_width * width_mult
+        half_width = 0.5 * wire_width
+        wire_space = self.m2_space
+        wire_pitch = wire_width + wire_space
+
+        # Find the corners
+        if not bbox:
+            bbox =  [self.find_lowest_coords(),
+                     self.find_highest_coords()]
+
+        [ll, ur] = bbox
+        ul = vector(ll.x, ur.y)
+        lr = vector(ur.x, ll.y)
+        ll += vector(-offset * wire_pitch,
+                     -offset * wire_pitch)
+        lr += vector(offset * wire_pitch,
+                     -offset * wire_pitch)
+        ur += vector(offset * wire_pitch,
+                     offset * wire_pitch)
+        ul += vector(-offset * wire_pitch,
+                     offset * wire_pitch)
+
+        half_offset = vector(half_width, half_width)
+        self.add_path("m1", [ll - half_offset.scale(1, 0), lr + half_offset.scale(1, 0)], width=wire_width)
+        self.add_path("m1", [ul - half_offset.scale(1, 0), ur + half_offset.scale(1, 0)], width=wire_width)
+        self.add_path("m2", [ll - half_offset.scale(0, 1), ul + half_offset.scale(0, 1)], width=wire_width)
+        self.add_path("m2", [lr - half_offset.scale(0, 1), ur + half_offset.scale(0, 1)], width=wire_width)
+
+        # Find the number of vias for this pitch
+        supply_vias = 1
+        from sram_factory import factory
+        while True:
+            c = factory.create(module_type="contact",
+                               layer_stack=self.m1_stack,
+                               dimensions=(supply_vias, supply_vias))
+            if c.second_layer_width < wire_width and c.second_layer_height < wire_width:
+                supply_vias += 1
+            else:
+                supply_vias -= 1
+                break
+
+        via_points = [ll, lr, ur, ul]
+        for pt in via_points:
+            self.add_via_center(layers=self.m1_stack,
+                                offset=pt,
+                                size=(supply_vias,
+                                      supply_vias))
+
+    def add_power_ring(self):
         """
         Create vdd and gnd power rings around an area of the bounding box
         argument. Must have a supply_rail_width and supply_rail_pitch
@@ -1354,7 +1583,7 @@ class layout():
         modules..
         """
 
-        [ll, ur] = bbox
+        [ll, ur] = self.bbox
 
         supply_rail_spacing = self.supply_rail_pitch - self.supply_rail_width
         height = (ur.y - ll.y) + 3 * self.supply_rail_pitch - supply_rail_spacing

compiler/base/lef.py

@@ -110,24 +110,27 @@ class lef:
 
         # For each pin, remove the blockage and add the pin
         for pin_name in self.pins:
-            pin = self.get_pin(pin_name)
-            inflated_pin = pin.inflated_pin(multiple=1)
-            another_iteration_needed = True
-            while another_iteration_needed:
-                another_iteration_needed = False
-                old_blockages = list(self.blockages[pin.layer])
-                for blockage in old_blockages:
-                    if blockage.overlaps(inflated_pin):
-                        intersection_shape = blockage.intersection(inflated_pin)
-                        # If it is zero area, don't add the pin
-                        if intersection_shape[0][0]==intersection_shape[1][0] or intersection_shape[0][1]==intersection_shape[1][1]:
-                            continue
-                        another_iteration_needed = True
-                        # Remove the old blockage and add the new ones
-                        self.blockages[pin.layer].remove(blockage)
-                        intersection_pin = pin_layout("", intersection_shape, inflated_pin.layer)
-                        new_blockages = blockage.cut(intersection_pin)
-                        self.blockages[pin.layer].extend(new_blockages)
+            pins = self.get_pins(pin_name)
+            for pin in pins:
+                inflated_pin = pin.inflated_pin(multiple=2)
+                continue_fragmenting = True
+                while continue_fragmenting:
+                    continue_fragmenting = False
+                    old_blockages = list(self.blockages[pin.layer])
+                    for blockage in old_blockages:
+                        if blockage.overlaps(inflated_pin):
+                            intersection_shape = blockage.intersection(inflated_pin)
+                            # If it is zero area, don't split the blockage
+                            if intersection_shape[0][0]==intersection_shape[1][0] or intersection_shape[0][1]==intersection_shape[1][1]:
+                                continue
+
+                            # Remove the old blockage and add the new ones
+                            self.blockages[pin.layer].remove(blockage)
+                            intersection_pin = pin_layout("", intersection_shape, inflated_pin.layer)
+                            new_blockages = blockage.cut(intersection_pin)
+                            self.blockages[pin.layer].extend(new_blockages)
+                            # We split something so make another pass
+                            continue_fragmenting = True
 
     def lef_write_header(self):
         """ Header of LEF file """

compiler/base/pin_layout.py

@@ -606,7 +606,9 @@ class pin_layout:
                 # Don't add the existing shape in if it overlaps the pin shape
                 if new_shape.contains(shape):
                     continue
-                new_shapes.append(new_shape)
+                # Only add non-zero shapes
+                if new_shape.area() > 0:
+                    new_shapes.append(new_shape)
 
         return new_shapes
 

compiler/base/verilog.py

@@ -6,6 +6,7 @@
 # All rights reserved.
 #
 import math
+from tech import spice
 
 
 class verilog:
@@ -28,10 +29,19 @@ class verilog:
         else:
             self.vf.write("\n")
 
+        try:
+            self.vdd_name = spice["power"]
+        except KeyError:
+            self.vdd_name = "vdd"
+        try:
+            self.gnd_name = spice["ground"]
+        except KeyError:
+            self.gnd_name = "gnd"
+            
         self.vf.write("module {0}(\n".format(self.name))
         self.vf.write("`ifdef USE_POWER_PINS\n")
-        self.vf.write("    vdd,\n")
-        self.vf.write("    gnd,\n")
+        self.vf.write("    {},\n".format(self.vdd_name))
+        self.vf.write("    {},\n".format(self.gnd_name))
         self.vf.write("`endif\n")
         
         for port in self.all_ports:
@@ -71,8 +81,8 @@ class verilog:
         self.vf.write("\n")
 
         self.vf.write("`ifdef USE_POWER_PINS\n")
-        self.vf.write("    inout vdd;\n")
-        self.vf.write("    inout gnd;\n")
+        self.vf.write("    inout {};\n".format(self.vdd_name))
+        self.vf.write("    inout {};\n".format(self.gnd_name))
         self.vf.write("`endif\n")
         
         for port in self.all_ports:

compiler/characterizer/__init__.py

@@ -24,14 +24,22 @@ debug.info(1, "Initializing characterizer...")
 OPTS.spice_exe = ""
 
 if not OPTS.analytical_delay:
-    debug.info(1, "Finding spice simulator.")
-
     if OPTS.spice_name != "":
+        # Capitalize Xyce
+        if OPTS.spice_name == "xyce":
+            OPTS.spice_name = "Xyce"
         OPTS.spice_exe=find_exe(OPTS.spice_name)
         if OPTS.spice_exe=="" or OPTS.spice_exe==None:
             debug.error("{0} not found. Unable to perform characterization.".format(OPTS.spice_name), 1)
     else:
-        (OPTS.spice_name, OPTS.spice_exe) = get_tool("spice", ["ngspice", "ngspice.exe", "hspice", "xa"])
+        (OPTS.spice_name, OPTS.spice_exe) = get_tool("spice", ["Xyce", "ngspice", "ngspice.exe", "hspice", "xa"])
+
+    if OPTS.spice_name in ["Xyce", "xyce"]:
+        (OPTS.mpi_name, OPTS.mpi_exe) = get_tool("mpi", ["mpirun"])
+        OPTS.hier_seperator = ":"
+    else:
+        OPTS.mpi_name = None
+        OPTS.mpi_exe = ""
 
     # set the input dir for spice files if using ngspice
     if OPTS.spice_name == "ngspice":
@@ -39,6 +47,12 @@ if not OPTS.analytical_delay:
 
     if OPTS.spice_exe == "":
         debug.error("No recognizable spice version found. Unable to perform characterization.", 1)
+    else:
+        debug.info(1, "Finding spice simulator: {} ({})".format(OPTS.spice_name, OPTS.spice_exe))
+        if OPTS.mpi_name:
+            debug.info(1, "MPI for spice simulator: {} ({})".format(OPTS.mpi_name, OPTS.mpi_exe))
+        debug.info(1, "Simulation threads: {}".format(OPTS.num_sim_threads))
+
 else:
     debug.info(1, "Analytical model enabled.")
 

compiler/characterizer/analytical_util.py

@@ -14,7 +14,7 @@ import os
 
 process_transform = {'SS':0.0, 'TT': 0.5, 'FF':1.0}
 
-def get_data_names(file_name):
+def get_data_names(file_name, exclude_area=True):
     """
     Returns just the data names in the first row of the CSV
     """
@@ -25,8 +25,18 @@ def get_data_names(file_name):
         # reader is iterable not a list, probably  a better way to do this
         for row in csv_reader:
             # Return names from first row
-            return row[0].split(',')
-    
+            names = row[0].split(',')
+            break
+    if exclude_area:
+        try:
+            area_ind = names.index('area')
+        except ValueError:
+            area_ind = -1
+            
+        if area_ind != -1:    
+            names = names[:area_ind] + names[area_ind+1:]
+    return names        
+            
 def get_data(file_name):
     """
     Returns data in CSV as lists of features
@@ -35,24 +45,33 @@ def get_data(file_name):
     with open(file_name, newline='') as csvfile:
         csv_reader = csv.reader(csvfile, delimiter=' ', quotechar='|')
         row_iter = 0
+        removed_items = 1
         for row in csv_reader:
             row_iter += 1
             if row_iter == 1:
                 feature_names = row[0].split(',')
-                input_list = [[] for _ in feature_names]
-                scaled_list = [[] for _ in feature_names]
-                
+                input_list = [[] for _ in range(len(feature_names)-removed_items)]
+                try:
+                    # Save to remove area
+                    area_ind = feature_names.index('area')
+                except ValueError:
+                    area_ind = -1
+                    
                 try:
                     process_ind = feature_names.index('process')
                 except:
                     debug.error('Process not included as a feature.')
                 continue
+                
+                
 
             data = []
             split_str = row[0].split(',')
             for i in range(len(split_str)):
                 if i == process_ind:
                     data.append(process_transform[split_str[i]])
+                elif i == area_ind:
+                    continue
                 else:
                     data.append(float(split_str[i]))
 
@@ -227,9 +246,8 @@ def get_scaled_data(file_name):
     
     # Data is scaled by max/min and data format is changed to points vs feature lists
     self_scaled_data = scale_data_and_transform(all_data)
-    samples = np.asarray(self_scaled_data)
-    features, labels = samples[:, :-1], samples[:,-1:]
-    return features, labels
+    data_np = np.asarray(self_scaled_data)
+    return data_np
 
 def scale_data_and_transform(data):
     """
@@ -275,16 +293,13 @@ def unscale_data(data, file_path, pos=None):
         
     # Hard coded to only convert the last max/min (i.e. the label of the data) 
     if pos == None:
-        maxs,mins,avgs = [maxs[-1]],[mins[-1]],[avgs[-1]]
+        maxs,mins,avgs = maxs[-1],mins[-1],avgs[-1]
     else:
-        maxs,mins,avgs = [maxs[pos]],[mins[pos]],[avgs[pos]]
+        maxs,mins,avgs = maxs[pos],mins[pos],avgs[pos]
     unscaled_data = []
     for data_row in data:
-        unscaled_row = []
-        for val, cur_max, cur_min in zip(data_row, maxs, mins):
-            unscaled_val = val*(cur_max-cur_min) + cur_min
-            unscaled_row.append(unscaled_val)
-        unscaled_data.append(unscaled_row)   
+        unscaled_val = data_row*(maxs-mins) + mins
+        unscaled_data.append(unscaled_val) 
 
     return unscaled_data
     

compiler/characterizer/charutils.py

@@ -11,21 +11,26 @@ import debug
 from globals import OPTS
 
 
-def relative_compare(value1,value2,error_tolerance=0.001):
+def relative_compare(value1, value2, error_tolerance=0.001):
     """ This is used to compare relative values for convergence. """
-    return (abs(value1 - value2) / abs(max(value1,value2)) <= error_tolerance)
+    return (abs(value1 - value2) / abs(max(value1, value2)) <= error_tolerance)
 
 
 def parse_spice_list(filename, key):
     """Parses a hspice output.lis file for a key value"""
+
+    lower_key = key.lower()
+
     if OPTS.spice_name == "xa" :
         # customsim has a different output file name
         full_filename="{0}xa.meas".format(OPTS.openram_temp)
     elif OPTS.spice_name == "spectre":
         full_filename = os.path.join(OPTS.openram_temp, "delay_stim.measure")
+    elif OPTS.spice_name in ["Xyce", "xyce"]:
+        full_filename = os.path.join(OPTS.openram_temp, "spice_stdout.log")
     else:
         # ngspice/hspice using a .lis file
-        full_filename="{0}{1}.lis".format(OPTS.openram_temp, filename)
+        full_filename = "{0}{1}.lis".format(OPTS.openram_temp, filename)
 
     try:
         f = open(full_filename, "r")
@@ -33,31 +38,34 @@ def parse_spice_list(filename, key):
         debug.error("Unable to open spice output file: {0}".format(full_filename),1)
         debug.archive()
         
-    contents = f.read()
+    contents = f.read().lower()
     f.close()
     # val = re.search(r"{0}\s*=\s*(-?\d+.?\d*\S*)\s+.*".format(key), contents)
-    val = re.search(r"{0}\s*=\s*(-?\d+.?\d*[e]?[-+]?[0-9]*\S*)\s+.*".format(key), contents)
+    val = re.search(r"{0}\s*=\s*(-?\d+.?\d*[e]?[-+]?[0-9]*\S*)\s+.*".format(lower_key), contents)
     if val != None:
-        debug.info(4, "Key = " + key + " Val = " + val.group(1))
+        debug.info(4, "Key = " + lower_key + " Val = " + val.group(1))
         return convert_to_float(val.group(1))
     else:
         return "Failed"
 
-def round_time(time,time_precision=3):
+
+def round_time(time, time_precision=3):
     # times are in ns, so this is how many digits of precision
     # 3 digits = 1ps
     # 4 digits = 0.1ps
     # etc.
-    return round(time,time_precision)
+    return round(time, time_precision)
 
-def round_voltage(voltage,voltag_precision=5):
+
+def round_voltage(voltage, voltage_precision=5):
     # voltages are in volts
     # 3 digits = 1mv
     # 4 digits = 0.1mv
     # 5 digits = 0.01mv
     # 6 digits = 1uv
     # etc
-    return round(voltage,voltage_precision)
+    return round(voltage, voltage_precision)
+
 
 def convert_to_float(number):
     """Converts a string into a (float) number; also converts units(m,u,n,p)"""
@@ -84,7 +92,7 @@ def convert_to_float(number):
                 'n': lambda x: x * 0.000000001,  # nano
                 'p': lambda x: x * 0.000000000001,  # pico
                 'f': lambda x: x * 0.000000000000001  # femto
-                }[unit.group(2)](float(unit.group(1)))
+            }[unit.group(2)](float(unit.group(1)))
 
     # if we weren't able to convert it to a float then error out
     if not type(float_value)==float:
@@ -92,9 +100,10 @@ def convert_to_float(number):
 
     return float_value
 
+
 def check_dict_values_is_float(dict):
     """Checks if all the values are floats. Useful for checking failed Spice measurements."""
     for key, value in dict.items():
-            if type(value)!=float:
-                return False
+        if type(value)!=float:
+            return False
     return True

compiler/characterizer/delay.py

@@ -69,7 +69,7 @@ class delay(simulation):
             for meas in meas_list:
                 name = meas.name.lower()
                 debug.check(name not in name_set, ("SPICE measurements must have unique names. "
-                                                   "Duplicate name={}").format(name))
+                                                   "Duplicate name={0}").format(name))
                 name_set.add(name)
 
     def create_read_port_measurement_objects(self):
@@ -77,7 +77,7 @@ class delay(simulation):
 
         self.read_lib_meas = []
         self.clk_frmt = "clk{0}" # Unformatted clock name
-        targ_name = "{0}{1}_{2}".format(self.dout_name, "{}", self.probe_data) # Empty values are the port and probe data bit
+        targ_name = "{0}{{}}_{1}".format(self.dout_name, self.probe_data) # Empty values are the port and probe data bit
         self.delay_meas = []
         self.delay_meas.append(delay_measure("delay_lh", self.clk_frmt, targ_name, "RISE", "RISE", measure_scale=1e9))
         self.delay_meas[-1].meta_str = sram_op.READ_ONE # Used to index time delay values when measurements written to spice file.
@@ -166,7 +166,7 @@ class delay(simulation):
         self.dout_volt_meas = []
         for meas in self.delay_meas:
             # Output voltage measures
-            self.dout_volt_meas.append(voltage_at_measure("v_{}".format(meas.name),
+            self.dout_volt_meas.append(voltage_at_measure("v_{0}".format(meas.name),
                                                            meas.targ_name_no_port))
             self.dout_volt_meas[-1].meta_str = meas.meta_str
 
@@ -186,7 +186,7 @@ class delay(simulation):
         self.read_bit_meas = {bit_polarity.NONINVERTING: [], bit_polarity.INVERTING: []}
         meas_cycles = (sram_op.READ_ZERO, sram_op.READ_ONE)
         for cycle in meas_cycles:
-            meas_tag = "a{}_b{}_{}".format(self.probe_address, self.probe_data, cycle.name)
+            meas_tag = "a{0}_b{1}_{2}".format(self.probe_address, self.probe_data, cycle.name)
             single_bit_meas = self.get_bit_measures(meas_tag, self.probe_address, self.probe_data)
             for polarity, meas in single_bit_meas.items():
                 meas.meta_str = cycle
@@ -200,7 +200,7 @@ class delay(simulation):
         self.write_bit_meas = {bit_polarity.NONINVERTING: [], bit_polarity.INVERTING: []}
         meas_cycles = (sram_op.WRITE_ZERO, sram_op.WRITE_ONE)
         for cycle in meas_cycles:
-            meas_tag = "a{}_b{}_{}".format(self.probe_address, self.probe_data, cycle.name)
+            meas_tag = "a{0}_b{1}_{2}".format(self.probe_address, self.probe_data, cycle.name)
             single_bit_meas = self.get_bit_measures(meas_tag, self.probe_address, self.probe_data)
             for polarity, meas in single_bit_meas.items():
                 meas.meta_str = cycle
@@ -219,20 +219,20 @@ class delay(simulation):
         (cell_name, cell_inst) = self.sram.get_cell_name(self.sram.name, bit_row, bit_col)
         storage_names = cell_inst.mod.get_storage_net_names()
         debug.check(len(storage_names) == 2, ("Only inverting/non-inverting storage nodes"
-                                              "supported for characterization. Storage nets={}").format(storage_names))
+                                              "supported for characterization. Storage nets={0}").format(storage_names))
         if OPTS.use_pex and OPTS.pex_exe[0] != "calibre":
             bank_num = self.sram.get_bank_num(self.sram.name, bit_row, bit_col)
             q_name = "bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, bit_row, bit_col)
             qbar_name = "bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, bit_row, bit_col)
         else:
-            q_name = cell_name + '.' + str(storage_names[0])
-            qbar_name = cell_name + '.' + str(storage_names[1])
+            q_name = cell_name + OPTS.hier_seperator + str(storage_names[0])
+            qbar_name = cell_name + OPTS.hier_seperator + str(storage_names[1])
 
         # Bit measures, measurements times to be defined later. The measurement names must be unique
         # but they is enforced externally. {} added to names to differentiate between ports allow the
         # measurements are independent of the ports
-        q_meas = voltage_at_measure("v_q_{}".format(meas_tag), q_name)
-        qbar_meas = voltage_at_measure("v_qbar_{}".format(meas_tag), qbar_name)
+        q_meas = voltage_at_measure("v_q_{0}".format(meas_tag), q_name)
+        qbar_meas = voltage_at_measure("v_qbar_{0}".format(meas_tag), qbar_name)
 
         return {bit_polarity.NONINVERTING: q_meas, bit_polarity.INVERTING: qbar_meas}
         
@@ -242,15 +242,15 @@ class delay(simulation):
         # FIXME: There should be a default_read_port variable in this case, pathing is done with this
         # but is never mentioned otherwise
         port = self.read_ports[0]
-        sen_and_port = self.sen_name+str(port)
+        sen_and_port = self.sen_name + str(port)
         bl_and_port = self.bl_name.format(port) # bl_name contains a '{}' for the port
         # Isolate the s_en and bitline paths
-        debug.info(1, "self.bl_name = {}".format(self.bl_name))
-        debug.info(1, "self.graph.all_paths = {}".format(self.graph.all_paths))
+        debug.info(1, "self.bl_name = {0}".format(self.bl_name))
+        debug.info(1, "self.graph.all_paths = {0}".format(self.graph.all_paths))
         sen_paths = [path for path in self.graph.all_paths if sen_and_port in path]
         bl_paths = [path for path in self.graph.all_paths if bl_and_port in path]
-        debug.check(len(sen_paths)==1, 'Found {} paths which contain the s_en net.'.format(len(sen_paths)))
-        debug.check(len(bl_paths)==1, 'Found {} paths which contain the bitline net.'.format(len(bl_paths)))
+        debug.check(len(sen_paths)==1, 'Found {0} paths which contain the s_en net.'.format(len(sen_paths)))
+        debug.check(len(bl_paths)==1, 'Found {0} paths which contain the bitline net.'.format(len(bl_paths)))
         sen_path = sen_paths[0]
         bitline_path = bl_paths[0]
         
@@ -286,11 +286,11 @@ class delay(simulation):
         
         # Create the measurements
         path_meas = []
-        for i in range(len(path)-1):
-            cur_net, next_net = path[i], path[i+1]
-            cur_dir, next_dir = path_dirs[i], path_dirs[i+1]
-            meas_name = "delay_{}_to_{}".format(cur_net, next_net)
-            if i+1 != len(path)-1:
+        for i in range(len(path) - 1):
+            cur_net, next_net = path[i], path[i + 1]
+            cur_dir, next_dir = path_dirs[i], path_dirs[i + 1]
+            meas_name = "delay_{0}_to_{1}".format(cur_net, next_net)
+            if i + 1 != len(path) - 1:
                 path_meas.append(delay_measure(meas_name, cur_net, next_net, cur_dir, next_dir, measure_scale=1e9, has_port=False))
             else: # Make the last measurement always measure on FALL because is a read 0
                 path_meas.append(delay_measure(meas_name, cur_net, next_net, cur_dir, "FALL", measure_scale=1e9, has_port=False))
@@ -309,13 +309,13 @@ class delay(simulation):
         # Convert to booleans based on function of modules (inverting/non-inverting)
         mod_type_bools = [mod.is_non_inverting() for mod in edge_mods]
         
-        #FIXME: obtuse hack to differentiate s_en input from bitline in sense amps
+        # FIXME: obtuse hack to differentiate s_en input from bitline in sense amps
         if self.sen_name in path:
             # Force the sense amp to be inverting for s_en->DOUT. 
             # bitline->DOUT is non-inverting, but the module cannot differentiate inputs.
             s_en_index = path.index(self.sen_name)
             mod_type_bools[s_en_index] = False
-            debug.info(2,'Forcing sen->dout to be inverting.')
+            debug.info(2, 'Forcing sen->dout to be inverting.')
         
         # Use these to determine direction list assuming delay start on neg. edge of clock (FALL)
         # Also, use shorthand that 'FALL' == False, 'RISE' == True to simplify logic
@@ -493,7 +493,7 @@ class delay(simulation):
         elif meas_type is voltage_at_measure:
             variant_tuple = self.get_volt_at_measure_variants(port, measure_obj)
         else:
-            debug.error("Input function not defined for measurement type={}".format(meas_type))
+            debug.error("Input function not defined for measurement type={0}".format(meas_type))
         # Removes port input from any object which does not use it. This shorthand only works if
         # the measurement has port as the last input. Could be implemented by measurement type or
         # remove entirely from measurement classes.
@@ -515,7 +515,7 @@ class delay(simulation):
         elif delay_obj.meta_str == sram_op.READ_ONE:
             meas_cycle_delay = self.cycle_times[self.measure_cycles[port][delay_obj.meta_str]]
         else:
-            debug.error("Unrecognized delay Index={}".format(delay_obj.meta_str),1)
+            debug.error("Unrecognized delay Index={0}".format(delay_obj.meta_str), 1)
 
         # These measurements have there time further delayed to the neg. edge of the clock.
         if delay_obj.meta_add_delay:
@@ -587,20 +587,20 @@ class delay(simulation):
         # Output some comments to aid where cycles start and
         # what is happening
         for comment in self.cycle_comments:
-            self.sf.write("* {}\n".format(comment))
+            self.sf.write("* {0}\n".format(comment))
 
         self.sf.write("\n")
         for read_port in self.targ_read_ports:
-            self.sf.write("* Read ports {}\n".format(read_port))
+            self.sf.write("* Read ports {0}\n".format(read_port))
             self.write_delay_measures_read_port(read_port)
 
         for write_port in self.targ_write_ports:
-            self.sf.write("* Write ports {}\n".format(write_port))
+            self.sf.write("* Write ports {0}\n".format(write_port))
             self.write_delay_measures_write_port(write_port)
 
     def load_pex_net(self, net: str):
         from subprocess import check_output, CalledProcessError
-        prefix = (self.sram_instance_name + ".").lower()
+        prefix = (self.sram_instance_name + OPTS.hier_seperator).lower()
         if not net.lower().startswith(prefix) or not OPTS.use_pex or not OPTS.calibre_pex:
             return net
         original_net = net
@@ -640,26 +640,41 @@ class delay(simulation):
         col = self.bitline_column
         row = self.wordline_row
         for port in set(self.targ_read_ports + self.targ_write_ports):
-            probe_nets.add("WEB{}".format(port))
-            probe_nets.add("{}.w_en{}".format(self.sram_instance_name, port))
-            probe_nets.add("{0}.Xbank0.Xport_data{1}.Xwrite_driver_array{1}.Xwrite_driver{2}.en_bar".format(
-                self.sram_instance_name, port, self.bitline_column))
-            probe_nets.add("{}.Xbank0.br_{}_{}".format(self.sram_instance_name, port,
-                                                       self.bitline_column))
+            probe_nets.add("WEB{0}".format(port))
+            probe_nets.add("{0}{2}w_en{1}".format(self.sram_instance_name, port, OPTS.hier_seperator))
+            probe_nets.add("{0}{3}Xbank0{3}Xport_data{1}{3}Xwrite_driver_array{1}{3}Xwrite_driver{2}{3}en_bar".format(self.sram_instance_name,
+                                                                                                                      port,
+                                                                                                                      self.bitline_column,
+                                                                                                                      OPTS.hier_seperator))
+            probe_nets.add("{0}{3}Xbank0{3}br_{1}_{2}".format(self.sram_instance_name,
+                                                              port,
+                                                              self.bitline_column,
+                                                              OPTS.hier_seperator))
             if not OPTS.use_pex:
                 continue
             probe_nets.add(
-                "{0}.vdd_Xbank0_Xbitcell_array_xbitcell_array_xbit_r{1}_c{2}".format(sram_name, row, col - 1))
+                "{0}{3}vdd_Xbank0_Xbitcell_array_xbitcell_array_xbit_r{1}_c{2}".format(sram_name,
+                                                                                       row,
+                                                                                       col - 1,
+                                                                                       OPTS.hier_seperator))
             probe_nets.add(
-                "{0}.p_en_bar{1}_Xbank0_Xport_data{1}_Xprecharge_array{1}_Xpre_column_{2}".format(sram_name, port, col))
+                "{0}{3}p_en_bar{1}_Xbank0_Xport_data{1}_Xprecharge_array{1}_Xpre_column_{2}".format(sram_name,
+                                                                                                    port,
+                                                                                                    col,
+                                                                                                    OPTS.hier_seperator))
             probe_nets.add(
-                "{0}.vdd_Xbank0_Xport_data{1}_Xprecharge_array{1}_xpre_column_{2}".format(sram_name, port, col))
-            probe_nets.add("{0}.vdd_Xbank0_Xport_data{1}_Xwrite_driver_array{1}_xwrite_driver{2}".format(sram_name,
-                                                                                                         port, col))
+                "{0}{3}vdd_Xbank0_Xport_data{1}_Xprecharge_array{1}_xpre_column_{2}".format(sram_name,
+                                                                                            port,
+                                                                                            col,
+                                                                                            OPTS.hier_seperator))
+            probe_nets.add("{0}{3}vdd_Xbank0_Xport_data{1}_Xwrite_driver_array{1}_xwrite_driver{2}".format(sram_name,
+                                                                                                           port,
+                                                                                                           col,
+                                                                                                           OPTS.hier_seperator))
         probe_nets.update(self.measurement_nets)
         for net in probe_nets:
-            debug.info(2, "Probe: {}".format(net))
-            self.sf.write(".plot V({}) \n".format(self.load_pex_net(net)))
+            debug.info(2, "Probe: {0}".format(net))
+            self.sf.write(".plot V({0}) \n".format(self.load_pex_net(net)))
 
     def write_power_measures(self):
         """
@@ -778,7 +793,7 @@ class delay(simulation):
             if not self.check_bit_measures(self.write_bit_meas, port):
                 return(False, {})
 
-            debug.info(2, "Checking write values for port {}".format(port))
+            debug.info(2, "Checking write values for port {0}".format(port))
             write_port_dict = {}
             for measure in self.write_lib_meas:
                 write_port_dict[measure.name] = measure.retrieve_measure(port=port)
@@ -792,7 +807,7 @@ class delay(simulation):
             if not self.check_bit_measures(self.read_bit_meas, port):
                 return(False, {})
 
-            debug.info(2, "Checking read delay values for port {}".format(port))
+            debug.info(2, "Checking read delay values for port {0}".format(port))
             # Check sen timing, then bitlines, then general measurements.
             if not self.check_sen_measure(port):
                 return (False, {})
@@ -813,7 +828,7 @@ class delay(simulation):
 
             result[port].update(read_port_dict)
             
-            self.check_path_measures()
+            self.path_delays = self.check_path_measures()
 
         return (True, result)
 
@@ -821,7 +836,7 @@ class delay(simulation):
         """Checks that the sen occurred within a half-period"""
 
         sen_val = self.sen_meas.retrieve_measure(port=port)
-        debug.info(2, "s_en delay={}ns".format(sen_val))
+        debug.info(2, "s_en delay={0}ns".format(sen_val))
         if self.sen_meas.meta_add_delay:
             max_delay = self.period / 2
         else:
@@ -843,22 +858,22 @@ class delay(simulation):
             elif self.br_name == meas.targ_name_no_port:
                 br_vals[meas.meta_str] = val
 
-            debug.info(2, "{}={}".format(meas.name, val))
+            debug.info(2, "{0}={1}".format(meas.name, val))
 
         dout_success = True
         bl_success = False
         for meas in self.dout_volt_meas:
             val = meas.retrieve_measure(port=port)
-            debug.info(2, "{}={}".format(meas.name, val))
+            debug.info(2, "{0}={1}".format(meas.name, val))
             debug.check(type(val)==float, "Error retrieving numeric measurement: {0} {1}".format(meas.name, val))
 
             if meas.meta_str == sram_op.READ_ONE and val < self.vdd_voltage * 0.1:
                 dout_success = False
-                debug.info(1, "Debug measurement failed. Value {}V was read on read 1 cycle.".format(val))
+                debug.info(1, "Debug measurement failed. Value {0}V was read on read 1 cycle.".format(val))
                 bl_success = self.check_bitline_meas(bl_vals[sram_op.READ_ONE], br_vals[sram_op.READ_ONE])
             elif meas.meta_str == sram_op.READ_ZERO and val > self.vdd_voltage * 0.9:
                 dout_success = False
-                debug.info(1, "Debug measurement failed. Value {}V was read on read 0 cycle.".format(val))
+                debug.info(1, "Debug measurement failed. Value {0}V was read on read 0 cycle.".format(val))
                 bl_success = self.check_bitline_meas(br_vals[sram_op.READ_ONE], bl_vals[sram_op.READ_ONE])
 
             # If the bitlines have a correct value while the output does not then that is a
@@ -877,7 +892,7 @@ class delay(simulation):
         for polarity, meas_list in bit_measures.items():
             for meas in meas_list:
                 val = meas.retrieve_measure(port=port)
-                debug.info(2, "{}={}".format(meas.name, val))
+                debug.info(2, "{0}={1}".format(meas.name, val))
                 if type(val) != float:
                     continue
                 meas_cycle = meas.meta_str
@@ -896,8 +911,8 @@ class delay(simulation):
                     success = val < self.vdd_voltage / 2
                 if not success:
                     debug.info(1, ("Wrong value detected on probe bit during read/write cycle. "
-                                   "Check writes and control logic for bugs.\n measure={}, op={}, "
-                                   "bit_storage={}, V(bit)={}").format(meas.name, meas_cycle.name, polarity.name, val))
+                                   "Check writes and control logic for bugs.\n measure={0}, op={1}, "
+                                   "bit_storage={2}, V(bit)={3}").format(meas.name, meas_cycle.name, polarity.name, val))
 
         return success
 
@@ -912,7 +927,7 @@ class delay(simulation):
         min_dicharge = v_discharged_bl < self.vdd_voltage * 0.9
         min_diff = (v_charged_bl - v_discharged_bl) > self.vdd_voltage * 0.1
 
-        debug.info(1, "min_dicharge={}, min_diff={}".format(min_dicharge, min_diff))
+        debug.info(1, "min_dicharge={0}, min_diff={1}".format(min_dicharge, min_diff))
         return (min_dicharge and min_diff)
 
     def check_path_measures(self):
@@ -921,13 +936,13 @@ class delay(simulation):
         # Get and set measurement, no error checking done other than prints.
         debug.info(2, "Checking measures in Delay Path")
         value_dict = {}
-        for meas in self.sen_path_meas+self.bl_path_meas:
+        for meas in self.sen_path_meas + self.bl_path_meas:
             val = meas.retrieve_measure()
-            debug.info(2, '{}={}'.format(meas.name, val))
-            if type(val) != float or val > self.period/2:
-                debug.info(1,'Failed measurement:{}={}'.format(meas.name, val))
+            debug.info(2, '{0}={1}'.format(meas.name, val))
+            if type(val) != float or val > self.period / 2:
+                debug.info(1, 'Failed measurement:{}={}'.format(meas.name, val))
             value_dict[meas.name] = val
-        
+        #debug.info(0, "value_dict={}".format(value_dict))
         return value_dict
 
     def run_power_simulation(self):
@@ -1100,14 +1115,14 @@ class delay(simulation):
 
         # Set up to trim the netlist here if that is enabled
         if OPTS.trim_netlist:
-            self.trim_sp_file = "{}trimmed.sp".format(OPTS.openram_temp)
+            self.trim_sp_file = "{0}trimmed.sp".format(OPTS.openram_temp)
             self.sram.sp_write(self.trim_sp_file, lvs=False, trim=True)
         else:
             # The non-reduced netlist file when it is disabled
-            self.trim_sp_file = "{}sram.sp".format(OPTS.openram_temp)
+            self.trim_sp_file = "{0}sram.sp".format(OPTS.openram_temp)
 
         # The non-reduced netlist file for power simulation
-        self.sim_sp_file = "{}sram.sp".format(OPTS.openram_temp)
+        self.sim_sp_file = "{0}sram.sp".format(OPTS.openram_temp)
         # Make a copy in temp for debugging
         shutil.copy(self.sp_file, self.sim_sp_file)
 
@@ -1120,7 +1135,7 @@ class delay(simulation):
         self.create_measurement_names()
         self.create_measurement_objects()
 
-    def analyze(self, probe_address, probe_data, slews, loads):
+    def analyze(self, probe_address, probe_data, load_slews):
         """
         Main function to characterize an SRAM for a table. Computes both delay and power characterization.
         """
@@ -1128,7 +1143,11 @@ class delay(simulation):
         # Dict to hold all characterization values
         char_sram_data = {}
         self.analysis_init(probe_address, probe_data)
-
+        loads = []
+        slews = []
+        for load,slew in load_slews:
+            loads.append(load)
+            slews.append(slew)
         self.load=max(loads)
         self.slew=max(slews)
 
@@ -1148,11 +1167,19 @@ class delay(simulation):
         leakage_offset = full_array_leakage - trim_array_leakage
         # 4) At the minimum period, measure the delay, slew and power for all slew/load pairs.
         self.period = min_period
-        char_port_data = self.simulate_loads_and_slews(slews, loads, leakage_offset)
-
+        char_port_data = self.simulate_loads_and_slews(load_slews, leakage_offset)
+        if OPTS.use_specified_load_slew != None and len(load_slews) > 1:
+            debug.warning("Path delay lists not correctly generated for characterizations of more than 1 load,slew")
+        # Get and save the path delays
+        bl_names, bl_delays, sen_names, sen_delays = self.get_delay_lists(self.path_delays)
+        # Removed from characterization output temporarily
+        #char_sram_data["bl_path_measures"] = bl_delays
+        #char_sram_data["sen_path_measures"] = sen_delays
+        #char_sram_data["bl_path_names"] = bl_names
+        #char_sram_data["sen_path_names"] = sen_names
         # FIXME: low-to-high delays are altered to be independent of the period. This makes the lib results less accurate.
         self.alter_lh_char_data(char_port_data)
-
+           
         return (char_sram_data, char_port_data)
 
     def alter_lh_char_data(self, char_port_data):
@@ -1163,30 +1190,47 @@ class delay(simulation):
             char_port_data[port]['delay_lh'] = char_port_data[port]['delay_hl']
             char_port_data[port]['slew_lh'] = char_port_data[port]['slew_hl']
 
-    def simulate_loads_and_slews(self, slews, loads, leakage_offset):
+    def simulate_loads_and_slews(self, load_slews, leakage_offset):
         """Simulate all specified output loads and input slews pairs of all ports"""
 
         measure_data = self.get_empty_measure_data_dict()
+        path_dict = {}
         # Set the target simulation ports to all available ports. This make sims slower but failed sims exit anyways.
         self.targ_read_ports = self.read_ports
         self.targ_write_ports = self.write_ports
-        for slew in slews:
-            for load in loads:
-                self.set_load_slew(load, slew)
-                # Find the delay, dynamic power, and leakage power of the trimmed array.
-                (success, delay_results) = self.run_delay_simulation()
-                debug.check(success, "Couldn't run a simulation. slew={0} load={1}\n".format(self.slew, self.load))
-                debug.info(1, "Simulation Passed: Port {0} slew={1} load={2}".format("All", self.slew, self.load))
-                # The results has a dict for every port but dicts can be empty (e.g. ports were not targeted).
-                for port in self.all_ports:
-                    for mname, value in delay_results[port].items():
-                        if "power" in mname:
-                            # Subtract partial array leakage and add full array leakage for the power measures
-                            measure_data[port][mname].append(value + leakage_offset)
-                        else:
-                            measure_data[port][mname].append(value)
+        for load, slew in load_slews:
+            self.set_load_slew(load, slew)
+            # Find the delay, dynamic power, and leakage power of the trimmed array.
+            (success, delay_results) = self.run_delay_simulation()
+            debug.check(success, "Couldn't run a simulation. slew={0} load={1}\n".format(self.slew, self.load))
+            debug.info(1, "Simulation Passed: Port {0} slew={1} load={2}".format("All", self.slew, self.load))
+            # The results has a dict for every port but dicts can be empty (e.g. ports were not targeted).
+            for port in self.all_ports:
+                for mname, value in delay_results[port].items():
+                    if "power" in mname:
+                        # Subtract partial array leakage and add full array leakage for the power measures
+                        debug.info(1, "Adding leakage offset to {0} {1} + {2} = {3}".format(mname, value, leakage_offset, value + leakage_offset))
+                        measure_data[port][mname].append(value + leakage_offset)
+                    else:
+                        measure_data[port][mname].append(value)
         return measure_data
 
+    def get_delay_lists(self, value_dict):
+        """Returns dicts for path measures of bitline and sen paths"""
+        sen_name_list = []
+        sen_delay_list = []
+        for meas in self.sen_path_meas:
+            sen_name_list.append(meas.name)
+            sen_delay_list.append(value_dict[meas.name])
+        
+        bl_name_list = []
+        bl_delay_list = []
+        for meas in self.bl_path_meas:
+            bl_name_list.append(meas.name)
+            bl_delay_list.append(value_dict[meas.name])
+
+        return sen_name_list, sen_delay_list, bl_name_list, bl_delay_list 
+
     def calculate_inverse_address(self):
         """Determine dummy test address based on probe address and column mux size."""
 
@@ -1218,13 +1262,13 @@ class delay(simulation):
         if self.t_current == 0:
             self.add_noop_all_ports("Idle cycle (no positive clock edge)")
 
-        self.add_write("W data 1 address {}".format(inverse_address),
+        self.add_write("W data 1 address {0}".format(inverse_address),
                        inverse_address,
                        data_ones,
                        wmask_ones,
                        write_port)
 
-        self.add_write("W data 0 address {} to write value".format(self.probe_address),
+        self.add_write("W data 0 address {0} to write value".format(self.probe_address),
                        self.probe_address,
                        data_zeros,
                        wmask_ones,
@@ -1235,11 +1279,11 @@ class delay(simulation):
         self.measure_cycles[write_port]["disabled_write0"] = len(self.cycle_times) - 1
 
         # This also ensures we will have a H->L transition on the next read
-        self.add_read("R data 1 address {} to set dout caps".format(inverse_address),
+        self.add_read("R data 1 address {0} to set dout caps".format(inverse_address),
                       inverse_address,
                       read_port)
 
-        self.add_read("R data 0 address {} to check W0 worked".format(self.probe_address),
+        self.add_read("R data 0 address {0} to check W0 worked".format(self.probe_address),
                       self.probe_address,
                       read_port)
         self.measure_cycles[read_port][sram_op.READ_ZERO] = len(self.cycle_times) - 1
@@ -1249,7 +1293,7 @@ class delay(simulation):
 
         self.add_noop_all_ports("Idle cycle (if read takes >1 cycle)")
 
-        self.add_write("W data 1 address {} to write value".format(self.probe_address),
+        self.add_write("W data 1 address {0} to write value".format(self.probe_address),
                        self.probe_address,
                        data_ones,
                        wmask_ones,
@@ -1259,7 +1303,7 @@ class delay(simulation):
         self.add_noop_clock_one_port(write_port)
         self.measure_cycles[write_port]["disabled_write1"] = len(self.cycle_times) - 1
 
-        self.add_write("W data 0 address {} to clear din caps".format(inverse_address),
+        self.add_write("W data 0 address {0} to clear din caps".format(inverse_address),
                        inverse_address,
                        data_zeros,
                        wmask_ones,
@@ -1269,11 +1313,11 @@ class delay(simulation):
         self.measure_cycles[read_port]["disabled_read1"] = len(self.cycle_times) - 1
 
         # This also ensures we will have a L->H transition on the next read
-        self.add_read("R data 0 address {} to clear dout caps".format(inverse_address),
+        self.add_read("R data 0 address {0} to clear dout caps".format(inverse_address),
                       inverse_address,
                       read_port)
 
-        self.add_read("R data 1 address {} to check W1 worked".format(self.probe_address),
+        self.add_read("R data 1 address {0} to check W1 worked".format(self.probe_address),
                       self.probe_address,
                       read_port)
         self.measure_cycles[read_port][sram_op.READ_ONE] = len(self.cycle_times) - 1

compiler/characterizer/elmore.py

@@ -30,7 +30,7 @@ class elmore(simulation):
         self.create_signal_names()
         self.add_graph_exclusions()
     
-    def get_lib_values(self, slews, loads):
+    def get_lib_values(self, load_slews):
         """
         Return the analytical model results for the SRAM.
         """
@@ -53,31 +53,29 @@ class elmore(simulation):
 
         # Set delay/power for slews and loads
         port_data = self.get_empty_measure_data_dict()
-        power = self.analytical_power(slews, loads)
+        power = self.analytical_power(load_slews)
         debug.info(1, 'Slew, Load, Delay(ns), Slew(ns)')
         max_delay = 0.0
-        for slew in slews:
-            for load in loads:
-                # Calculate delay based on slew and load
-                path_delays = self.graph.get_timing(bl_path, self.corner, slew, load)
+        for load,slew in load_slews:
+            # Calculate delay based on slew and load
+            path_delays = self.graph.get_timing(bl_path, self.corner, slew, load)
 
-                total_delay = self.sum_delays(path_delays)
-                max_delay = max(max_delay, total_delay.delay)
-                debug.info(1,
-                           '{}, {}, {}, {}'.format(slew,
-                                                   load,
-                                                   total_delay.delay / 1e3,
-                                                   total_delay.slew / 1e3))
-
-                # Delay is only calculated on a single port and replicated for now.
-                for port in self.all_ports:
-                    for mname in self.delay_meas_names + self.power_meas_names:
-                        if "power" in mname:
-                            port_data[port][mname].append(power.dynamic)
-                        elif "delay" in mname and port in self.read_ports:
-                            port_data[port][mname].append(total_delay.delay / 1e3)
-                        elif "slew" in mname and port in self.read_ports:
-                            port_data[port][mname].append(total_delay.slew / 1e3)
+            total_delay = self.sum_delays(path_delays)
+            max_delay = max(max_delay, total_delay.delay)
+            debug.info(1,
+                       '{}, {}, {}, {}'.format(slew,
+                                               load,
+                                               total_delay.delay / 1e3,
+                                               total_delay.slew / 1e3))
+            # Delay is only calculated on a single port and replicated for now.
+            for port in self.all_ports:
+                for mname in self.delay_meas_names + self.power_meas_names:
+                    if "power" in mname:
+                        port_data[port][mname].append(power.dynamic)
+                    elif "delay" in mname and port in self.read_ports:
+                        port_data[port][mname].append(total_delay.delay / 1e3)
+                    elif "slew" in mname and port in self.read_ports:
+                        port_data[port][mname].append(total_delay.slew / 1e3)
 
         # Margin for error in period. Calculated by averaging required margin for a small and large 
         # memory. FIXME: margin is quite large, should be looked into.
@@ -90,11 +88,11 @@ class elmore(simulation):
 
         return (sram_data, port_data)
 
-    def analytical_power(self, slews, loads):
+    def analytical_power(self, load_slews):
         """Get the dynamic and leakage power from the SRAM"""
 
         # slews unused, only last load is used
-        load = loads[-1]
+        load = load_slews[-1][0]
         power = self.sram.analytical_power(self.corner, load)
         # convert from nW to mW
         power.dynamic /= 1e6

compiler/characterizer/functional.py

@@ -81,7 +81,7 @@ class functional(simulation):
         self.create_graph()
         self.set_internal_spice_names()
         self.q_name, self.qbar_name = self.get_bit_name()
-        debug.info(2, "q name={}\nqbar name={}".format(self.q_name, self.qbar_name))
+        debug.info(2, "q name={0}\nqbar name={1}".format(self.q_name, self.qbar_name))
 
         # Number of checks can be changed
         self.num_cycles = cycles
@@ -144,7 +144,7 @@ class functional(simulation):
         for port in self.write_ports:
             addr = self.gen_addr()
             (word, spare) = self.gen_data()
-            combined_word = "{}+{}".format(word, spare)            
+            combined_word = "{0}+{1}".format(word, spare)
             comment = self.gen_cycle_comment("write", combined_word, addr, "1" * self.num_wmasks, port, self.t_current)
             self.add_write_one_port(comment, addr, word + spare, "1" * self.num_wmasks, port)
             self.stored_words[addr] = word
@@ -167,7 +167,7 @@ class functional(simulation):
                 self.add_noop_one_port(port)
             else:
                 (addr, word, spare) = self.get_data()
-                combined_word = "{}+{}".format(word, spare)
+                combined_word = "{0}+{1}".format(word, spare)
                 comment = self.gen_cycle_comment("read", combined_word, addr, "0" * self.num_wmasks, port, self.t_current)
                 self.add_read_one_port(comment, addr, port)
                 self.add_read_check(word, port)
@@ -197,7 +197,7 @@ class functional(simulation):
                         self.add_noop_one_port(port)
                     else:
                         (word, spare) = self.gen_data()
-                        combined_word = "{}+{}".format(word, spare)
+                        combined_word = "{0}+{1}".format(word, spare)
                         comment = self.gen_cycle_comment("write", combined_word, addr, "1" * self.num_wmasks, port, self.t_current)
                         self.add_write_one_port(comment, addr, word + spare, "1" * self.num_wmasks, port)
                         self.stored_words[addr] = word
@@ -213,7 +213,7 @@ class functional(simulation):
                         (word, spare) = self.gen_data()
                         wmask  = self.gen_wmask()
                         new_word = self.gen_masked_data(old_word, word, wmask)
-                        combined_word = "{}+{}".format(word, spare)
+                        combined_word = "{0}+{1}".format(word, spare)
                         comment = self.gen_cycle_comment("partial_write", combined_word, addr, wmask, port, self.t_current)
                         self.add_write_one_port(comment, addr, word + spare, wmask, port)
                         self.stored_words[addr] = new_word
@@ -222,7 +222,7 @@ class functional(simulation):
                 else:
                     (addr, word) = random.choice(list(self.stored_words.items()))
                     spare = self.stored_spares[addr[:self.addr_spare_index]]
-                    combined_word = "{}+{}".format(word, spare)
+                    combined_word = "{0}+{1}".format(word, spare)
                     # The write driver is not sized sufficiently to drive through the two
                     # bitcell access transistors to the read port. So, for now, we do not allow
                     # a simultaneous write and read to the same address on different ports. This
@@ -363,7 +363,7 @@ class functional(simulation):
         self.stim_sp = "functional_stim.sp"
         temp_stim = "{0}/{1}".format(self.output_path, self.stim_sp)
         self.sf = open(temp_stim, "w")
-        self.sf.write("* Functional test stimulus file for {}ns period\n\n".format(self.period))
+        self.sf.write("* Functional test stimulus file for {0}ns period\n\n".format(self.period))
         self.stim = stimuli(self.sf, self.corner)
 
         # Write include statements
@@ -387,16 +387,16 @@ class functional(simulation):
 
         # Write important signals to stim file
         self.sf.write("\n\n* Important signals for debug\n")
-        self.sf.write("* bl: {}\n".format(self.bl_name.format(port)))
-        self.sf.write("* br: {}\n".format(self.br_name.format(port)))
-        self.sf.write("* s_en: {}\n".format(self.sen_name))
-        self.sf.write("* q: {}\n".format(self.q_name))
-        self.sf.write("* qbar: {}\n".format(self.qbar_name))
+        self.sf.write("* bl: {0}\n".format(self.bl_name.format(port)))
+        self.sf.write("* br: {0}\n".format(self.br_name.format(port)))
+        self.sf.write("* s_en: {0}\n".format(self.sen_name))
+        self.sf.write("* q: {0}\n".format(self.q_name))
+        self.sf.write("* qbar: {0}\n".format(self.qbar_name))
 
         # Write debug comments to stim file
         self.sf.write("\n\n* Sequence of operations\n")
         for comment in self.fn_cycle_comments:
-            self.sf.write("*{}\n".format(comment))
+            self.sf.write("*{0}\n".format(comment))
 
         # Generate data input bits
         self.sf.write("\n* Generation of data and address signals\n")
@@ -414,10 +414,10 @@ class functional(simulation):
         # Generate control signals
         self.sf.write("\n * Generation of control signals\n")
         for port in self.all_ports:
-            self.stim.gen_pwl("CSB{}".format(port), self.cycle_times, self.csb_values[port], self.period, self.slew, 0.05)
+            self.stim.gen_pwl("CSB{0}".format(port), self.cycle_times, self.csb_values[port], self.period, self.slew, 0.05)
 
         for port in self.readwrite_ports:
-            self.stim.gen_pwl("WEB{}".format(port), self.cycle_times, self.web_values[port], self.period, self.slew, 0.05)
+            self.stim.gen_pwl("WEB{0}".format(port), self.cycle_times, self.web_values[port], self.period, self.slew, 0.05)
 
         # Generate wmask bits
         for port in self.write_ports:
@@ -472,15 +472,15 @@ class functional(simulation):
         self.stim.write_control(self.cycle_times[-1] + self.period)
         self.sf.close()
 
-    #FIXME: Similar function to delay.py, refactor this
+    # FIXME: Similar function to delay.py, refactor this
     def get_bit_name(self):
         """ Get a bit cell name """
         (cell_name, cell_inst) = self.sram.get_cell_name(self.sram.name, 0, 0)
         storage_names = cell_inst.mod.get_storage_net_names()
         debug.check(len(storage_names) == 2, ("Only inverting/non-inverting storage nodes"
-                                              "supported for characterization. Storage nets={}").format(storage_names))
-        q_name = cell_name + '.' + str(storage_names[0])
-        qbar_name = cell_name + '.' + str(storage_names[1])
+                                              "supported for characterization. Storage nets={0}").format(storage_names))
+        q_name = cell_name + OPTS.hier_seperator + str(storage_names[0])
+        qbar_name = cell_name + OPTS.hier_seperator + str(storage_names[1])
 
         return (q_name, qbar_name)
 

compiler/characterizer/lib.py

@@ -5,7 +5,8 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import os
+import os,sys,re
+import time
 import debug
 import datetime
 from .setup_hold import *
@@ -14,6 +15,7 @@ from .charutils import *
 import tech
 import numpy as np
 from globals import OPTS
+from tech import spice
 
 
 class lib:
@@ -21,10 +23,20 @@ class lib:
 
     def __init__(self, out_dir, sram, sp_file, use_model=OPTS.analytical_delay):
 
+        try:
+            self.vdd_name = spice["power"]
+        except KeyError:
+            self.vdd_name = "vdd"
+        try:
+            self.gnd_name = spice["ground"]
+        except KeyError:
+            self.gnd_name = "gnd"
+            
         self.out_dir = out_dir
         self.sram = sram
         self.sp_file = sp_file
         self.use_model = use_model
+        self.pred_time = None
         self.set_port_indices()
 
         self.prepare_tables()
@@ -44,16 +56,32 @@ class lib:
     def prepare_tables(self):
         """ Determine the load/slews if they aren't specified in the config file. """
         # These are the parameters to determine the table sizes
-        self.load_scales = np.array(OPTS.load_scales)
-        self.load = tech.spice["dff_in_cap"]
-        self.loads = self.load_scales * self.load
+        if OPTS.use_specified_load_slew == None:
+            self.load_scales = np.array(OPTS.load_scales)
+            self.load = tech.spice["dff_in_cap"]
+            self.loads = self.load_scales * self.load
+            
+
+            self.slew_scales = np.array(OPTS.slew_scales)
+            self.slew = tech.spice["rise_time"]
+            self.slews = self.slew_scales * self.slew
+            self.load_slews = []
+            for slew in self.slews:
+                for load in self.loads:
+                    self.load_slews.append((load, slew))
+        else:
+            debug.warning("Using the option \"use_specified_load_slew\" will make load slew,data in lib file inaccurate.")
+            self.load_slews = OPTS.use_specified_load_slew
+            self.loads = []
+            self.slews = []
+            for load,slew in self.load_slews:
+                self.loads.append(load)
+                self.slews.append(slew)
+        self.loads = np.array(self.loads)
+        self.slews = np.array(self.slews)
+        debug.info(1, "Slews: {0}".format(self.slews))    
         debug.info(1, "Loads: {0}".format(self.loads))
-
-        self.slew_scales = np.array(OPTS.slew_scales)
-        self.slew = tech.spice["rise_time"]
-        self.slews = self.slew_scales * self.slew
-        debug.info(1, "Slews: {0}".format(self.slews))
-
+        debug.info(1, "self.load_slews : {0}".format(self.load_slews))
     def create_corners(self):
         """ Create corners for characterization. """
         # Get the corners from the options file
@@ -124,7 +152,9 @@ class lib:
     def characterize_corners(self):
         """ Characterize the list of corners. """
         debug.info(1,"Characterizing corners: " + str(self.corners))
+        is_first_corner = True
         for (self.corner,lib_name) in zip(self.corners,self.lib_files):
+            run_start = time.time()
             debug.info(1,"Corner: " + str(self.corner))
             (self.process, self.voltage, self.temperature) = self.corner
             self.lib = open(lib_name, "w")
@@ -132,7 +162,12 @@ class lib:
             self.corner_name = lib_name.replace(self.out_dir,"").replace(".lib","")
             self.characterize()
             self.lib.close()
-            self.parse_info(self.corner,lib_name)
+            if self.pred_time == None:
+                total_time = time.time()-run_start
+            else:
+                total_time = self.pred_time
+            self.parse_info(self.corner,lib_name, is_first_corner, total_time)
+            is_first_corner = False
 
     def characterize(self):
         """ Characterize the current corner. """
@@ -249,8 +284,8 @@ class lib:
         self.lib.write("    default_max_fanout   : 4.0 ;\n")
         self.lib.write("    default_connection_class : universal ;\n\n")
 
-        self.lib.write("    voltage_map ( VDD, {} );\n".format(self.voltage))
-        self.lib.write("    voltage_map ( GND, 0 );\n\n")
+        self.lib.write("    voltage_map ( {0}, {1} );\n".format(self.vdd_name.upper(), self.voltage))
+        self.lib.write("    voltage_map ( {0}, 0 );\n\n".format(self.gnd_name.upper()))
 
     def create_list(self,values):
         """ Helper function to create quoted, line wrapped list """
@@ -582,12 +617,12 @@ class lib:
             self.lib.write("        }\n")
 
     def write_pg_pin(self):
-        self.lib.write("    pg_pin(vdd) {\n")
-        self.lib.write("         voltage_name : VDD;\n")
+        self.lib.write("    pg_pin({0}) ".format(self.vdd_name) + "{\n")
+        self.lib.write("         voltage_name : {};\n".format(self.vdd_name.upper()))
         self.lib.write("         pg_type : primary_power;\n")
         self.lib.write("    }\n\n")
-        self.lib.write("    pg_pin(gnd) {\n")
-        self.lib.write("         voltage_name : GND;\n")
+        self.lib.write("    pg_pin({0}) ".format(self.gnd_name) + "{\n")
+        self.lib.write("         voltage_name : {};\n".format(self.gnd_name.upper()))
         self.lib.write("         pg_type : primary_ground;\n")
         self.lib.write("    }\n\n")
 
@@ -603,7 +638,7 @@ class lib:
                 debug.error("{} model not recognized. See options.py for available models.".format(OPTS.model_name))
 
             m = model(self.sram, self.sp_file, self.corner)
-            char_results = m.get_lib_values(self.slews,self.loads)
+            char_results = m.get_lib_values(self.load_slews)
 
         else:
             self.d = delay(self.sram, self.sp_file, self.corner)
@@ -612,27 +647,44 @@ class lib:
             else:
                 probe_address = "0" + "1" * (self.sram.addr_size - 1)
             probe_data = self.sram.word_size - 1
-            char_results = self.d.analyze(probe_address, probe_data, self.slews, self.loads)
+            char_results = self.d.analyze(probe_address, probe_data, self.load_slews)
+            
+            
+            
         self.char_sram_results, self.char_port_results = char_results
-
+        if 'sim_time' in self.char_sram_results:
+            self.pred_time = self.char_sram_results['sim_time']
+        # Add to the OPTS to be written out as part of the extended OPTS file
+        # FIXME: Temporarily removed from characterization output  
+        # if not self.use_model:
+            # OPTS.sen_path_delays = self.char_sram_results["sen_path_measures"]
+            # OPTS.sen_path_names = self.char_sram_results["sen_path_names"]
+            # OPTS.bl_path_delays = self.char_sram_results["bl_path_measures"]
+            # OPTS.bl_path_names = self.char_sram_results["bl_path_names"]
+  
+            
     def compute_setup_hold(self):
         """ Do the analysis if we haven't characterized a FF yet """
         # Do the analysis if we haven't characterized a FF yet
         if not hasattr(self,"sh"):
             self.sh = setup_hold(self.corner)
             if self.use_model:
-                self.times = self.sh.analytical_setuphold(self.slews,self.loads)
+                self.times = self.sh.analytical_setuphold(self.slews,self.slews)
             else:
                 self.times = self.sh.analyze(self.slews,self.slews)
 
 
-    def parse_info(self,corner,lib_name):
+    def parse_info(self,corner,lib_name, is_first_corner, time):
         """ Copies important characterization data to datasheet.info to be added to datasheet """
         if OPTS.output_datasheet_info:
             datasheet_path = OPTS.output_path
         else:
             datasheet_path = OPTS.openram_temp
-        datasheet = open(datasheet_path +'/datasheet.info', 'a+')
+        # Open for write and truncate to not conflict with a previous run using the same name
+        if is_first_corner:
+            datasheet = open(datasheet_path +'/datasheet.info', 'w')
+        else:
+            datasheet = open(datasheet_path +'/datasheet.info', 'a+')
         
         self.write_inp_params_datasheet(datasheet, corner, lib_name)
         self.write_signal_from_ports(datasheet,
@@ -694,7 +746,7 @@ class lib:
 
         self.write_power_datasheet(datasheet)
 
-        self.write_model_params(datasheet)
+        self.write_model_params(datasheet, time)
         
         datasheet.write("END\n")
         datasheet.close()
@@ -807,8 +859,9 @@ class lib:
 
         datasheet.write("{0},{1},{2},".format('leak', control_str, self.char_sram_results["leakage_power"]))
         
-    def write_model_params(self, datasheet):
+    def write_model_params(self, datasheet, time):
         """Write values which will be used in the analytical model as inputs"""
+        datasheet.write("{0},{1},".format('sim_time', time))
         datasheet.write("{0},{1},".format('words_per_row', OPTS.words_per_row))
         datasheet.write("{0},{1},".format('slews', list(self.slews)))
         datasheet.write("{0},{1},".format('loads', list(self.loads)))
@@ -824,13 +877,15 @@ class lib:
             write0_power = np.mean(self.char_port_results[port]["write0_power"])
             datasheet.write("{0},{1},".format('write_rise_power_{}'.format(port), write1_power))
             #FIXME: should be write_fall_power
-            datasheet.write("{0},{1},".format('read_fall_power_{}'.format(port), write0_power))
+            datasheet.write("{0},{1},".format('write_fall_power_{}'.format(port), write0_power))
         
         for port in self.read_ports:
             read1_power = np.mean(self.char_port_results[port]["read1_power"])
             read0_power = np.mean(self.char_port_results[port]["read0_power"])
             datasheet.write("{0},{1},".format('read_rise_power_{}'.format(port), read1_power))
             #FIXME: should be read_fall_power
-            datasheet.write("{0},{1},".format('write_fall_power_{}'.format(port), read0_power))
+            datasheet.write("{0},{1},".format('read_fall_power_{}'.format(port), read0_power))
         
         
+ 
+        

compiler/characterizer/linear_regression.py

@@ -7,6 +7,7 @@
 #
 
 from .regression_model import regression_model
+from sklearn.linear_model import Ridge
 from globals import OPTS
 import debug
 
@@ -23,7 +24,8 @@ class linear_regression(regression_model):
         Supervised training of model.
         """
         
-        model = LinearRegression()
+        #model = LinearRegression()
+        model = Ridge()
         model.fit(features, labels)
         return model
         

compiler/characterizer/measurements.py

@@ -53,11 +53,20 @@ class spice_measurement(ABC):
         elif not self.has_port and port != None:
             debug.error("Unexpected port input received during measure retrieval.",1)
 
+
 class delay_measure(spice_measurement):
     """Generates a spice measurement for the delay of 50%-to-50% points of two signals."""
 
-    def __init__(self, measure_name, trig_name, targ_name,  trig_dir_str, targ_dir_str,\
-                 trig_vdd=0.5, targ_vdd=0.5, measure_scale=None, has_port=True):
+    def __init__(self,
+                 measure_name,
+                 trig_name,
+                 targ_name,
+                 trig_dir_str,
+                 targ_dir_str,
+                 trig_vdd=0.5,
+                 targ_vdd=0.5,
+                 measure_scale=None,
+                 has_port=True):
         spice_measurement.__init__(self, measure_name, measure_scale, has_port)
         self.set_meas_constants(trig_name, targ_name, trig_dir_str, targ_dir_str, trig_vdd, targ_vdd)
 
@@ -73,7 +82,7 @@ class delay_measure(spice_measurement):
         self.trig_name_no_port = trig_name
         self.targ_name_no_port = targ_name
 
-        #Time delays and ports are variant and needed as inputs when writing the measurement
+        # Time delays and ports are variant and needed as inputs when writing the measurement
 
     def get_measure_values(self, trig_td, targ_td, vdd_voltage, port=None):
         """Constructs inputs to stimulus measurement function. Variant values are inputs here."""
@@ -82,7 +91,7 @@ class delay_measure(spice_measurement):
         targ_val = self.targ_val_of_vdd * vdd_voltage
 
         if port != None:
-            #For dictionary indexing reasons, the name is formatted differently than the signals
+            # For dictionary indexing reasons, the name is formatted differently than the signals
             meas_name = "{}{}".format(self.name, port)
             trig_name = self.trig_name_no_port.format(port)
             targ_name = self.targ_name_no_port.format(port)
@@ -90,7 +99,8 @@ class delay_measure(spice_measurement):
             meas_name = self.name
             trig_name = self.trig_name_no_port
             targ_name = self.targ_name_no_port
-        return (meas_name,trig_name,targ_name,trig_val,targ_val,self.trig_dir_str,self.targ_dir_str,trig_td,targ_td)
+        return (meas_name, trig_name, targ_name, trig_val, targ_val, self.trig_dir_str, self.targ_dir_str, trig_td, targ_td)
+
 
 class slew_measure(delay_measure):
 
@@ -114,7 +124,8 @@ class slew_measure(delay_measure):
         self.trig_name_no_port = signal_name
         self.targ_name_no_port = signal_name
 
-        #Time delays and ports are variant and needed as inputs when writing the measurement
+        # Time delays and ports are variant and needed as inputs when writing the measurement
+
 
 class power_measure(spice_measurement):
     """Generates a spice measurement for the average power between two time points."""
@@ -128,8 +139,8 @@ class power_measure(spice_measurement):
 
     def set_meas_constants(self, power_type):
         """Sets values useful for power simulations. This value is only meta related to the lib file (rise/fall)"""
-        #Not needed for power simulation
-        self.power_type = power_type #Expected to be  "RISE"/"FALL"
+        # Not needed for power simulation
+        self.power_type = power_type # Expected to be  "RISE"/"FALL"
 
     def get_measure_values(self, t_initial, t_final, port=None):
         """Constructs inputs to stimulus measurement function. Variant values are inputs here."""
@@ -138,7 +149,8 @@ class power_measure(spice_measurement):
             meas_name = "{}{}".format(self.name, port)
         else:
             meas_name = self.name
-        return (meas_name,t_initial,t_final)
+        return (meas_name, t_initial, t_final)
+
 
 class voltage_when_measure(spice_measurement):
     """Generates a spice measurement to measure the voltage of a signal based on the voltage of another."""
@@ -161,7 +173,7 @@ class voltage_when_measure(spice_measurement):
         """Constructs inputs to stimulus measurement function. Variant values are inputs here."""
         self.port_error_check(port)
         if port != None:
-            #For dictionary indexing reasons, the name is formatted differently than the signals
+            # For dictionary indexing reasons, the name is formatted differently than the signals
             meas_name = "{}{}".format(self.name, port)
             trig_name = self.trig_name_no_port.format(port)
             targ_name = self.targ_name_no_port.format(port)
@@ -169,9 +181,10 @@ class voltage_when_measure(spice_measurement):
             meas_name = self.name
             trig_name = self.trig_name_no_port
             targ_name = self.targ_name_no_port
-        trig_voltage = self.trig_val_of_vdd*vdd_voltage
-        return (meas_name,trig_name,targ_name,trig_voltage,self.trig_dir_str,trig_td)
+        trig_voltage = self.trig_val_of_vdd * vdd_voltage
+        return (meas_name, trig_name, targ_name, trig_voltage, self.trig_dir_str, trig_td)
 
+    
 class voltage_at_measure(spice_measurement):
     """Generates a spice measurement to measure the voltage at a specific time.
        The time is considered variant with different periods."""
@@ -191,11 +204,11 @@ class voltage_at_measure(spice_measurement):
         """Constructs inputs to stimulus measurement function. Variant values are inputs here."""
         self.port_error_check(port)
         if port != None:
-            #For dictionary indexing reasons, the name is formatted differently than the signals
+            # For dictionary indexing reasons, the name is formatted differently than the signals
             meas_name = "{}{}".format(self.name, port)
             targ_name = self.targ_name_no_port.format(port)
         else:
             meas_name = self.name
             targ_name = self.targ_name_no_port
-        return (meas_name,targ_name,time_at)
+        return (meas_name, targ_name, time_at)
 

compiler/characterizer/model_check.py

@@ -5,18 +5,16 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import sys,re,shutil
 import debug
 import tech
-import math
 from .stimuli import *
 from .trim_spice import *
 from .charutils import *
-import utils
 from globals import OPTS
 from .delay import delay
 from .measurements import *
 
+
 class model_check(delay):
     """Functions to test for the worst case delay in a target SRAM
 
@@ -39,43 +37,44 @@ class model_check(delay):
         self.power_name = "total_power"
 
     def create_measurement_names(self, port):
-        """Create measurement names. The names themselves currently define the type of measurement"""
-        #Create delay measurement names
-        wl_en_driver_delay_names = ["delay_wl_en_dvr_{}".format(stage) for stage in range(1,self.get_num_wl_en_driver_stages())]
-        wl_driver_delay_names = ["delay_wl_dvr_{}".format(stage) for stage in range(1,self.get_num_wl_driver_stages())]
-        sen_driver_delay_names = ["delay_sen_dvr_{}".format(stage) for stage in range(1,self.get_num_sen_driver_stages())]
+        """
+        Create measurement names. The names themselves currently define the type of measurement
+        """
+        wl_en_driver_delay_names = ["delay_wl_en_dvr_{0}".format(stage) for stage in range(1, self.get_num_wl_en_driver_stages())]
+        wl_driver_delay_names = ["delay_wl_dvr_{0}".format(stage) for stage in range(1, self.get_num_wl_driver_stages())]
+        sen_driver_delay_names = ["delay_sen_dvr_{0}".format(stage) for stage in range(1, self.get_num_sen_driver_stages())]
         if self.custom_delaychain:
-            dc_delay_names = ['delay_dc_out_final']
+            dc_delay_names = ["delay_dc_out_final"]
         else:
-            dc_delay_names = ["delay_delay_chain_stage_{}".format(stage) for stage in range(1,self.get_num_delay_stages()+1)]
-        self.wl_delay_meas_names = wl_en_driver_delay_names+["delay_wl_en", "delay_wl_bar"]+wl_driver_delay_names+["delay_wl"]
+            dc_delay_names = ["delay_delay_chain_stage_{0}".format(stage) for stage in range(1, self.get_num_delay_stages() + 1)]
+        self.wl_delay_meas_names = wl_en_driver_delay_names + ["delay_wl_en", "delay_wl_bar"] + wl_driver_delay_names + ["delay_wl"]
         if port not in self.sram.readonly_ports:
-            self.rbl_delay_meas_names = ["delay_gated_clk_nand", "delay_delay_chain_in"]+dc_delay_names
+            self.rbl_delay_meas_names = ["delay_gated_clk_nand", "delay_delay_chain_in"] + dc_delay_names
         else:
-            self.rbl_delay_meas_names = ["delay_gated_clk_nand"]+dc_delay_names
-        self.sae_delay_meas_names = ["delay_pre_sen"]+sen_driver_delay_names+["delay_sen"]
+            self.rbl_delay_meas_names = ["delay_gated_clk_nand"] + dc_delay_names
+        self.sae_delay_meas_names = ["delay_pre_sen"] + sen_driver_delay_names + ["delay_sen"]
 
         # if self.custom_delaychain:
-            # self.delay_chain_indices = (len(self.rbl_delay_meas_names), len(self.rbl_delay_meas_names)+1)
+        # self.delay_chain_indices = (len(self.rbl_delay_meas_names), len(self.rbl_delay_meas_names)+1)
         # else:
-        self.delay_chain_indices = (len(self.rbl_delay_meas_names)-len(dc_delay_names), len(self.rbl_delay_meas_names))
-        #Create slew measurement names
-        wl_en_driver_slew_names = ["slew_wl_en_dvr_{}".format(stage) for stage in range(1,self.get_num_wl_en_driver_stages())]
-        wl_driver_slew_names = ["slew_wl_dvr_{}".format(stage) for stage in range(1,self.get_num_wl_driver_stages())]
-        sen_driver_slew_names = ["slew_sen_dvr_{}".format(stage) for stage in range(1,self.get_num_sen_driver_stages())]
+        self.delay_chain_indices = (len(self.rbl_delay_meas_names) - len(dc_delay_names), len(self.rbl_delay_meas_names))
+        # Create slew measurement names
+        wl_en_driver_slew_names = ["slew_wl_en_dvr_{0}".format(stage) for stage in range(1, self.get_num_wl_en_driver_stages())]
+        wl_driver_slew_names = ["slew_wl_dvr_{0}".format(stage) for stage in range(1, self.get_num_wl_driver_stages())]
+        sen_driver_slew_names = ["slew_sen_dvr_{0}".format(stage) for stage in range(1, self.get_num_sen_driver_stages())]
         if self.custom_delaychain:
-            dc_slew_names = ['slew_dc_out_final']
+            dc_slew_names = ["slew_dc_out_final"]
         else:
-            dc_slew_names = ["slew_delay_chain_stage_{}".format(stage) for stage in range(1,self.get_num_delay_stages()+1)]
-        self.wl_slew_meas_names = ["slew_wl_gated_clk_bar"]+wl_en_driver_slew_names+["slew_wl_en", "slew_wl_bar"]+wl_driver_slew_names+["slew_wl"]
+            dc_slew_names = ["slew_delay_chain_stage_{0}".format(stage) for stage in range(1, self.get_num_delay_stages() + 1)]
+        self.wl_slew_meas_names = ["slew_wl_gated_clk_bar"] + wl_en_driver_slew_names + ["slew_wl_en", "slew_wl_bar"] + wl_driver_slew_names + ["slew_wl"]
         if port not in self.sram.readonly_ports:
-            self.rbl_slew_meas_names = ["slew_rbl_gated_clk_bar","slew_gated_clk_nand", "slew_delay_chain_in"]+dc_slew_names
+            self.rbl_slew_meas_names = ["slew_rbl_gated_clk_bar", "slew_gated_clk_nand", "slew_delay_chain_in"] + dc_slew_names
         else:
-            self.rbl_slew_meas_names = ["slew_rbl_gated_clk_bar"]+dc_slew_names
-        self.sae_slew_meas_names = ["slew_replica_bl0", "slew_pre_sen"]+sen_driver_slew_names+["slew_sen"]
+            self.rbl_slew_meas_names = ["slew_rbl_gated_clk_bar"] + dc_slew_names
+        self.sae_slew_meas_names = ["slew_replica_bl0", "slew_pre_sen"] + sen_driver_slew_names + ["slew_sen"]
 
         self.bitline_meas_names = ["delay_wl_to_bl", "delay_bl_to_dout"]
-        self.power_meas_names = ['read0_power']
+        self.power_meas_names = ["read0_power"]
 
     def create_signal_names(self, port):
         """Creates list of the signal names used in the spice file along the wl and sen paths.
@@ -83,40 +82,45 @@ class model_check(delay):
            replicated here.
         """
         delay.create_signal_names(self)
-        #Signal names are all hardcoded, need to update to make it work for probe address and different configurations.
-        wl_en_driver_signals = ["Xsram.Xcontrol{}.Xbuf_wl_en.Zb{}_int".format('{}', stage) for stage in range(1,self.get_num_wl_en_driver_stages())]
-        wl_driver_signals = ["Xsram.Xbank0.Xwordline_driver{}.Xwl_driver_inv{}.Zb{}_int".format('{}', self.wordline_row, stage) for stage in range(1,self.get_num_wl_driver_stages())]
-        sen_driver_signals = ["Xsram.Xcontrol{}.Xbuf_s_en.Zb{}_int".format('{}',stage) for stage in range(1,self.get_num_sen_driver_stages())]
+        
+        # Signal names are all hardcoded, need to update to make it work for probe address and different configurations.
+        wl_en_driver_signals = ["Xsram{1}Xcontrol{{}}.Xbuf_wl_en.Zb{0}_int".format(stage, OPTS.hier_seperator) for stage in range(1, self.get_num_wl_en_driver_stages())]
+        wl_driver_signals = ["Xsram{2}Xbank0{2}Xwordline_driver{{}}{2}Xwl_driver_inv{0}{2}Zb{1}_int".format(self.wordline_row, stage, OPTS.hier_seperator) for stage in range(1, self.get_num_wl_driver_stages())]
+        sen_driver_signals = ["Xsram{1}Xcontrol{{}}{1}Xbuf_s_en{1}Zb{0}_int".format(stage, OPTS.hier_seperator) for stage in range(1, self.get_num_sen_driver_stages())]
         if self.custom_delaychain:
             delay_chain_signal_names = []
         else:
-            delay_chain_signal_names = ["Xsram.Xcontrol{}.Xreplica_bitline.Xdelay_chain.dout_{}".format('{}', stage) for stage in range(1,self.get_num_delay_stages())]
+            delay_chain_signal_names = ["Xsram{1}Xcontrol{{}}{1}Xreplica_bitline{1}Xdelay_chain{1}dout_{0}".format(stage, OPTS.hier_seperator) for stage in range(1, self.get_num_delay_stages())]
         if len(self.sram.all_ports) > 1:
             port_format = '{}'
         else:
             port_format = ''
-        self.wl_signal_names = ["Xsram.Xcontrol{}.gated_clk_bar".format('{}')]+\
-                               wl_en_driver_signals+\
-                               ["Xsram.wl_en{}".format('{}'), "Xsram.Xbank0.Xwordline_driver{}.wl_bar_{}".format('{}',self.wordline_row)]+\
-                               wl_driver_signals+\
-                               ["Xsram.Xbank0.wl{}_{}".format(port_format, self.wordline_row)]
-        pre_delay_chain_names = ["Xsram.Xcontrol{}.gated_clk_bar".format('{}')]
+        self.wl_signal_names = ["Xsram{0}Xcontrol{{}}{0}gated_clk_bar".format(OPTS.hier_seperator)] + \
+                               wl_en_driver_signals + \
+                               ["Xsram{0}wl_en{{}}".format(OPTS.hier_seperator),
+                                "Xsram{1}Xbank0{1}Xwordline_driver{{}}{1}wl_bar_{0}".format(self.wordline_row,
+                                                                                            OPTS.hier_seperator)] + \
+                               wl_driver_signals + \
+                               ["Xsram{2}Xbank0{2}wl{0}_{1}".format(port_format,
+                                                                    self.wordline_row,
+                                                                    OPTS.hier_seperator)]
+        pre_delay_chain_names = ["Xsram.Xcontrol{{}}{0}gated_clk_bar".format(OPTS.hier_seperator)]
         if port not in self.sram.readonly_ports:
-            pre_delay_chain_names+= ["Xsram.Xcontrol{}.Xand2_rbl_in.zb_int".format('{}'), "Xsram.Xcontrol{}.rbl_in".format('{}')]
+            pre_delay_chain_names+= ["Xsram{0}Xcontrol{{}}{0}Xand2_rbl_in{0}zb_int".format(OPTS.hier_seperator),
+                                     "Xsram{0}Xcontrol{{}}{0}rbl_in".format(OPTS.hier_seperator)]
 
-        self.rbl_en_signal_names = pre_delay_chain_names+\
-                                   delay_chain_signal_names+\
-                                   ["Xsram.Xcontrol{}.Xreplica_bitline.delayed_en".format('{}')]
+        self.rbl_en_signal_names = pre_delay_chain_names + \
+                                   delay_chain_signal_names + \
+                                   ["Xsram{0}Xcontrol{{}}{0}Xreplica_bitline{0}delayed_en".format(OPTS.hier_seperator)]
 
+        self.sae_signal_names = ["Xsram{0}Xcontrol{{}}{0}Xreplica_bitline{0}bl0_0".format(OPTS.hier_seperator),
+                                 "Xsram{0}Xcontrol{{}}{0}pre_s_en".format(OPTS.hier_seperator)] + \
+                                sen_driver_signals + \
+                                ["Xsram{0}s_en{{}}".format(OPTS.hier_seperator)]
 
-        self.sae_signal_names = ["Xsram.Xcontrol{}.Xreplica_bitline.bl0_0".format('{}'), "Xsram.Xcontrol{}.pre_s_en".format('{}')]+\
-                                sen_driver_signals+\
-                                ["Xsram.s_en{}".format('{}')]
-
-        dout_name = "{0}{1}_{2}".format(self.dout_name,"{}",self.probe_data) #Empty values are the port and probe data bit
-        self.bl_signal_names = ["Xsram.Xbank0.wl{}_{}".format(port_format, self.wordline_row),\
-                                "Xsram.Xbank0.bl{}_{}".format(port_format, self.bitline_column),\
-                                dout_name]
+        self.bl_signal_names = ["Xsram{2}Xbank0{2}wl{0}_{1}".format(port_format, self.wordline_row, OPTS.hier_seperator),
+                                "Xsram{2}Xbank0{2}bl{0}_{1}".format(port_format, self.bitline_column, OPTS.hier_seperator),
+                                "{0}{{}}_{1}".format(self.dout_name, self.probe_data)] # Empty values are the port and probe data bit
 
     def create_measurement_objects(self):
         """Create the measurements used for read and write ports"""
@@ -124,7 +128,7 @@ class model_check(delay):
         self.create_sae_meas_objs()
         self.create_bl_meas_objs()
         self.create_power_meas_objs()
-        self.all_measures = self.wl_meas_objs+self.sae_meas_objs+self.bl_meas_objs+self.power_meas_objs
+        self.all_measures = self.wl_meas_objs + self.sae_meas_objs + self.bl_meas_objs + self.power_meas_objs
 
     def create_power_meas_objs(self):
         """Create power measurement object. Only one."""
@@ -138,14 +142,14 @@ class model_check(delay):
         targ_dir = "FALL"
 
         for i in range(1, len(self.wl_signal_names)):
-            self.wl_meas_objs.append(delay_measure(self.wl_delay_meas_names[i-1],
-                                                   self.wl_signal_names[i-1],
+            self.wl_meas_objs.append(delay_measure(self.wl_delay_meas_names[i - 1],
+                                                   self.wl_signal_names[i - 1],
                                                    self.wl_signal_names[i],
                                                    trig_dir,
                                                    targ_dir,
                                                    measure_scale=1e9))
-            self.wl_meas_objs.append(slew_measure(self.wl_slew_meas_names[i-1],
-                                                  self.wl_signal_names[i-1],
+            self.wl_meas_objs.append(slew_measure(self.wl_slew_meas_names[i - 1],
+                                                  self.wl_signal_names[i - 1],
                                                   trig_dir,
                                                   measure_scale=1e9))
             temp_dir = trig_dir
@@ -155,9 +159,9 @@ class model_check(delay):
 
     def create_bl_meas_objs(self):
         """Create the measurements to measure the bitline to dout, static stages"""
-        #Bitline has slightly different measurements, objects appends hardcoded.
+        # Bitline has slightly different measurements, objects appends hardcoded.
         self.bl_meas_objs = []
-        trig_dir, targ_dir = "RISE", "FALL" #Only check read 0
+        trig_dir, targ_dir = "RISE", "FALL" # Only check read 0
         self.bl_meas_objs.append(delay_measure(self.bitline_meas_names[0],
                                                    self.bl_signal_names[0],
                                                    self.bl_signal_names[-1],
@@ -171,22 +175,22 @@ class model_check(delay):
         self.sae_meas_objs = []
         trig_dir = "RISE"
         targ_dir = "FALL"
-        #Add measurements from gated_clk_bar to RBL
+        # Add measurements from gated_clk_bar to RBL
         for i in range(1, len(self.rbl_en_signal_names)):
-            self.sae_meas_objs.append(delay_measure(self.rbl_delay_meas_names[i-1],
-                                                    self.rbl_en_signal_names[i-1],
+            self.sae_meas_objs.append(delay_measure(self.rbl_delay_meas_names[i - 1],
+                                                    self.rbl_en_signal_names[i - 1],
                                                     self.rbl_en_signal_names[i],
                                                     trig_dir,
                                                     targ_dir,
                                                     measure_scale=1e9))
-            self.sae_meas_objs.append(slew_measure(self.rbl_slew_meas_names[i-1],
-                                                   self.rbl_en_signal_names[i-1],
+            self.sae_meas_objs.append(slew_measure(self.rbl_slew_meas_names[i - 1],
+                                                   self.rbl_en_signal_names[i - 1],
                                                    trig_dir,
                                                    measure_scale=1e9))
             temp_dir = trig_dir
             trig_dir = targ_dir
             targ_dir = temp_dir
-        if self.custom_delaychain: #Hack for custom delay chains
+        if self.custom_delaychain: # Hack for custom delay chains
             self.sae_meas_objs[-2] = delay_measure(self.rbl_delay_meas_names[-1],
                                                     self.rbl_en_signal_names[-2],
                                                     self.rbl_en_signal_names[-1],
@@ -198,18 +202,18 @@ class model_check(delay):
                                                trig_dir,
                                                measure_scale=1e9))
 
-        #Add measurements from rbl_out to sae. Trigger directions do not invert from previous stage due to RBL.
+        # Add measurements from rbl_out to sae. Trigger directions do not invert from previous stage due to RBL.
         trig_dir = "FALL"
         targ_dir = "RISE"
         for i in range(1, len(self.sae_signal_names)):
-            self.sae_meas_objs.append(delay_measure(self.sae_delay_meas_names[i-1],
-                                                    self.sae_signal_names[i-1],
+            self.sae_meas_objs.append(delay_measure(self.sae_delay_meas_names[i - 1],
+                                                    self.sae_signal_names[i - 1],
                                                     self.sae_signal_names[i],
                                                     trig_dir,
                                                     targ_dir,
                                                     measure_scale=1e9))
-            self.sae_meas_objs.append(slew_measure(self.sae_slew_meas_names[i-1],
-                                                   self.sae_signal_names[i-1],
+            self.sae_meas_objs.append(slew_measure(self.sae_slew_meas_names[i - 1],
+                                                   self.sae_signal_names[i - 1],
                                                    trig_dir,
                                                    measure_scale=1e9))
             temp_dir = trig_dir
@@ -231,16 +235,16 @@ class model_check(delay):
             self.sf.write("* {}\n".format(comment))
 
         for read_port in self.targ_read_ports:
-           self.write_measures_read_port(read_port)
+            self.write_measures_read_port(read_port)
 
     def get_delay_measure_variants(self, port, measure_obj):
         """Get the measurement values that can either vary from simulation to simulation (vdd, address)
            or port to port (time delays)"""
-        #Return value is intended to match the delay measure format:  trig_td, targ_td, vdd, port
-        #Assuming only read 0 for now
-        debug.info(3,"Power measurement={}".format(measure_obj))
+        # Return value is intended to match the delay measure format:  trig_td, targ_td, vdd, port
+        # Assuming only read 0 for now
+        debug.info(3, "Power measurement={}".format(measure_obj))
         if (type(measure_obj) is delay_measure or type(measure_obj) is slew_measure):
-            meas_cycle_delay = self.cycle_times[self.measure_cycles[port]["read0"]] + self.period/2
+            meas_cycle_delay = self.cycle_times[self.measure_cycles[port]["read0"]] + self.period / 2
             return (meas_cycle_delay, meas_cycle_delay, self.vdd_voltage, port)
         elif type(measure_obj) is power_measure:
             return self.get_power_measure_variants(port, measure_obj, "read")
@@ -249,9 +253,9 @@ class model_check(delay):
 
     def get_power_measure_variants(self, port, power_obj, operation):
         """Get the measurement values that can either vary port to port (time delays)"""
-        #Return value is intended to match the power measure format:  t_initial, t_final, port
+        # Return value is intended to match the power measure format:  t_initial, t_final, port
         t_initial = self.cycle_times[self.measure_cycles[port]["read0"]]
-        t_final = self.cycle_times[self.measure_cycles[port]["read0"]+1]
+        t_final = self.cycle_times[self.measure_cycles[port]["read0"] + 1]
 
         return (t_initial, t_final, port)
 
@@ -280,8 +284,8 @@ class model_check(delay):
             elif type(measure)is power_measure:
                 power_meas_list.append(measure_value)
             else:
-                debug.error("Measurement object not recognized.",1)
-        return delay_meas_list, slew_meas_list,power_meas_list
+                debug.error("Measurement object not recognized.", 1)
+        return delay_meas_list, slew_meas_list, power_meas_list
 
     def run_delay_simulation(self):
         """
@@ -290,7 +294,7 @@ class model_check(delay):
         works on the trimmed netlist by default, so powers do not
         include leakage of all cells.
         """
-        #Sanity Check
+        # Sanity Check
         debug.check(self.period > 0, "Target simulation period non-positive")
 
         wl_delay_result = [[] for i in self.all_ports]
@@ -303,16 +307,16 @@ class model_check(delay):
         # Checking from not data_value to data_value
         self.write_delay_stimulus()
 
-        self.stim.run_sim() #running sim prodoces spice output file.
+        self.stim.run_sim() # running sim prodoces spice output file.
 
-        #Retrieve the results from the output file
+        # Retrieve the results from the output file
         for port in self.targ_read_ports:
-            #Parse and check the voltage measurements
-            wl_delay_result[port], wl_slew_result[port],_ = self.get_measurement_values(self.wl_meas_objs, port)
-            sae_delay_result[port], sae_slew_result[port],_ = self.get_measurement_values(self.sae_meas_objs, port)
-            bl_delay_result[port], bl_slew_result[port],_ = self.get_measurement_values(self.bl_meas_objs, port)
-            _,__,power_result[port] = self.get_measurement_values(self.power_meas_objs, port)
-        return (True,wl_delay_result, sae_delay_result, wl_slew_result, sae_slew_result, bl_delay_result, bl_slew_result, power_result)
+            # Parse and check the voltage measurements
+            wl_delay_result[port], wl_slew_result[port], _ = self.get_measurement_values(self.wl_meas_objs, port)
+            sae_delay_result[port], sae_slew_result[port], _ = self.get_measurement_values(self.sae_meas_objs, port)
+            bl_delay_result[port], bl_slew_result[port], _ = self.get_measurement_values(self.bl_meas_objs, port)
+            _, __, power_result[port] = self.get_measurement_values(self.power_meas_objs, port)
+        return (True, wl_delay_result, sae_delay_result, wl_slew_result, sae_slew_result, bl_delay_result, bl_slew_result, power_result)
 
     def get_model_delays(self, port):
         """Get model delays based on port. Currently assumes single RW port."""
@@ -345,41 +349,41 @@ class model_check(delay):
     def scale_delays(self, delay_list):
         """Takes in a list of measured delays and convert it to simple units to easily compare to model values."""
         converted_values = []
-        #Calculate average
+        # Calculate average
         total = 0
         for meas_value in delay_list:
             total+=meas_value
-        average = total/len(delay_list)
+        average = total / len(delay_list)
 
-        #Convert values
+        # Convert values
         for meas_value in delay_list:
-            converted_values.append(meas_value/average)
+            converted_values.append(meas_value / average)
         return converted_values
 
     def min_max_normalization(self, value_list):
         """Re-scales input values on a range from 0-1 where min(list)=0, max(list)=1"""
         scaled_values = []
         min_max_diff = max(value_list) - min(value_list)
-        average = sum(value_list)/len(value_list)
+        average = sum(value_list) / len(value_list)
         for value in value_list:
-            scaled_values.append((value-average)/(min_max_diff))
+            scaled_values.append((value - average) / (min_max_diff))
         return scaled_values
 
     def calculate_error_l2_norm(self, list_a, list_b):
         """Calculates error between two lists using the l2 norm"""
         error_list = []
         for val_a, val_b in zip(list_a, list_b):
-            error_list.append((val_a-val_b)**2)
+            error_list.append((val_a - val_b)**2)
         return error_list
 
     def compare_measured_and_model(self, measured_vals, model_vals):
         """First scales both inputs into similar ranges and then compares the error between both."""
         scaled_meas = self.min_max_normalization(measured_vals)
-        debug.info(1, "Scaled measurements:\n{}".format(scaled_meas))
+        debug.info(1, "Scaled measurements:\n{0}".format(scaled_meas))
         scaled_model = self.min_max_normalization(model_vals)
-        debug.info(1, "Scaled model:\n{}".format(scaled_model))
+        debug.info(1, "Scaled model:\n{0}".format(scaled_model))
         errors = self.calculate_error_l2_norm(scaled_meas, scaled_model)
-        debug.info(1, "Errors:\n{}\n".format(errors))
+        debug.info(1, "Errors:\n{0}\n".format(errors))
 
     def analyze(self, probe_address, probe_data, slews, loads, port):
         """Measures entire delay path along the wordline and sense amp enable and compare it to the model delays."""
@@ -391,19 +395,19 @@ class model_check(delay):
         self.create_measurement_objects()
         data_dict = {}
 
-        read_port = self.read_ports[0] #only test the first read port
+        read_port = self.read_ports[0] # only test the first read port
         read_port = port
         self.targ_read_ports = [read_port]
         self.targ_write_ports = [self.write_ports[0]]
-        debug.info(1,"Model test: corner {}".format(self.corner))
+        debug.info(1, "Model test: corner {0}".format(self.corner))
         (success, wl_delays, sae_delays, wl_slews, sae_slews, bl_delays, bl_slews, powers)=self.run_delay_simulation()
-        debug.check(success, "Model measurements Failed: period={}".format(self.period))
+        debug.check(success, "Model measurements Failed: period={0}".format(self.period))
 
-        debug.info(1,"Measured Wordline delays (ns):\n\t {}".format(wl_delays[read_port]))
-        debug.info(1,"Measured Wordline slews:\n\t {}".format(wl_slews[read_port]))
-        debug.info(1,"Measured SAE delays (ns):\n\t {}".format(sae_delays[read_port]))
-        debug.info(1,"Measured SAE slews:\n\t {}".format(sae_slews[read_port]))
-        debug.info(1,"Measured Bitline delays (ns):\n\t {}".format(bl_delays[read_port]))
+        debug.info(1, "Measured Wordline delays (ns):\n\t {0}".format(wl_delays[read_port]))
+        debug.info(1, "Measured Wordline slews:\n\t {0}".format(wl_slews[read_port]))
+        debug.info(1, "Measured SAE delays (ns):\n\t {0}".format(sae_delays[read_port]))
+        debug.info(1, "Measured SAE slews:\n\t {0}".format(sae_slews[read_port]))
+        debug.info(1, "Measured Bitline delays (ns):\n\t {0}".format(bl_delays[read_port]))
 
         data_dict[self.wl_meas_name] = wl_delays[read_port]
         data_dict[self.sae_meas_name] = sae_delays[read_port]
@@ -412,14 +416,14 @@ class model_check(delay):
         data_dict[self.bl_meas_name] = bl_delays[read_port]
         data_dict[self.power_name] = powers[read_port]
 
-        if OPTS.auto_delay_chain_sizing: #Model is not used in this case
+        if OPTS.auto_delay_chain_sizing: # Model is not used in this case
             wl_model_delays, sae_model_delays = self.get_model_delays(read_port)
-            debug.info(1,"Wordline model delays:\n\t {}".format(wl_model_delays))
-            debug.info(1,"SAE model delays:\n\t {}".format(sae_model_delays))
+            debug.info(1, "Wordline model delays:\n\t {0}".format(wl_model_delays))
+            debug.info(1, "SAE model delays:\n\t {0}".format(sae_model_delays))
             data_dict[self.wl_model_name] = wl_model_delays
             data_dict[self.sae_model_name] = sae_model_delays
 
-        #Some evaluations of the model and measured values
+        # Some evaluations of the model and measured values
         # debug.info(1, "Comparing wordline measurements and model.")
         # self.compare_measured_and_model(wl_delays[read_port], wl_model_delays)
         # debug.info(1, "Comparing SAE measurements and model")
@@ -430,17 +434,17 @@ class model_check(delay):
     def get_all_signal_names(self):
         """Returns all signals names as a dict indexed by hardcoded names. Useful for writing the head of the CSV."""
         name_dict = {}
-        #Signal names are more descriptive than the measurement names, first value trimmed to match size of measurements names.
+        # Signal names are more descriptive than the measurement names, first value trimmed to match size of measurements names.
         name_dict[self.wl_meas_name] = self.wl_signal_names[1:]
-        name_dict[self.sae_meas_name] = self.rbl_en_signal_names[1:]+self.sae_signal_names[1:]
+        name_dict[self.sae_meas_name] = self.rbl_en_signal_names[1:] + self.sae_signal_names[1:]
         name_dict[self.wl_slew_name] = self.wl_slew_meas_names
-        name_dict[self.sae_slew_name] = self.rbl_slew_meas_names+self.sae_slew_meas_names
+        name_dict[self.sae_slew_name] = self.rbl_slew_meas_names + self.sae_slew_meas_names
         name_dict[self.bl_meas_name] = self.bitline_meas_names[0:1]
         name_dict[self.power_name] = self.power_meas_names
-        #name_dict[self.wl_slew_name] = self.wl_slew_meas_names
+        # pname_dict[self.wl_slew_name] = self.wl_slew_meas_names
 
         if OPTS.auto_delay_chain_sizing:
-            name_dict[self.wl_model_name] = name_dict["wl_measures"] #model uses same names as measured.
+            name_dict[self.wl_model_name] = name_dict["wl_measures"] # model uses same names as measured.
             name_dict[self.sae_model_name] = name_dict["sae_measures"]
 
         return name_dict

compiler/characterizer/regression_model.py

@@ -13,7 +13,8 @@ import debug
 
 import math
 
-relative_data_path = "/sim_data"
+relative_data_path = "sim_data"
+data_file = "sim_data.csv"
 data_fnames = ["rise_delay.csv",
                "fall_delay.csv",
                "rise_slew.csv",
@@ -22,7 +23,8 @@ data_fnames = ["rise_delay.csv",
                "write0_power.csv",
                "read1_power.csv",
                "read0_power.csv",
-               "leakage_data.csv"]
+               "leakage_data.csv",
+               "sim_time.csv"]
 # Positions must correspond to data_fname list               
 lib_dnames = ["delay_lh",
               "delay_hl",
@@ -32,14 +34,15 @@ lib_dnames = ["delay_lh",
               "write0_power",
               "read1_power",
               "read0_power",
-              "leakage_power"] 
+              "leakage_power",
+              "sim_time"] 
 # Check if another data dir was specified
 if OPTS.sim_data_path == None:              
     data_dir = OPTS.openram_tech+relative_data_path
 else:
     data_dir = OPTS.sim_data_path 
     
-data_paths = {dname:data_dir +'/'+fname for dname, fname in zip(lib_dnames, data_fnames)}
+data_path = data_dir + '/' + data_file
 
 class regression_model(simulation):
 
@@ -47,7 +50,7 @@ class regression_model(simulation):
         super().__init__(sram, spfile, corner)
         self.set_corner(corner)
 
-    def get_lib_values(self, slews, loads):
+    def get_lib_values(self, load_slews):
         """
         A model and prediction is created for each output needed for the LIB 
         """
@@ -56,12 +59,16 @@ class regression_model(simulation):
         log_num_words = math.log(OPTS.num_words, 2)
         model_inputs = [log_num_words, 
                         OPTS.word_size, 
-                        OPTS.words_per_row, 
-                        self.sram.width * self.sram.height,
+                        OPTS.words_per_row,
+                        OPTS.local_array_size,
                         process_transform[self.process], 
                         self.vdd_voltage, 
                         self.temperature]  
-
+                        # Area removed for now
+                        # self.sram.width * self.sram.height,
+        # Include above inputs, plus load and slew which are added below
+        self.num_inputs = len(model_inputs)+2
+        
         self.create_measurement_names()
         models = self.train_models()
 
@@ -69,36 +76,35 @@ class regression_model(simulation):
         port_data = self.get_empty_measure_data_dict()
         debug.info(1, 'Slew, Load, Port, Delay(ns), Slew(ns)')
         max_delay = 0.0
-        for slew in slews:
-            for load in loads:
-                # List returned with value order being delay, power, leakage, slew
-                sram_vals = self.get_predictions(model_inputs+[slew, load], models)
-                # Delay is only calculated on a single port and replicated for now.
-                for port in self.all_ports:
-                    port_data[port]['delay_lh'].append(sram_vals['delay_lh'])
-                    port_data[port]['delay_hl'].append(sram_vals['delay_hl'])
-                    port_data[port]['slew_lh'].append(sram_vals['slew_lh'])
-                    port_data[port]['slew_hl'].append(sram_vals['slew_hl'])
+        for load, slew in load_slews:
+            # List returned with value order being delay, power, leakage, slew
+            sram_vals = self.get_predictions(model_inputs+[slew, load], models)
+            # Delay is only calculated on a single port and replicated for now.
+            for port in self.all_ports:
+                port_data[port]['delay_lh'].append(sram_vals['rise_delay'])
+                port_data[port]['delay_hl'].append(sram_vals['fall_delay'])
+                port_data[port]['slew_lh'].append(sram_vals['rise_slew'])
+                port_data[port]['slew_hl'].append(sram_vals['fall_slew'])
+                
+                port_data[port]['write1_power'].append(sram_vals['write1_power'])
+                port_data[port]['write0_power'].append(sram_vals['write0_power'])
+                port_data[port]['read1_power'].append(sram_vals['read1_power'])
+                port_data[port]['read0_power'].append(sram_vals['read0_power'])
+                
+                # Disabled power not modeled. Copied from other power predictions
+                port_data[port]['disabled_write1_power'].append(sram_vals['write1_power'])
+                port_data[port]['disabled_write0_power'].append(sram_vals['write0_power'])
+                port_data[port]['disabled_read1_power'].append(sram_vals['read1_power'])
+                port_data[port]['disabled_read0_power'].append(sram_vals['read0_power'])
                     
-                    port_data[port]['write1_power'].append(sram_vals['write1_power'])
-                    port_data[port]['write0_power'].append(sram_vals['write0_power'])
-                    port_data[port]['read1_power'].append(sram_vals['read1_power'])
-                    port_data[port]['read0_power'].append(sram_vals['read0_power'])
-                    
-                    # Disabled power not modeled. Copied from other power predictions
-                    port_data[port]['disabled_write1_power'].append(sram_vals['write1_power'])
-                    port_data[port]['disabled_write0_power'].append(sram_vals['write0_power'])
-                    port_data[port]['disabled_read1_power'].append(sram_vals['read1_power'])
-                    port_data[port]['disabled_read0_power'].append(sram_vals['read0_power'])
-                        
-                    debug.info(1, '{}, {}, {}, {}, {}'.format(slew, 
-                                                                                 load, 
-                                                                                 port, 
-                                                                                 sram_vals['delay_lh'], 
-                                                                                 sram_vals['slew_lh']))
+                debug.info(1, '{}, {}, {}, {}, {}'.format(slew, 
+                                                          load, 
+                                                          port, 
+                                                          sram_vals['rise_delay'], 
+                                                          sram_vals['rise_slew']))
         # Estimate the period as double the delay with margin
         period_margin = 0.1
-        sram_data = {"min_period": sram_vals['delay_lh'] * 2,
+        sram_data = {"min_period": sram_vals['rise_delay'] * 2,
                      "leakage_power": sram_vals["leakage_power"]}
 
         debug.info(2, "SRAM Data:\n{}".format(sram_data))
@@ -111,30 +117,46 @@ class regression_model(simulation):
         Generate a model and prediction for LIB output
         """
         
-        #Scaled the inputs using first data file as a reference
-        data_name = lib_dnames[0]       
-        scaled_inputs = np.asarray([scale_input_datapoint(model_inputs, data_paths[data_name])])
+        #Scaled the inputs using first data file as a reference    
+        scaled_inputs = np.asarray([scale_input_datapoint(model_inputs, data_path)])
 
         predictions = {}
-        for dname in data_paths.keys():
-            path = data_paths[dname]
+        out_pos = 0
+        for dname in self.output_names:
             m = models[dname]
         
-            features, labels = get_scaled_data(path)
             scaled_pred = self.model_prediction(m, scaled_inputs)
-            pred = unscale_data(scaled_pred.tolist(), path)
+            pred = unscale_data(scaled_pred.tolist(), data_path, pos=self.num_inputs+out_pos)
             debug.info(2,"Unscaled Prediction = {}".format(pred))
-            predictions[dname] = pred[0][0]
+            predictions[dname] = pred[0]
+            out_pos+=1
         return predictions
 
     def train_models(self):
         """
         Generate and return models
         """
+        self.output_names = get_data_names(data_path)[self.num_inputs:]
+        data = get_scaled_data(data_path)
+        features, labels = data[:, :self.num_inputs], data[:,self.num_inputs:]
+
+        output_num = 0
         models = {}
-        for dname, dpath in data_paths.items():
-            features, labels = get_scaled_data(dpath)
-            model = self.generate_model(features, labels)
-            models[dname] = model
+        for o_name in self.output_names:
+            output_label = labels[:,output_num]
+            model = self.generate_model(features, output_label)
+            models[o_name] = model
+            output_num+=1
+
         return models
+    
+    # Fixme - only will work for sklearn regression models
+    def save_model(self, model_name, model):
+        try:
+            OPTS.model_dict
+        except AttributeError:
+            OPTS.model_dict = {}
+        OPTS.model_dict[model_name+"_coef"] = list(model.coef_[0])
+        debug.info(1,"Coefs of {}:{}".format(model_name,OPTS.model_dict[model_name+"_coef"]))
+        OPTS.model_dict[model_name+"_intercept"] = float(model.intercept_)
         

compiler/characterizer/setup_hold.py

@@ -76,10 +76,10 @@ class setup_hold():
         self.stim.write_supply()
 
     def write_data(self, mode, target_time, correct_value):
-        """Create the data signals for setup/hold analysis. First period is to
+        """
+        Create the data signals for setup/hold analysis. First period is to
         initialize it to the opposite polarity. Second period is used for
         characterization.
-
         """
         self.sf.write("\n* Generation of the data and clk signals\n")
         if correct_value == 1:
@@ -106,8 +106,11 @@ class setup_hold():
                           setup=0)
 
     def write_clock(self):
-        """ Create the clock signal for setup/hold analysis. First period initializes the FF
-        while the second is used for characterization."""
+        """ 
+        Create the clock signal for setup/hold analysis. 
+        First period initializes the FF
+        while the second is used for characterization.
+        """
 
         self.stim.gen_pwl(sig_name="clk",
                           # initial clk edge is right after the 0 time to initialize a flop
@@ -128,16 +131,6 @@ class setup_hold():
         else:
             dout_rise_or_fall = "FALL"
 
-        # in SETUP mode, the input mirrors what the output should be
-        if mode == "SETUP":
-            din_rise_or_fall = dout_rise_or_fall
-        else:
-            # in HOLD mode, however, the input should be opposite of the output
-            if correct_value == 1:
-                din_rise_or_fall = "FALL"
-            else:
-                din_rise_or_fall = "RISE"
-
         self.sf.write("\n* Measure statements for pass/fail verification\n")
         trig_name = "clk"
         targ_name = "Q"
@@ -153,19 +146,6 @@ class setup_hold():
                                  trig_td=1.9 * self.period,
                                  targ_td=1.9 * self.period)
 
-        targ_name = "D"
-        # Start triggers right after initialize value is returned to normal
-        # at one period
-        self.stim.gen_meas_delay(meas_name="setup_hold_time",
-                                 trig_name=trig_name,
-                                 targ_name=targ_name,
-                                 trig_val=trig_val,
-                                 targ_val=targ_val,
-                                 trig_dir="RISE",
-                                 targ_dir=din_rise_or_fall,
-                                 trig_td=1.2 * self.period,
-                                 targ_td=1.2 * self.period)
-
     def bidir_search(self, correct_value, mode):
         """ This will perform a bidirectional search for either setup or hold times.
         It starts with the feasible priod and looks a half period beyond or before it
@@ -189,26 +169,28 @@ class setup_hold():
                             correct_value=correct_value)
         self.stim.run_sim(self.stim_sp)
         ideal_clk_to_q = convert_to_float(parse_spice_list("timing", "clk2q_delay"))
-        setuphold_time = convert_to_float(parse_spice_list("timing", "setup_hold_time"))
-        debug.info(2,"*** {0} CHECK: {1} Ideal Clk-to-Q: {2} Setup/Hold: {3}".format(mode, correct_value,ideal_clk_to_q,setuphold_time))
+        # We use a 1/2 speed clock for some reason...
+        setuphold_time = (feasible_bound - 2 * self.period)
+        if mode == "SETUP": # SETUP is clk-din, not din-clk
+            passing_setuphold_time = -1 * setuphold_time
+        else:
+            passing_setuphold_time = setuphold_time
+        debug.info(2, "*** {0} CHECK: {1} Ideal Clk-to-Q: {2} Setup/Hold: {3}".format(mode,
+                                                                                      correct_value,
+                                                                                      ideal_clk_to_q,
+                                                                                      setuphold_time))
 
-        if type(ideal_clk_to_q)!=float or type(setuphold_time)!=float:
-            debug.error("Initial hold time fails for data value feasible bound {0} Clk-to-Q {1} Setup/Hold {2}".format(feasible_bound,
-                                                                                                                       ideal_clk_to_q,
-                                                                                                                       setuphold_time),
+        if type(ideal_clk_to_q)!=float:
+            debug.error("Initial hold time fails for data value feasible "
+                        "bound {0} Clk-to-Q {1} Setup/Hold {2}".format(feasible_bound,
+                                                                       ideal_clk_to_q,
+                                                                       setuphold_time),
                         2)
 
-        if mode == "SETUP": # SETUP is clk-din, not din-clk
-            setuphold_time *= -1e9
-        else:
-            setuphold_time *= 1e9
-
-        passing_setuphold_time = setuphold_time
         debug.info(2, "Checked initial {0} time {1}, data at {2}, clock at {3} ".format(mode,
                                                                                         setuphold_time,
                                                                                         feasible_bound,
                                                                                         2 * self.period))
-        #raw_input("Press Enter to continue...")
 
         while True:
             target_time = (feasible_bound + infeasible_bound) / 2
@@ -224,15 +206,14 @@ class setup_hold():
 
             self.stim.run_sim(self.stim_sp)
             clk_to_q = convert_to_float(parse_spice_list("timing", "clk2q_delay"))
-            setuphold_time = convert_to_float(parse_spice_list("timing", "setup_hold_time"))
-            if type(clk_to_q) == float and (clk_to_q < 1.1 * ideal_clk_to_q) and type(setuphold_time)==float:
-                if mode == "SETUP": # SETUP is clk-din, not din-clk
-                    setuphold_time *= -1e9
-                else:
-                    setuphold_time *= 1e9
-
-                debug.info(2, "PASS Clk-to-Q: {0} Setup/Hold: {1}".format(clk_to_q, setuphold_time))
+            # We use a 1/2 speed clock for some reason...            
+            setuphold_time = (target_time - 2 * self.period)
+            if mode == "SETUP": # SETUP is clk-din, not din-clk
+                passing_setuphold_time = -1 * setuphold_time
+            else:
                 passing_setuphold_time = setuphold_time
+            if type(clk_to_q) == float and (clk_to_q < 1.1 * ideal_clk_to_q):
+                debug.info(2, "PASS Clk-to-Q: {0} Setup/Hold: {1}".format(clk_to_q, setuphold_time))
                 feasible_bound = target_time
             else:
                 debug.info(2, "FAIL Clk-to-Q: {0} Setup/Hold: {1}".format(clk_to_q, setuphold_time))
@@ -242,7 +223,6 @@ class setup_hold():
                 debug.info(3, "CONVERGE {0} vs {1}".format(feasible_bound, infeasible_bound))
                 break
 
-
         debug.info(2, "Converged on {0} time {1}.".format(mode, passing_setuphold_time))
         return passing_setuphold_time
 

compiler/characterizer/simulation.py

@@ -586,7 +586,7 @@ class simulation():
             bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set))
         if OPTS.use_pex and OPTS.pex_exe[0] != "calibre":
             for i in range(len(bl_names)):
-                bl_names[i] = bl_names[i].split('.')[-1]
+                bl_names[i] = bl_names[i].split(OPTS.hier_seperator)[-1]
         return bl_names[0], bl_names[1]
         
     def get_empty_measure_data_dict(self):

compiler/characterizer/stimuli.py

@@ -22,7 +22,7 @@ from globals import OPTS
 class stimuli():
     """ Class for providing stimuli functions """
 
-    def __init__(self, stim_file, corner):
+    def __init__(self, stim_file, corner):        
         self.vdd_name = "vdd"
         self.gnd_name = "gnd"
         self.pmos_name = tech.spice["pmos"]
@@ -146,7 +146,7 @@ class stimuli():
             edge. The first clk_time should be 0 and is the initial time that corresponds
             to the initial value.
         """
-        # the initial value is not a clock time
+
         str = "Clock and data value lengths don't match. {0} clock values, {1} data values for {2}"
         debug.check(len(clk_times)==len(data_values),
                     str.format(len(clk_times),
@@ -181,7 +181,7 @@ class stimuli():
     def gen_meas_delay(self, meas_name, trig_name, targ_name, trig_val, targ_val, trig_dir, targ_dir, trig_td, targ_td):
         """ Creates the .meas statement for the measurement of delay """
         measure_string=".meas tran {0} TRIG v({1}) VAL={2} {3}=1 TD={4}n TARG v({5}) VAL={6} {7}=1 TD={8}n\n\n"
-        self.sf.write(measure_string.format(meas_name,
+        self.sf.write(measure_string.format(meas_name.lower(),
                                             trig_name,
                                             trig_val,
                                             trig_dir,
@@ -194,7 +194,7 @@ class stimuli():
     def gen_meas_find_voltage(self, meas_name, trig_name, targ_name, trig_val, trig_dir, trig_td):
         """ Creates the .meas statement for the measurement of delay """
         measure_string=".meas tran {0} FIND v({1}) WHEN v({2})={3}v {4}=1 TD={5}n \n\n"
-        self.sf.write(measure_string.format(meas_name,
+        self.sf.write(measure_string.format(meas_name.lower(),
                                             targ_name,
                                             trig_name,
                                             trig_val,
@@ -204,7 +204,7 @@ class stimuli():
     def gen_meas_find_voltage_at_time(self, meas_name, targ_name, time_at):
         """ Creates the .meas statement for voltage at time"""
         measure_string=".meas tran {0} FIND v({1}) AT={2}n \n\n"
-        self.sf.write(measure_string.format(meas_name,
+        self.sf.write(measure_string.format(meas_name.lower(),
                                             targ_name,
                                             time_at))
 
@@ -215,13 +215,13 @@ class stimuli():
             power_exp = "power"
         else:
             power_exp = "par('(-1*v(" + str(self.vdd_name) + ")*I(v" + str(self.vdd_name) + "))')"
-        self.sf.write(".meas tran {0} avg {1} from={2}n to={3}n\n\n".format(meas_name,
+        self.sf.write(".meas tran {0} avg {1} from={2}n to={3}n\n\n".format(meas_name.lower(),
                                                                             power_exp,
                                                                             t_initial,
                                                                             t_final))
 
     def gen_meas_value(self, meas_name, dout, t_initial, t_final):
-        measure_string=".meas tran {0} AVG v({1}) FROM={2}n TO={3}n\n\n".format(meas_name, dout, t_initial, t_final)
+        measure_string=".meas tran {0} AVG v({1}) FROM={2}n TO={3}n\n\n".format(meas_name.lower(), dout, t_initial, t_final)
         self.sf.write(measure_string)
 
     def write_control(self, end_time, runlvl=4):
@@ -238,8 +238,8 @@ class stimuli():
             reltol = 0.001 # 0.1%
         timestep = 10 # ps, was 5ps but ngspice was complaining the timestep was too small in certain tests.
 
-        self.sf.write(".TEMP {}\n".format(self.temperature))
         if OPTS.spice_name == "ngspice":
+            self.sf.write(".TEMP {}\n".format(self.temperature))
             # UIC is needed for ngspice to converge
             self.sf.write(".TRAN {0}p {1}n UIC\n".format(timestep, end_time))
             # ngspice sometimes has convergence problems if not using gear method
@@ -248,6 +248,7 @@ class stimuli():
             # unless you figure out what these are.
             self.sf.write(".OPTIONS POST=1 RELTOL={0} PROBE method=gear ACCT\n".format(reltol))
         elif OPTS.spice_name == "spectre":
+            self.sf.write(".TEMP {}\n".format(self.temperature))
             self.sf.write("simulator lang=spectre\n")
             if OPTS.use_pex:
                 nestlvl = 1
@@ -255,8 +256,7 @@ class stimuli():
             else:
                 nestlvl = 10
                 spectre_save = "lvlpub"
-            self.sf.write('saveOptions options save={} nestlvl={} pwr=total \n'.format(
-                spectre_save, nestlvl))
+            self.sf.write('saveOptions options save={} nestlvl={} pwr=total \n'.format(spectre_save, nestlvl))
             self.sf.write("simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp={0} try_fast_op=no "
                           "rforce=10m maxnotes=10 maxwarns=10 "
                           " preservenode=all topcheck=fixall "
@@ -265,12 +265,19 @@ class stimuli():
             self.sf.write('tran tran step={} stop={}n ic=node write=spectre.dc errpreset=moderate '
                           ' annotate=status maxiters=5 \n'.format("5p", end_time))
             self.sf.write("simulator lang=spice\n")
-        else:
+        elif OPTS.spice_name in ["hspice", "xa"]:
+            self.sf.write(".TEMP {}\n".format(self.temperature))
             self.sf.write(".TRAN {0}p {1}n UIC\n".format(timestep, end_time))
             self.sf.write(".OPTIONS POST=1 RUNLVL={0} PROBE\n".format(runlvl))
-            if OPTS.spice_name == "hspice":  # for cadence plots
-                self.sf.write(".OPTIONS PSF=1 \n")
-                self.sf.write(".OPTIONS HIER_DELIM=1 \n")
+            self.sf.write(".OPTIONS PSF=1 \n")
+            self.sf.write(".OPTIONS HIER_DELIM=1 \n")
+        elif OPTS.spice_name in ["Xyce", "xyce"]:
+            self.sf.write(".OPTIONS DEVICE TEMP={}\n".format(self.temperature))
+            self.sf.write(".OPTIONS MEASURE MEASFAIL=1\n")
+            self.sf.write(".OPTIONS LINSOL type=klu\n")
+            self.sf.write(".TRAN {0}p {1}n\n".format(timestep, end_time))
+        else:
+            debug.error("Unkown spice simulator {}".format(OPTS.spice_name))
 
         # create plots for all signals
         if not OPTS.use_pex:   # Don't save all for extracted simulations
@@ -278,7 +285,7 @@ class stimuli():
             if OPTS.verbose_level>0:
                 if OPTS.spice_name in ["hspice", "xa"]:
                     self.sf.write(".probe V(*)\n")
-                else:
+                elif OPTS.spice_name != "Xyce":
                     self.sf.write(".plot V(*)\n")
             else:
                 self.sf.write("*.probe V(*)\n")
@@ -312,7 +319,10 @@ class stimuli():
 
         # Adding a commented out supply for simulators where gnd and 0 are not global grounds.
         self.sf.write("\n*Nodes gnd and 0 are the same global ground node in ngspice/hspice/xa. Otherwise, this source may be needed.\n")
-        self.sf.write("*V{0} {0} {1} {2}\n".format(self.gnd_name, gnd_node_name, 0.0))
+        if OPTS.spice_name in ["Xyce", "xyce"]:
+            self.sf.write("V{0} {0} {1} {2}\n".format(self.gnd_name, gnd_node_name, 0.0))
+        else:
+            self.sf.write("*V{0} {0} {1} {2}\n".format(self.gnd_name, gnd_node_name, 0.0))
 
     def run_sim(self, name):
         """ Run hspice in batch mode and output rawfile to parse. """
@@ -349,6 +359,19 @@ class stimuli():
                                                            temp_stim,
                                                            OPTS.openram_temp)
             valid_retcode=0
+        elif OPTS.spice_name in ["Xyce", "xyce"]:
+            if OPTS.num_sim_threads > 1 and OPTS.mpi_name:
+                mpi_cmd = "{0} -np {1}".format(OPTS.mpi_exe,
+                                               OPTS.num_sim_threads)
+            else:
+                mpi_cmd = ""
+
+            cmd = "{0} {1} -o {3}timing.lis {2}".format(mpi_cmd,
+                                                        OPTS.spice_exe,
+                                                        temp_stim,
+                                                        OPTS.openram_temp)
+
+            valid_retcode=0
         else:
             # ngspice 27+ supports threading with "set num_threads=4" in the stimulus file or a .spiceinit
             # Measurements can't be made with a raw file set in ngspice

compiler/example_configs/sky130_sram_1kbyte_1r1w_8x1024_8.py

@@ -8,7 +8,7 @@ num_words = 1024
 human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8)
 
 # Allow byte writes
-write_size = 8 # Bits
+#write_size = 8 # Bits
 
 # Dual port
 num_rw_ports = 0

compiler/example_configs/sky130_sram_common.py

@@ -9,7 +9,8 @@ nominal_corner_only = True
 # Local wordlines have issues with met3 power routing for now
 #local_array_size = 16
 
-#route_supplies = False
+route_supplies = "ring"
+#route_supplies = "left"
 check_lvsdrc = True
 #perimeter_pins = False
 #netlist_only = True

compiler/globals.py

@@ -66,7 +66,7 @@ def parse_args():
         optparse.make_option("-m", "--sim_threads",
                              action="store",
                              type="int",
-                             help="Specify the number of spice simulation threads (default: 2)",
+                             help="Specify the number of spice simulation threads (default: 3)",
                              dest="num_sim_threads"),
         optparse.make_option("-v",
                              "--verbose",
@@ -607,14 +607,14 @@ def report_status():
 
     # If a write mask is specified by the user, the mask write size should be the same as
     # the word size so that an entire word is written at once.
-    if OPTS.write_size is not None:
+    if OPTS.write_size is not None and OPTS.write_size != OPTS.word_size:
         if (OPTS.word_size % OPTS.write_size != 0):
             debug.error("Write size needs to be an integer multiple of word size.")
         # If write size is more than half of the word size,
         # then it doesn't need a write mask. It would be writing
         # the whole word.
-        if (OPTS.write_size < 1 or OPTS.write_size > OPTS.word_size/2):
-            debug.error("Write size needs to be between 1 bit and {0} bits/2.".format(OPTS.word_size))
+        if (OPTS.write_size < 1 or OPTS.write_size > OPTS.word_size / 2):
+            debug.error("Write size needs to be between 1 bit and {0} bits.".format(int(OPTS.word_size / 2)))
 
     if not OPTS.tech_name:
         debug.error("Tech name must be specified in config file.")

compiler/model_configs/sram_128b_1024_1rw.py

@@ -0,0 +1,7 @@
+word_size = 128
+num_words = 1024
+
+output_extended_config = True
+output_datasheet_info = True
+netlist_only = True
+nominal_corner_only = True

compiler/model_configs/sram_32b_1024_1rw.py

@@ -0,0 +1,7 @@
+word_size = 32
+num_words = 1024
+
+output_extended_config = True
+output_datasheet_info = True
+netlist_only = True
+nominal_corner_only = True

compiler/model_configs/sram_32b_2048_1rw.py

@@ -0,0 +1,7 @@
+word_size = 32
+num_words = 2048
+
+output_extended_config = True
+output_datasheet_info = True
+netlist_only = True
+nominal_corner_only = True

compiler/model_configs/sram_32b_256_1rw.py

@@ -0,0 +1,7 @@
+word_size = 32
+num_words = 256
+
+output_extended_config = True
+output_datasheet_info = True
+netlist_only = True
+nominal_corner_only = True

compiler/model_configs/sram_32b_512_1rw.py

@@ -0,0 +1,7 @@
+word_size = 32
+num_words = 512
+
+output_extended_config = True
+output_datasheet_info = True
+netlist_only = True
+nominal_corner_only = True

compiler/model_configs/sram_64b_1024_1rw.py

@@ -0,0 +1,7 @@
+word_size = 64
+num_words = 1024
+
+output_extended_config = True
+output_datasheet_info = True
+netlist_only = True
+nominal_corner_only = True

compiler/model_configs/sram_64b_512_1rw.py

@@ -0,0 +1,7 @@
+word_size = 64
+num_words = 512
+
+output_extended_config = True
+output_datasheet_info = True
+netlist_only = True
+nominal_corner_only = True

compiler/model_configs/sram_8b_1024_1rw.py

@@ -0,0 +1,7 @@
+word_size = 8
+num_words = 1024
+
+output_extended_config = True
+output_datasheet_info = True
+netlist_only = True
+nominal_corner_only = True

compiler/model_configs/sram_8b_256_1rw.py

@@ -0,0 +1,7 @@
+word_size = 8
+num_words = 256
+
+output_extended_config = True
+output_datasheet_info = True
+netlist_only = True
+nominal_corner_only = True

compiler/model_configs/sram_8b_512_1rw.py

@@ -0,0 +1,7 @@
+word_size = 8
+num_words = 512
+
+output_extended_config = True
+output_datasheet_info = True
+netlist_only = True
+nominal_corner_only = True

compiler/model_data_util.py

@@ -0,0 +1,283 @@
+import os
+import csv
+import re
+import sys
+import csv
+import importlib
+
+# Use the HTML file to extra the data. Easier to do than LIB
+data_file_ext = ".html"
+extended_name = "_extended" # Name addon of extended config file
+DEFAULT_LAS = 0
+
+def gen_regex_float_group(num, separator):
+    if num <= 0:
+        return ''
+    float_regex = '([-+]?[0-9]*\.?[0-9]*)'
+    full_regex = float_regex
+    for i in range(num-1):
+        full_regex+=separator+float_regex
+    return full_regex
+    
+def import_module(mod_name, mod_path):
+    spec = importlib.util.spec_from_file_location(mod_name, mod_path)
+    mod = importlib.util.module_from_spec(spec)
+    spec.loader.exec_module(mod)
+    return mod
+    
+def get_config_mods(openram_dir):
+    # Get dataset name used by all the files e.g. sram_1b_16
+    files_names = [name for name in os.listdir(openram_dir) if os.path.isfile(openram_dir+'/'+name)]
+    log = [name for name in files_names if '.log' in name][0]
+    dataset_name = log[:-4]
+    print("Extracting dataset:{}".format(dataset_name))
+     
+    # Check that the config files exist (including special extended config) 
+    dir_path = openram_dir+"/"
+    #sys.path.append(dir_path)
+    imp_mod = None
+    imp_mod_extended = None
+    if not os.path.exists(openram_dir+'/'+dataset_name+".py"):
+        print("Python module for {} not found. Returning...".format(dataset_name))
+    else:
+        imp_mod = import_module(dataset_name, openram_dir+"/"+dataset_name+".py")
+        
+    if not os.path.exists(openram_dir+'/'+dataset_name+extended_name+".py"):
+        print("Python module for {} not found. Returning...".format(dataset_name))
+    else:
+        imp_mod_extended = import_module(dataset_name+extended_name, openram_dir+"/"+dataset_name+extended_name+".py")
+    
+    datasheet_fname = openram_dir+"/"+dataset_name+data_file_ext
+    
+    return dataset_name, imp_mod, imp_mod_extended, datasheet_fname  
+
+def get_corners(datafile_contents, dataset_name, tech):
+    """Search through given datasheet to find all corners available"""
+
+    corner_regex = r"{}.*{},([-+]?[0-9]*\.?[0-9]*),([-+]?[0-9]*\.?[0-9]*),([tsfTSF][tsfTSF]),".format(dataset_name, tech)
+    corners = re.findall(corner_regex,datafile_contents)
+    return corners # List of corner tuples in order (T, V, P)
+ 
+feature_names = ['num_words', 
+                 'word_size', 
+                 'words_per_row',
+                 'local_array_size',
+                 'area', 
+                 'process', 
+                 'voltage', 
+                 'temperature',
+                 'slew',
+                 'load']
+output_names =  ['rise_delay', 
+                 'fall_delay',
+                 'rise_slew',
+                 'fall_slew',
+                 'write1_power',
+                 'write0_power',
+                 'read1_power',
+                 'read0_power',
+                 'leakage_power'] 
+                 
+multivalue_names = ['cell_rise_0', 
+                    'cell_fall_0',
+                    'rise_transition_0',
+                    'fall_transition_0']
+singlevalue_names = ['write_rise_power_0',
+                    'write_fall_power_0',
+                    'read_rise_power_0',
+                    'read_fall_power_0']                  
+ 
+def write_to_csv(dataset_name, csv_file, datasheet_fname, imp_mod, imp_mod_extended, mode):    
+
+    
+    writer = csv.writer(csv_file)
+    # If the file was opened to write and not append then we write the header
+    if mode == 'w':
+        writer.writerow(feature_names+output_names)
+
+    try:
+        load_slews = imp_mod.use_specified_load_slew
+    except:
+        load_slews = None
+        
+    if load_slews != None:
+        num_items = len(load_slews)
+        num_loads_or_slews = len(load_slews)
+    else:
+        # These are the defaults for openram
+        num_items = 9
+        num_loads_or_slews = 3
+      
+    try:
+        f = open(datasheet_fname, "r")
+    except IOError:
+        print("Unable to open spice output file: {0}".format(datasheet_fname))
+        return None
+    print("Opened file",datasheet_fname)
+    contents = f.read()
+    f.close()                    
+                  
+    available_corners = get_corners(contents, dataset_name, imp_mod_extended.tech_name)
+                  
+    # Loop through corners, adding data for each corner    
+    for (temp, voltage, process) in available_corners:    
+        
+        # Create a regex to search the datasheet for specified outputs
+        voltage_str = "".join(['\\'+i if i=='.' else i for i in str(voltage)])
+        area_regex = r"Area \(&microm<sup>2<\/sup>\)<\/td><td>(\d+)"
+
+        leakage_regex = r"leakage<\/td><td>([-+]?[0-9]*\.?[0-9]*)"
+        slew_regex = r"rise transition<\/td><td>([-+]?[0-9]*\.?[0-9]*)"
+
+        if load_slews == None:
+            float_regex = gen_regex_float_group(num_loads_or_slews, ', ')
+            inp_slews_regex = r"{},{}.*{},{},{},.*slews,\[{}".format(
+                dataset_name,
+                imp_mod.num_words,
+                str(temp),
+                voltage_str,
+                process,
+                float_regex)
+            
+            loads_regex = r"{},{}.*{},{},{},.*loads,\[{}".format(
+                dataset_name,
+                imp_mod.num_words,
+                str(temp),
+                voltage_str,
+                process,
+                float_regex)    
+
+        float_regex = gen_regex_float_group(num_items, ', ')
+        multivalue_regexs = []
+        for value_identifier in multivalue_names:
+            regex_str = r"{},{}.*{},{},{},.*{},\[{}".format(
+                dataset_name,
+                imp_mod.num_words,
+                str(temp),
+                voltage_str,
+                process,
+                value_identifier,
+                float_regex)    
+            multivalue_regexs.append(regex_str) 
+            
+        singlevalue_regexs = []        
+        for value_identifier in singlevalue_names:
+            regex_str = r"{},{}.*{},{},{},.*{},([-+]?[0-9]*\.?[0-9]*)".format(
+                dataset_name,
+                imp_mod.num_words,
+                str(temp),
+                voltage_str,
+                process,
+                value_identifier,
+                float_regex)        
+            singlevalue_regexs.append(regex_str)     
+ 
+        area_vals = re.search(area_regex,contents)
+        leakage_vals = re.search(leakage_regex,contents)
+        if load_slews == None:
+            inp_slew_vals = re.search(inp_slews_regex,contents)
+            load_vals = re.search(loads_regex,contents)
+            
+        datasheet_multivalues = [re.search(r,contents) for r in multivalue_regexs]
+        datasheet_singlevalues = [re.search(r,contents) for r in singlevalue_regexs]
+        for dval in datasheet_multivalues+datasheet_singlevalues:
+            if dval == None:
+                print("Error occurred while searching through datasheet: {}".format(datasheet_fname))
+                return None
+
+        try:
+            las = imp_mod.local_array_size
+        except:
+            las = DEFAULT_LAS
+        
+        # All the extracted values are delays but val[2] is the max delay
+        feature_vals = [imp_mod.num_words, 
+                        imp_mod.word_size,
+                        imp_mod_extended.words_per_row,
+                        las,
+                        area_vals[1], 
+                        process, 
+                        voltage, 
+                        temp]
+                        
+        if load_slews == None:
+            c = 1                
+            for i in range(num_loads_or_slews):
+                for j in range(num_loads_or_slews):
+                    multi_values = [val[i+j+c] for val in datasheet_multivalues]
+                    single_values = [val[1] for val in datasheet_singlevalues]
+                    writer.writerow(feature_vals+[inp_slew_vals[i+1], load_vals[j+1]]+multi_values+single_values+[leakage_vals[1]])        
+                c+=2
+        else:
+            # if num loads and num slews are not equal then this might break because of how OpenRAM formats
+            # the outputs
+            c = 1
+            for load,slew in load_slews:
+                multi_values = [val[c] for val in datasheet_multivalues]
+                single_values = [val[1] for val in datasheet_singlevalues]
+                writer.writerow(feature_vals+[slew, load]+multi_values+single_values+[leakage_vals[1]])      
+                c+=1
+
+
+def extract_data(openram_dir, out_dir, is_first):
+    """Given an OpenRAM output dir, searches through datasheet files and ouputs
+       a CSV files with data used in model."""
+
+    # Get dataset name used by all the files e.g. sram_1b_16
+    dataset_name, inp_mod, imp_mod_extended, datasheet_fname = get_config_mods(openram_dir)
+
+    if is_first:
+        mode = 'w'
+    else:
+        mode = 'a+'
+    data_file = open("{}/sim_data.csv".format(out_dir), mode, newline='')
+    write_to_csv(dataset_name, data_file, datasheet_fname, inp_mod, imp_mod_extended, mode)
+
+    return out_dir
+    
+def gen_model_csv(openram_dir_path, out_dir):
+    if not os.path.isdir(input_dir_path):
+        print("Path does not exist: {}".format(input_dir_path))
+        return
+        
+    if not os.path.isdir(out_path):
+        print("Path does not exist: {}".format(out_path))
+        return   
+        
+    is_first = True
+    oram_dirs = [openram_dir_path+'/'+name for name in os.listdir(openram_dir_path) if os.path.isdir(openram_dir_path+'/'+name)]
+    for dir in oram_dirs:
+        extract_data(dir, out_dir, is_first)
+        is_first = False
+        
+if __name__ == "__main__":
+    if len(sys.argv) < 3:
+        print("Usage: python model_data_util.py path_to_openram_dirs out_dir_path")
+    else:
+        input_dir_path = sys.argv[1]   
+        out_path = sys.argv[2] 
+        gen_model_csv(input_dir_path, out_path) 
+
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    

compiler/modules/bank.py

@@ -1089,7 +1089,7 @@ class bank(design.design):
         """
         Gets the spice name of the target bitcell.
         """
-        return self.bitcell_array_inst.mod.get_cell_name(inst_name + '.x' + self.bitcell_array_inst.name,
+        return self.bitcell_array_inst.mod.get_cell_name(inst_name + "{}x".format(OPTS.hier_seperator) + self.bitcell_array_inst.name,
                                                          row,
                                                          col)
 

compiler/modules/bitcell_array.py

@@ -121,4 +121,4 @@ class bitcell_array(bitcell_base_array):
 
     def get_cell_name(self, inst_name, row, col):
         """Gets the spice name of the target bitcell."""
-        return inst_name + '.x' + self.cell_inst[row, col].name, self.cell_inst[row, col]
+        return inst_name + "{}x".format(OPTS.hier_seperator) + self.cell_inst[row, col].name, self.cell_inst[row, col]

compiler/modules/global_bitcell_array.py

@@ -330,7 +330,7 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
         # We must also translate the global array column number to the local array column number
         local_col = col - self.col_offsets[i - 1]
 
-        return local_array.get_cell_name(inst_name + '.x' + local_inst.name, row, local_col)
+        return local_array.get_cell_name(inst_name + "{}x".format(OPTS.hier_seperator) + local_inst.name, row, local_col)
 
     def clear_exclude_bits(self):
         """

compiler/modules/local_bitcell_array.py

@@ -295,7 +295,7 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
 
     def get_cell_name(self, inst_name, row, col):
         """Gets the spice name of the target bitcell."""
-        return self.bitcell_array.get_cell_name(inst_name + '.x' + self.bitcell_array_inst.name, row, col)
+        return self.bitcell_array.get_cell_name(inst_name + "{}x".format(OPTS.hier_seperator) + self.bitcell_array_inst.name, row, col)
 
     def clear_exclude_bits(self):
         """

compiler/modules/orig_bitcell_array.py

@@ -114,4 +114,4 @@ class bitcell_array(bitcell_base_array):
 
     def get_cell_name(self, inst_name, row, col):
         """Gets the spice name of the target bitcell."""
-        return inst_name + '.x' + self.cell_inst[row, col].name, self.cell_inst[row, col]
+        return inst_name + "{}x".format(OPTS.hier_seperator) + self.cell_inst[row, col].name, self.cell_inst[row, col]

compiler/modules/replica_bitcell_array.py

@@ -553,7 +553,7 @@ class replica_bitcell_array(bitcell_base_array):
         """
         Gets the spice name of the target bitcell.
         """
-        return self.bitcell_array.get_cell_name(inst_name + '.x' + self.bitcell_array_inst.name, row, col)
+        return self.bitcell_array.get_cell_name(inst_name + "{}x".format(OPTS.hier_seperator) + self.bitcell_array_inst.name, row, col)
 
     def clear_exclude_bits(self):
         """

compiler/options.py

@@ -6,9 +6,9 @@
 # All rights reserved.
 #
 import optparse
-import getpass
 import os
 
+
 class options(optparse.Values):
     """
     Class for holding all of the OpenRAM options. All
@@ -89,6 +89,8 @@ class options(optparse.Values):
     use_specified_corners = None
     # Allows specification of model data
     sim_data_path = None
+    # A list of load/slew tuples
+    use_specified_load_slew = None
 
     ###################
     # Run-time vs accuracy options.
@@ -99,6 +101,7 @@ class options(optparse.Values):
     netlist_only = False
     # Whether we should do the final power routing
     route_supplies = "tree"
+    supply_pin_type = "ring"
     # This determines whether LVS and DRC is checked at all.
     check_lvsdrc = False
     # This determines whether LVS and DRC is checked for every submodule.
@@ -137,8 +140,11 @@ class options(optparse.Values):
     # Number of threads to use
     num_threads = 1
     # Number of threads to use in ngspice/hspice
-    num_sim_threads = 2
+    num_sim_threads = 3
 
+    # Some tools (e.g. Xyce) use other separators like ":"
+    hier_seperator = "."
+    
     # Should we print out the banner at startup
     print_banner = True
 

compiler/router/grid.py

@@ -37,6 +37,8 @@ class grid:
         # This is really lower left bottom layer and upper right top layer in 3D.
         self.ll = vector3d(ll.x, ll.y, 0).scale(self.track_factor).round()
         self.ur = vector3d(ur.x, ur.y, 0).scale(self.track_factor).round()
+        debug.info(1, "BBOX coords: ll=" + str(ll) + " ur=" + str(ur))
+        debug.info(1, "BBOX grids: ll=" + str(self.ll) + " ur=" + str(self.ur))
 
         # let's leave the map sparse, cells are created on demand to reduce memory
         self.map={}
@@ -127,33 +129,47 @@ class grid:
         Side specifies which side.
         Layer specifies horizontal (0) or vertical (1)
         Width specifies how wide the perimter "stripe" should be.
+        Works from the inside out from the bbox (ll, ur)
         """
+        if "ring" in side:
+            ring_width = width
+        else:
+            ring_width = 0
+
+        if "ring" in side:
+            ring_offset = offset
+        else:
+            ring_offset = 0
+
         perimeter_list = []
         # Add the left/right columns
-        if side=="all" or side=="left":
-            for x in range(self.ll.x + offset, self.ll.x + width + offset, 1):
-                for y in range(self.ll.y + margin, self.ur.y - margin, 1):
+        if side=="all" or "left" in side:
+            for x in range(self.ll.x - offset, self.ll.x - width - offset, -1):
+                for y in range(self.ll.y - ring_offset - margin - ring_width + 1, self.ur.y + ring_offset + margin + ring_width, 1):
                     for layer in layers:
                         perimeter_list.append(vector3d(x, y, layer))
                 
-        if side=="all" or side=="right":
-            for x in range(self.ur.x - width - offset, self.ur.x - offset, 1):
-                for y in range(self.ll.y + margin, self.ur.y - margin, 1):
+        if side=="all" or "right" in side:
+            for x in range(self.ur.x + offset, self.ur.x + width + offset, 1):
+                for y in range(self.ll.y - ring_offset - margin - ring_width + 1, self.ur.y + ring_offset + margin + ring_width, 1):
                     for layer in layers:
                         perimeter_list.append(vector3d(x, y, layer))
 
-        if side=="all" or side=="bottom":
-            for y in range(self.ll.y + offset, self.ll.y + width + offset, 1):
-                for x in range(self.ll.x + margin, self.ur.x - margin, 1):
+        if side=="all" or "bottom" in side:
+            for y in range(self.ll.y - offset, self.ll.y - width - offset, -1):
+                for x in range(self.ll.x - ring_offset - margin - ring_width + 1, self.ur.x + ring_offset + margin + ring_width, 1):
                     for layer in layers:
                         perimeter_list.append(vector3d(x, y, layer))
 
-        if side=="all" or side=="top":
-            for y in range(self.ur.y - width - offset, self.ur.y - offset, 1):
-                for x in range(self.ll.x + margin, self.ur.x - margin, 1):
+        if side=="all" or "top" in side:
+            for y in range(self.ur.y + offset, self.ur.y + width + offset, 1):
+                for x in range(self.ll.x - ring_offset - margin - ring_width + 1, self.ur.x + ring_offset + margin + ring_width, 1):
                     for layer in layers:
                         perimeter_list.append(vector3d(x, y, layer))
 
+        # Add them all to the map
+        self.add_map(perimeter_list)
+
         return perimeter_list
     
     def add_perimeter_target(self, side="all", layers=[0, 1]):

compiler/router/router.py

@@ -75,35 +75,20 @@ class router(router_tech):
         self.margin = margin
         self.init_bbox(bbox, margin)
 
+        # New pins if we create a ring or side pins or etc.
+        self.new_pins = {}
+
     def init_bbox(self, bbox=None, margin=0):
         """
         Initialize the ll,ur values with the paramter or using the layout boundary.
         """
-
-        # If didn't specify a gds blockage file, write it out to read the gds
-        # This isn't efficient, but easy for now
-        # Load the gds file and read in all the shapes
-        self.cell.gds_write(self.gds_filename)
-        self.layout = gdsMill.VlsiLayout(units=GDS["unit"])
-        self.reader = gdsMill.Gds2reader(self.layout)
-        self.reader.loadFromFile(self.gds_filename)
-        self.top_name = self.layout.rootStructureName
-        
         if not bbox:
-            # The boundary will determine the limits to the size
-            # of the routing grid
-            self.boundary = self.layout.measureBoundary(self.top_name)
-            # These must be un-indexed to get rid of the matrix type
-            self.ll = vector(self.boundary[0][0], self.boundary[0][1])
-            self.ur = vector(self.boundary[1][0], self.boundary[1][1])
+            self.bbox = self.cell.get_bbox(margin)
         else:
-            self.ll, self.ur = bbox
+            self.bbox = bbox
+
+        (self.ll, self.ur) = self.bbox
 
-        margin_offset = vector(margin, margin)
-        self.bbox = (self.ll - margin_offset, self.ur + margin_offset)
-        size = self.ur - self.ll
-        debug.info(1, "Size: {0} x {1} with perimeter margin {2}".format(size.x, size.y, margin))
-        
     def get_bbox(self):
         return self.bbox
     
@@ -890,25 +875,96 @@ class router(router_tech):
         # Clearing the blockage of this pin requires the inflated pins
         self.clear_blockages(pin_name)
 
-    def add_side_supply_pin(self, name, side="left", width=2):
+    def add_side_supply_pin(self, name, side="left", width=3, space=2):
         """
         Adds a supply pin to the perimeter and resizes the bounding box.
         """
         pg = pin_group(name, [], self)
+        # Offset two spaces inside and one between the rings
         if name == "vdd":
-            offset = width
+            offset = width + 2 * space
         else:
-            offset = 0
-        
+            offset = space
+        if side in ["left", "right"]:
+            layers = [1]
+        else:
+            layers = [0]
+
         pg.grids = set(self.rg.get_perimeter_list(side=side,
                                                   width=width,
                                                   margin=self.margin,
                                                   offset=offset,
-                                                  layers=[1]))
+                                                  layers=layers))
         pg.enclosures = pg.compute_enclosures()
         pg.pins = set(pg.enclosures)
+        debug.check(len(pg.pins)==1, "Too many pins for a side supply.")
+
         self.cell.pin_map[name].update(pg.pins)
         self.pin_groups[name].append(pg)
+
+        self.new_pins[name] = pg.pins
+        
+    def add_ring_supply_pin(self, name, width=3, space=2):
+        """
+        Adds a ring supply pin that goes inside the given bbox.
+        """
+        pg = pin_group(name, [], self)
+        # Offset two spaces inside and one between the rings
+        # Units are in routing grids
+        if name == "vdd":
+            offset = width + 2 * space
+        else:
+            offset = space
+
+        # LEFT
+        left_grids = set(self.rg.get_perimeter_list(side="left_ring",
+                                                    width=width,
+                                                    margin=self.margin,
+                                                    offset=offset,
+                                                    layers=[1]))
+
+        # RIGHT
+        right_grids = set(self.rg.get_perimeter_list(side="right_ring",
+                                                     width=width,
+                                                     margin=self.margin,
+                                                     offset=offset,
+                                                     layers=[1]))
+        # TOP
+        top_grids = set(self.rg.get_perimeter_list(side="top_ring",
+                                                   width=width,
+                                                   margin=self.margin,
+                                                   offset=offset,
+                                                   layers=[0]))
+        # BOTTOM
+        bottom_grids = set(self.rg.get_perimeter_list(side="bottom_ring",
+                                                      width=width,
+                                                      margin=self.margin,
+                                                      offset=offset,
+                                                      layers=[0]))
+
+        horizontal_layer_grids = left_grids | right_grids
+        
+        # Must move to the same layer to find layer 1 corner grids
+        vertical_layer_grids = set()
+        for x in top_grids | bottom_grids:
+            vertical_layer_grids.add(vector3d(x.x, x.y, 1))
+
+        # Add vias in the overlap points
+        horizontal_corner_grids = vertical_layer_grids & horizontal_layer_grids
+        for g in horizontal_corner_grids:
+            self.add_via(g)
+
+        # The big pin group, but exclude the corners from the pins
+        pg.grids = (left_grids | right_grids | top_grids | bottom_grids)
+        pg.enclosures = pg.compute_enclosures()
+        pg.pins = set(pg.enclosures)
+        
+        self.cell.pin_map[name].update(pg.pins)
+        self.pin_groups[name].append(pg)
+        self.new_pins[name] = pg.pins
+
+    def get_new_pins(self, name):
+        return self.new_pins[name]
         
     def add_perimeter_target(self, side="all"):
         """

compiler/router/supply_grid_router.py

@@ -21,7 +21,7 @@ class supply_grid_router(router):
     routes a grid to connect the supply on the two layers.
     """
 
-    def __init__(self, layers, design, margin=0, bbox=None):
+    def __init__(self, layers, design, bbox=None, pin_type=None):
         """
         This will route on layers in design. It will get the blockages from
         either the gds file name or the design itself (by saving to a gds file).

compiler/router/supply_tree_router.py

@@ -21,7 +21,7 @@ class supply_tree_router(router):
     routes a grid to connect the supply on the two layers.
     """
 
-    def __init__(self, layers, design, bbox=None, side_pin=None):
+    def __init__(self, layers, design, bbox=None, pin_type=None):
         """
         This will route on layers in design. It will get the blockages from
         either the gds file name or the design itself (by saving to a gds file).
@@ -33,7 +33,10 @@ class supply_tree_router(router):
 
         # The pin escape router already made the bounding box big enough,
         # so we can use the regular bbox here.
-        self.side_pin = side_pin
+        if pin_type:
+            debug.check(pin_type in ["left", "right", "top", "bottom", "single", "ring"],
+                        "Invalid pin type {}".format(pin_type))
+        self.pin_type = pin_type
         router.__init__(self,
                         layers,
                         design,
@@ -65,10 +68,13 @@ class supply_tree_router(router):
         print_time("Finding pins and blockages", datetime.now(), start_time, 3)
 
         # Add side pins if enabled
-        if self.side_pin:
-            self.add_side_supply_pin(self.vdd_name)
-            self.add_side_supply_pin(self.gnd_name)
-        
+        if self.pin_type in ["left", "right", "top", "bottom"]:
+            self.add_side_supply_pin(self.vdd_name, side=self.pin_type)
+            self.add_side_supply_pin(self.gnd_name, side=self.pin_type)
+        elif self.pin_type == "ring":
+            self.add_ring_supply_pin(self.vdd_name)
+            self.add_ring_supply_pin(self.gnd_name)
+
         # Route the supply pins to the supply rails
         # Route vdd first since we want it to be shorter
         start_time = datetime.now()

compiler/router/vector3d.py

@@ -5,9 +5,9 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
 import math
 
+
 class vector3d():
     """
     This is the vector3d class to represent a 3D coordinate.
@@ -22,20 +22,20 @@ class vector3d():
             self.x = x[0]
             self.y = x[1]
             self.z = x[2]
-        #will take inputs as the values of a coordinate
+        # will take inputs as the values of a coordinate
         else:
             self.x = x
             self.y = y
             self.z = z
-        self._hash = hash((self.x,self.y,self.z))
+        self._hash = hash((self.x, self.y, self.z))
 
     def __str__(self):
         """ override print function output """
-        return "v3d["+str(self.x)+", "+str(self.y)+", "+str(self.z)+"]"
+        return "v3d[" + str(self.x) + ", " + str(self.y) + ", " + str(self.z) + "]"
 
     def __repr__(self):
         """ override print function output """
-        return "v3d["+str(self.x)+", "+str(self.y)+", "+str(self.z)+"]"
+        return "v3d[" + str(self.x) + ", " + str(self.y) + ", " + str(self.z) + "]"
 
     def __setitem__(self, index, value):
         """
@@ -74,7 +74,6 @@ class vector3d():
         """
         return vector3d(self.x + other[0], self.y + other[1], self.z + other[2])
 
-
     def __radd__(self, other):
         """
         Override + function (right add)
@@ -98,7 +97,6 @@ class vector3d():
         """
         return self._hash
 
-
     def __rsub__(self, other):
         """
         Override - function (right)
@@ -107,7 +105,7 @@ class vector3d():
 
     def rotate(self):
         """ pass a copy of rotated vector3d, without altering the vector3d! """
-        return vector3d(self.y,self.x,self.z)
+        return vector3d(self.y, self.x, self.z)
 
     def scale(self, x_factor, y_factor=None,z_factor=None):
         """ pass a copy of scaled vector3d, without altering the vector3d! """
@@ -115,7 +113,7 @@ class vector3d():
             z_factor=x_factor[2]
             y_factor=x_factor[1]
             x_factor=x_factor[0]
-        return vector3d(self.x*x_factor,self.y*y_factor,self.z*z_factor)
+        return vector3d(self.x * x_factor, self.y * y_factor, self.z * z_factor)
 
     def rotate_scale(self, x_factor, y_factor=None, z_factor=None):
         """ pass a copy of scaled vector3d, without altering the vector3d! """
@@ -123,25 +121,25 @@ class vector3d():
             z_factor=x_factor[2]
             y_factor=x_factor[1]
             x_factor=x_factor[0]
-        return vector3d(self.y*x_factor,self.x*y_factor,self.z*z_factor)
+        return vector3d(self.y * x_factor, self.x * y_factor, self.z * z_factor)
 
     def floor(self):
         """
         Override floor function
         """
-        return vector3d(int(math.floor(self.x)),int(math.floor(self.y)), self.z)
+        return vector3d(int(math.floor(self.x)), int(math.floor(self.y)), self.z)
 
     def ceil(self):
         """
         Override ceil function
         """
-        return vector3d(int(math.ceil(self.x)),int(math.ceil(self.y)), self.z)
+        return vector3d(int(math.ceil(self.x)), int(math.ceil(self.y)), self.z)
 
     def round(self):
         """
         Override round function
         """
-        return vector3d(int(round(self.x)),int(round(self.y)), self.z)
+        return vector3d(int(round(self.x)), int(round(self.y)), self.z)
 
     def __eq__(self, other):
         """Override the default Equals behavior"""
@@ -164,30 +162,29 @@ class vector3d():
 
     def max(self, other):
         """ Max of both values """
-        return vector3d(max(self.x,other.x),max(self.y,other.y),max(self.z,other.z))
+        return vector3d(max(self.x, other.x), max(self.y, other.y), max(self.z, other.z))
 
     def min(self, other):
         """ Min of both values """
-        return vector3d(min(self.x,other.x),min(self.y,other.y),min(self.z,other.z))
+        return vector3d(min(self.x, other.x), min(self.y, other.y), min(self.z, other.z))
 
     def distance(self, other):
         """ Return the manhattan distance between two values """
-        return abs(self.x-other.x)+abs(self.y-other.y)
+        return abs(self.x - other.x) + abs(self.y - other.y)
 
     def euclidean_distance(self, other):
         """ Return the euclidean distance between two values """
-        return math.sqrt((self.x-other.x)**2+(self.y-other.y)**2)
-
+        return math.sqrt((self.x - other.x)**2 + (self.y - other.y)**2)
 
     def adjacent(self, other):
         """ Is the one grid adjacent in any planar direction to the other """
-        if self == other + vector3d(1,0,0):
+        if self == other + vector3d(1, 0, 0):
             return True
-        elif self == other + vector3d(-1,0,0):
+        elif self == other + vector3d(-1, 0, 0):
             return True
-        elif self == other + vector3d(0,1,0):
+        elif self == other + vector3d(0, 1, 0):
             return True
-        elif self == other + vector3d(0,-1,0):
+        elif self == other + vector3d(0, -1, 0):
             return True
         else:
             return False

compiler/sram/sram.py

@@ -24,12 +24,6 @@ class sram():
 
         sram_config.set_local_config(self)
                 
-        # FIXME: adjust this to not directly change OPTS.
-        # Word-around to have values relevant to OPTS be displayed if not directly set.
-        OPTS.words_per_row = self.words_per_row
-        debug.info(1, "Changed OPTS wpr={}".format(self.words_per_row))
-        debug.info(1, "OPTS wpr={}".format(OPTS.words_per_row))
-        
         # reset the static duplicate name checker for unit tests
         # in case we create more than one SRAM
         from design import design

compiler/sram/sram_1bank.py

@@ -9,6 +9,7 @@ from vector import vector
 from sram_base import sram_base
 from contact import m2_via
 from channel_route import channel_route
+from router_tech import router_tech
 from globals import OPTS
 
 
@@ -326,13 +327,34 @@ class sram_1bank(sram_base):
         # they might create some blockages
         self.add_layout_pins()
 
+        # Some technologies have an isolation
+        self.add_dnwell(inflate=2)
+
+        # We need the initial bbox for the supply rings later
+        # because the perimeter pins will change the bbox
         # Route the pins to the perimeter
+        pre_bbox = None
         if OPTS.perimeter_pins:
-            self.route_escape_pins()
+            rt = router_tech(self.supply_stack, 1)
+
+            if OPTS.supply_pin_type in ["ring", "left", "right", "top", "bottom"]:
+                big_margin = 12 * rt.track_width
+                little_margin = 2 * rt.track_width
+            else:
+                big_margin = 6 * rt.track_width
+                little_margin = 0
+
+            pre_bbox = self.get_bbox(side="ring",
+                                     big_margin=rt.track_width)
+
+            bbox = self.get_bbox(side=OPTS.supply_pin_type,
+                                 big_margin=big_margin,
+                                 little_margin=little_margin)
+            self.route_escape_pins(bbox)
             
         # Route the supplies first since the MST is not blockage aware
         # and signals can route to anywhere on sides (it is flexible)
-        self.route_supplies()
+        self.route_supplies(pre_bbox)
         
     def route_dffs(self, add_routes=True):
 
@@ -613,7 +635,7 @@ class sram_1bank(sram_base):
         # Sanity check in case it was forgotten
         if inst_name.find("x") != 0:
             inst_name = "x" + inst_name
-        return self.bank_inst.mod.get_cell_name(inst_name + ".x" + self.bank_inst.name, row, col)
+        return self.bank_inst.mod.get_cell_name(inst_name + "{}x".format(OPTS.hier_seperator) + self.bank_inst.name, row, col)
 
     def get_bank_num(self, inst_name, row, col):
         return 0

compiler/sram/sram_base.py

@@ -15,6 +15,7 @@ from design import design
 from verilog import verilog
 from lef import lef
 from sram_factory import factory
+from tech import spice, layer
 
 
 class sram_base(design, verilog, lef):
@@ -40,7 +41,15 @@ class sram_base(design, verilog, lef):
         if not self.num_spare_cols:
             self.num_spare_cols = 0
 
-    def add_pins(self): 
+        try:
+            from tech import power_grid
+            self.supply_stack = power_grid
+        except ImportError:
+            # if no power_grid is specified by tech we use sensible defaults
+            # Route a M3/M4 grid
+            self.supply_stack = self.m3_stack
+
+    def add_pins(self):
         """ Add pins for entire SRAM. """
 
         for port in self.write_ports:
@@ -81,8 +90,20 @@ class sram_base(design, verilog, lef):
             for bit in range(self.word_size + self.num_spare_cols):
                 self.add_pin("dout{0}[{1}]".format(port, bit), "OUTPUT")
 
-        self.add_pin("vdd", "POWER")
-        self.add_pin("gnd", "GROUND")
+        # Standard supply and ground names
+        try:
+            self.vdd_name = spice["power"]
+        except KeyError:
+            self.vdd_name = "vdd"
+        try:
+            self.gnd_name = spice["ground"]
+        except KeyError:
+            self.gnd_name = "gnd"
+
+        self.add_pin(self.vdd_name, "POWER")
+        self.add_pin(self.gnd_name, "GROUND")
+        self.ext_supplies = [self.vdd_name, self.gnd_name]
+        self.ext_supply = {"vdd" : self.vdd_name, "gnd" : self.gnd_name}
 
     def add_global_pex_labels(self):
         """
@@ -217,47 +238,15 @@ class sram_base(design, verilog, lef):
     def create_modules(self):
         debug.error("Must override pure virtual function.", -1)
 
-    def route_supplies(self):
+    def route_supplies(self, bbox=None):
         """ Route the supply grid and connect the pins to them. """
 
         # Copy the pins to the top level
         # This will either be used to route or left unconnected.
         for pin_name in ["vdd", "gnd"]:
             for inst in self.insts:
-                self.copy_power_pins(inst, pin_name)
+                self.copy_power_pins(inst, pin_name, self.ext_supply[pin_name])
         
-        try:
-            from tech import power_grid
-            grid_stack = power_grid
-        except ImportError:
-            # if no power_grid is specified by tech we use sensible defaults
-            # Route a M3/M4 grid
-            grid_stack = self.m3_stack
-
-        # lowest_coord = self.find_lowest_coords()
-        # highest_coord = self.find_highest_coords()
-            
-        # # Add two rails to the side
-        # if OPTS.route_supplies == "side":
-        #     supply_pins = {}
-        #     # Find the lowest leftest pin for vdd and gnd
-        #     for (pin_name, pin_index) in [("vdd", 0), ("gnd", 1)]:
-        #         pin_width = 8 * getattr(self, "{}_width".format(grid_stack[2]))
-        #         pin_space = 2 * getattr(self, "{}_space".format(grid_stack[2]))
-        #         supply_pitch = pin_width + pin_space
-
-        #         # Add side power rails on left from bottom to top
-        #         # These have a temporary name and will be connected later.
-        #         # They are here to reserve space now and ensure other pins go beyond
-        #         # their perimeter.
-        #         supply_height = highest_coord.y - lowest_coord.y
-                
-        #         supply_pins[pin_name] = self.add_layout_pin(text=pin_name,
-        #                                                     layer=grid_stack[2],
-        #                                                     offset=lowest_coord + vector(pin_index * supply_pitch, 0),
-        #                                                     width=pin_width,
-        #                                                     height=supply_height)
-
         if not OPTS.route_supplies:
             # Do not route the power supply (leave as must-connect pins)
             return
@@ -265,11 +254,14 @@ class sram_base(design, verilog, lef):
             from supply_grid_router import supply_grid_router as router
         else:
             from supply_tree_router import supply_tree_router as router
+        rtr=router(layers=self.supply_stack,
+                   design=self,
+                   bbox=bbox,
+                   pin_type=OPTS.supply_pin_type)
 
-        rtr=router(grid_stack, self, side_pin=(OPTS.route_supplies == "side"))
         rtr.route()
 
-        if OPTS.route_supplies == "side":
+        if OPTS.supply_pin_type in ["left", "right", "top", "bottom", "ring"]:
             # Find the lowest leftest pin for vdd and gnd
             for pin_name in ["vdd", "gnd"]:
                 # Copy the pin shape(s) to rectangles
@@ -282,15 +274,16 @@ class sram_base(design, verilog, lef):
                 # Remove the pin shape(s)
                 self.remove_layout_pin(pin_name)
 
-                # Get the lowest, leftest pin
-                pin = rtr.get_ll_pin(pin_name)
-                self.add_layout_pin(pin_name,
-                                    pin.layer,
-                                    pin.ll(),
-                                    pin.width(),
-                                    pin.height())
+                # Get new pins
+                pins = rtr.get_new_pins(pin_name)
+                for pin in pins:
+                    self.add_layout_pin(self.ext_supply[pin_name],
+                                        pin.layer,
+                                        pin.ll(),
+                                        pin.width(),
+                                        pin.height())
             
-        elif OPTS.route_supplies:
+        elif OPTS.route_supplies and OPTS.supply_pin_type == "single":
             # Update these as we may have routed outside the region (perimeter pins)
             lowest_coord = self.find_lowest_coords()
         
@@ -319,7 +312,7 @@ class sram_base(design, verilog, lef):
                               route_width,
                               pin.height())
 
-                self.add_layout_pin(pin_name,
+                self.add_layout_pin(self.ext_supply[pin_name],
                                     pin.layer,
                                     pin_offset,
                                     pin_width,
@@ -328,7 +321,7 @@ class sram_base(design, verilog, lef):
             # Grid is left with many top level pins
             pass
 
-    def route_escape_pins(self):
+    def route_escape_pins(self, bbox):
         """
         Add the top-level pins for a single bank SRAM with control.
         """
@@ -371,7 +364,7 @@ class sram_base(design, verilog, lef):
         from signal_escape_router import signal_escape_router as router
         rtr=router(layers=self.m3_stack,
                    design=self,
-                   margin=8 * self.m3_pitch)
+                   bbox=bbox)
         rtr.escape_route(pins_to_route)
 
     def compute_bus_sizes(self):
@@ -573,7 +566,7 @@ class sram_base(design, verilog, lef):
                 temp.append("bank_spare_wen{0}[{1}]".format(port, bit))
         for port in self.all_ports:
             temp.append("wl_en{0}".format(port))
-        temp.extend(["vdd", "gnd"])
+        temp.extend(self.ext_supplies)
         self.connect_inst(temp)
 
         return self.bank_insts[-1]
@@ -622,7 +615,7 @@ class sram_base(design, verilog, lef):
                 inputs.append("addr{}[{}]".format(port, bit + self.col_addr_size))
                 outputs.append("a{}[{}]".format(port, bit + self.col_addr_size))
 
-            self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"])
+            self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)
 
         return insts
 
@@ -640,7 +633,7 @@ class sram_base(design, verilog, lef):
                 inputs.append("addr{}[{}]".format(port, bit))
                 outputs.append("a{}[{}]".format(port, bit))
 
-            self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"])
+            self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)
 
         return insts
 
@@ -662,7 +655,7 @@ class sram_base(design, verilog, lef):
                 inputs.append("din{}[{}]".format(port, bit))
                 outputs.append("bank_din{}[{}]".format(port, bit))
 
-            self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"])
+            self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)
 
         return insts
 
@@ -684,7 +677,7 @@ class sram_base(design, verilog, lef):
                 inputs.append("wmask{}[{}]".format(port, bit))
                 outputs.append("bank_wmask{}[{}]".format(port, bit))
 
-            self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"])
+            self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)
 
         return insts
 
@@ -706,7 +699,7 @@ class sram_base(design, verilog, lef):
                 inputs.append("spare_wen{}[{}]".format(port, bit))
                 outputs.append("bank_spare_wen{}[{}]".format(port, bit))
 
-            self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"])
+            self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)
 
         return insts
 
@@ -737,7 +730,7 @@ class sram_base(design, verilog, lef):
             if port in self.write_ports:
                 temp.append("w_en{}".format(port))
             temp.append("p_en_bar{}".format(port))
-            temp.extend(["wl_en{}".format(port), "clk_buf{}".format(port), "vdd", "gnd"])
+            temp.extend(["wl_en{}".format(port), "clk_buf{}".format(port)] + self.ext_supplies)
             self.connect_inst(temp)
 
         return insts

compiler/sram/sram_config.py

@@ -63,6 +63,11 @@ class sram_config:
 
         self.recompute_sizes()
 
+        # Set word_per_row in OPTS 
+        OPTS.words_per_row = self.words_per_row
+        debug.info(1, "Set SRAM Words Per Row={}".format(OPTS.words_per_row))
+
+        
     def recompute_sizes(self):
         """
         Calculate the auxiliary values assuming fixed number of words per row.

compiler/tests/21_hspice_delay_test.py

@@ -50,7 +50,11 @@ class timing_sram_test(openram_test):
         import tech
         loads = [tech.spice["dff_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]
-        data, port_data = d.analyze(probe_address, probe_data, slews, loads)
+        load_slews = []
+        for slew in slews:
+            for load in loads:
+                load_slews.append((load, slew))
+        data, port_data = d.analyze(probe_address, probe_data, load_slews)
         #Combine info about port into all data
         data.update(port_data[0])
 

compiler/tests/21_model_delay_test.py

@@ -55,13 +55,17 @@ class model_delay_test(openram_test):
         import tech
         loads = [tech.spice["dff_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]
+        load_slews = []
+        for slew in slews:
+            for load in loads:
+                load_slews.append((load, slew))
 
         # Run a spice characterization
-        spice_data, port_data = d.analyze(probe_address, probe_data, slews, loads)
+        spice_data, port_data = d.analyze(probe_address, probe_data, load_slews)
         spice_data.update(port_data[0])
 
         # Run analytical characterization
-        model_data, port_data = m.get_lib_values(slews, loads)
+        model_data, port_data = m.get_lib_values(load_slews)
         model_data.update(port_data[0])
 
         # Only compare the delays
@@ -79,6 +83,9 @@ class model_delay_test(openram_test):
         else:
             self.assertTrue(False) # other techs fail
 
+        print('spice_delays', spice_delays)
+        print('model_delays', model_delays)
+
         # Check if no too many or too few results
         self.assertTrue(len(spice_delays.keys())==len(model_delays.keys()))
 

compiler/tests/21_ngspice_delay_extra_rows_test.py

@@ -51,7 +51,11 @@ class timing_sram_test(openram_test):
         import tech
         loads = [tech.spice["dff_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]
-        data, port_data = d.analyze(probe_address, probe_data, slews, loads)
+        load_slews = []
+        for slew in slews:
+            for load in loads:
+                load_slews.append((load, slew))
+        data, port_data = d.analyze(probe_address, probe_data, load_slews)
         #Combine info about port into all data
         data.update(port_data[0])
 

compiler/tests/21_ngspice_delay_global_test.py

@@ -58,7 +58,11 @@ class timing_sram_test(openram_test):
         import tech
         loads = [tech.spice["dff_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]
-        data, port_data = d.analyze(probe_address, probe_data, slews, loads)
+        load_slews = []
+        for slew in slews:
+            for load in loads:
+                load_slews.append((load, slew))
+        data, port_data = d.analyze(probe_address, probe_data, load_slews)
         #Combine info about port into all data
         data.update(port_data[0])
 

compiler/tests/21_ngspice_delay_test.py

@@ -50,7 +50,11 @@ class timing_sram_test(openram_test):
         import tech
         loads = [tech.spice["dff_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]
-        data, port_data = d.analyze(probe_address, probe_data, slews, loads)
+        load_slews = []
+        for slew in slews:
+            for load in loads:
+                load_slews.append((load, slew))
+        data, port_data = d.analyze(probe_address, probe_data, load_slews)
         #Combine info about port into all data
         data.update(port_data[0])
 

compiler/tests/21_xyce_delay_test.py

@@ -0,0 +1,106 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+class timing_sram_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        OPTS.spice_name="xyce"
+        OPTS.analytical_delay = False
+        OPTS.netlist_only = True
+
+        # This is a hack to reload the characterizer __init__ with the spice version
+        from importlib import reload
+        import characterizer
+        reload(characterizer)
+        from characterizer import delay
+        from sram_config import sram_config
+        c = sram_config(word_size=4,
+                        num_words=16,
+                        num_banks=1)
+        c.words_per_row=1
+        c.recompute_sizes()
+        debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
+        s = factory.create(module_type="sram", sram_config=c)
+
+        tempspice = OPTS.openram_temp + "temp.sp"
+        s.sp_write(tempspice)
+
+        probe_address = "1" * s.s.addr_size
+        probe_data = s.s.word_size - 1
+        debug.info(1, "Probe address {0} probe data bit {1}".format(probe_address, probe_data))
+
+        corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
+        d = delay(s.s, tempspice, corner)
+        import tech
+        loads = [tech.spice["dff_in_cap"]*4]
+        slews = [tech.spice["rise_time"]*2]
+        load_slews = []
+        for slew in slews:
+            for load in loads:
+                load_slews.append((load, slew))
+        data, port_data = d.analyze(probe_address, probe_data, load_slews)
+        # Combine info about port into all data
+        data.update(port_data[0])
+
+        if OPTS.tech_name == "freepdk45":
+            golden_data = {'delay_hl': [0.24042560000000002],
+                           'delay_lh': [0.24042560000000002],
+                           'disabled_read0_power': [0.8981647999999998],
+                           'disabled_read1_power': [0.9101543999999998],
+                           'disabled_write0_power': [0.9270382999999998],
+                           'disabled_write1_power': [0.9482969999999998],
+                           'leakage_power': 2.9792199999999998,
+                           'min_period': 0.938,
+                           'read0_power': [1.1107930999999998],
+                           'read1_power': [1.1143252999999997],
+                           'slew_hl': [0.2800772],
+                           'slew_lh': [0.2800772],
+                           'write0_power': [1.1667769],
+                           'write1_power': [1.0986076999999999]}
+        elif OPTS.tech_name == "scn4m_subm":
+            golden_data = {'delay_hl': [1.884186],
+                           'delay_lh': [1.884186],
+                           'disabled_read0_power': [20.86336],
+                           'disabled_read1_power': [22.10636],
+                           'disabled_write0_power': [22.62321],
+                           'disabled_write1_power': [23.316010000000002],
+                           'leakage_power': 13.351170000000002,
+                           'min_period': 7.188,
+                           'read0_power': [29.90159],
+                           'read1_power': [30.47858],
+                           'slew_hl': [2.042723],
+                           'slew_lh': [2.042723],
+                           'write0_power': [32.13199],
+                           'write1_power': [28.46703]}
+        else:
+            self.assertTrue(False) # other techs fail
+        # Check if no too many or too few results
+        self.assertTrue(len(data.keys())==len(golden_data.keys()))
+
+        self.assertTrue(self.check_golden_data(data,golden_data,0.25))
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/21_xyce_setuphold_test.py

@@ -0,0 +1,67 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+
+
+class timing_setup_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        OPTS.spice_name="Xyce"
+        OPTS.analytical_delay = False
+        OPTS.netlist_only = True
+
+        # This is a hack to reload the characterizer __init__ with the spice version
+        from importlib import reload
+        import characterizer
+        reload(characterizer)
+        from characterizer import setup_hold
+        import tech
+        slews = [tech.spice["rise_time"]*2]
+
+        corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
+        sh = setup_hold(corner)
+        data = sh.analyze(slews,slews)
+        if OPTS.tech_name == "freepdk45":
+            golden_data = {'hold_times_HL': [-0.0158691],
+                           'hold_times_LH': [-0.0158691],
+                           'setup_times_HL': [0.026855499999999997],
+                           'setup_times_LH': [0.032959]}
+        elif OPTS.tech_name == "scn4m_subm":
+            golden_data = {'hold_times_HL': [-0.0805664],
+                           'hold_times_LH': [-0.11718749999999999],
+                           'setup_times_HL': [0.16357419999999998],
+                           'setup_times_LH': [0.1757812]}
+        elif OPTS.tech_name == "sky130":
+            golden_data = {'hold_times_HL': [-0.05615234],
+                           'hold_times_LH': [-0.03173828],
+                           'setup_times_HL': [0.078125],
+                           'setup_times_LH': [0.1025391]}
+        else:
+            self.assertTrue(False) # other techs fail
+
+        # Check if no too many or too few results
+        self.assertTrue(len(data.keys())==len(golden_data.keys()))
+
+        self.assertTrue(self.check_golden_data(data,golden_data,0.25))
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/verify/magic.py

@@ -71,9 +71,12 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa
     global OPTS
 
     # Copy .magicrc file into the output directory
-    magic_file = OPTS.openram_tech + "tech/.magicrc"
+    magic_file = os.environ.get('OPENRAM_MAGICRC', None)
+    if not magic_file:
+        magic_file = OPTS.openram_tech + "tech/.magicrc"
+        
     if os.path.exists(magic_file):
-        shutil.copy(magic_file, output_path)
+        shutil.copy(magic_file, output_path + "/.magicrc")
     else:
         debug.warning("Could not locate .magicrc file: {}".format(magic_file))
     

technology/freepdk45/sim_data/fall_delay.csv

@@ -1,217 +0,0 @@
-num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,fall_delay
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technology/freepdk45/sim_data/fall_slew.csv

@@ -1,217 +0,0 @@
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technology/freepdk45/sim_data/read0_power.csv

@@ -1,217 +0,0 @@
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technology/freepdk45/sim_data/read1_power.csv

@@ -1,217 +0,0 @@
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technology/freepdk45/sim_data/rise_delay.csv

@@ -1,217 +0,0 @@
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technology/freepdk45/sim_data/rise_slew.csv

@@ -1,217 +0,0 @@
-num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,rise_slew
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technology/freepdk45/sim_data/sim_data.csv

@@ -0,0 +1,82 @@
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technology/freepdk45/sim_data/write0_power.csv

@@ -1,217 +0,0 @@
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technology/freepdk45/sim_data/write1_power.csv

@@ -1,217 +0,0 @@
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technology/scn4m_subm/sim_data/fall_delay.csv

@@ -1,244 +0,0 @@
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technology/scn4m_subm/sim_data/fall_slew.csv

@@ -1,244 +0,0 @@
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technology/scn4m_subm/sim_data/leakage_data.csv

@@ -1,244 +0,0 @@
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technology/scn4m_subm/sim_data/read0_power.csv

@@ -1,244 +0,0 @@
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technology/scn4m_subm/sim_data/read1_power.csv

@@ -1,244 +0,0 @@
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technology/scn4m_subm/sim_data/rise_delay.csv

@@ -1,244 +0,0 @@
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technology/scn4m_subm/sim_data/rise_slew.csv

@@ -1,244 +0,0 @@
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technology/scn4m_subm/sim_data/sim_data.csv

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technology/scn4m_subm/sim_data/write0_power.csv

@@ -1,244 +0,0 @@
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technology/scn4m_subm/sim_data/write1_power.csv

@@ -1,244 +0,0 @@
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