mirror of https://github.com/VLSIDA/OpenRAM.git
Specify two stage wl_en driver to prevent race condition
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@ -121,8 +121,10 @@ class control_logic(design.design):
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# max_fanout = max(self.num_rows, self.num_cols)
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# wl_en drives every row in the bank
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# MRG 9/3/2021: Ensure that this is two stages to prevent race conditions with the write driver
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size_list = [max(int(self.num_rows / 9), 1), max(int(self.num_rows / 3), 1)]
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self.wl_en_driver = factory.create(module_type="pdriver",
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fanout=self.num_rows,
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size_list=size_list,
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height=dff_height)
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self.add_mod(self.wl_en_driver)
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@ -348,7 +350,7 @@ class control_logic(design.design):
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row += 1
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control_center_y = self.wl_en_inst.uy() + self.m3_pitch
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# Delay chain always gets placed at row 4
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self.place_delay(4)
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height = self.delay_inst.uy()
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@ -391,7 +393,7 @@ class control_logic(design.design):
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def place_delay(self, row):
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""" Place the replica bitline """
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debug.check(row % 2 == 0, "Must place delay chain at even row for supply alignment.")
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# It is flipped on X axis
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y_off = row * self.and2.height + self.delay_chain.height
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