mirror of https://github.com/VLSIDA/OpenRAM.git
extend input rail
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@ -122,7 +122,7 @@ class hierarchical_predecode(design.design):
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self.input_rails = self.create_vertical_bus(layer=self.bus_layer,
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offset=offset,
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names=input_names,
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length=self.height - 2 * self.bus_pitch,
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length=self.height - self.bus_pitch,
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pitch=self.bus_pitch)
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invert_names = ["Abar_{}".format(x) for x in range(self.number_of_inputs)]
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@ -132,7 +132,7 @@ class hierarchical_predecode(design.design):
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self.decode_rails = self.create_vertical_bus(layer=self.bus_layer,
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offset=offset,
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names=decode_names,
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length=self.height - 2 * self.bus_pitch,
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length=self.height - self.bus_pitch,
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pitch=self.bus_pitch)
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def create_input_inverters(self):
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