mirror of https://github.com/VLSIDA/OpenRAM.git
place decoder rail contacts at least m2 min spacing away
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@ -692,7 +692,7 @@ class hierarchical_decoder(design.design):
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drc_error = 0
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for and_input in self.predecode_bus_rail_pos:
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if and_input.x == rail_pos.x:
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if (abs(y_offset - and_input.y) < total_buffer_space) or (abs(y_offset - and_input.y) < via.height):
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if (abs(y_offset - and_input.y) < total_buffer_space) or (abs(y_offset - and_input.y) < via.height) or (abs(y_offset - drc("minwidth_{}".format(cur_layer)) - pin_pos.y - via.height/2) < drc("{0}_to_{0}".format(cur_layer)) ):
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drc_error = 1
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if drc_error == 0:
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break
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