mirror of https://github.com/VLSIDA/OpenRAM.git
remove hierarchical decoder vertial m1 above pins
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@ -662,9 +662,9 @@ class hierarchical_decoder(design.design):
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mid_point2 = vector(x_offset, y_offset)
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rail_pos = vector(self.predecode_bus[rail_name].cx(), mid_point2.y)
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self.add_path(self.output_layer, [pin_pos, mid_point1, mid_point2, rail_pos])
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if layer_props.hierarchical_decoder.vertical_supply:
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above_rail = vector(self.predecode_bus[rail_name].cx(), mid_point2.y + (self.cell_height / 2))
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self.add_path(self.bus_layer, [rail_pos, above_rail], width=self.li_width + self.m1_enclose_mcon * 2)
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#if layer_props.hierarchical_decoder.vertical_supply:
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# above_rail = vector(self.predecode_bus[rail_name].cx(), mid_point2.y + (self.cell_height / 2))
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# self.add_path(self.bus_layer, [rail_pos, above_rail], width=self.li_width + self.m1_enclose_mcon * 2)
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# pin_pos = pin.center()
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# rail_pos = vector(self.predecode_bus[rail_name].cx(), pin_pos.y)
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