mirror of https://github.com/VLSIDA/OpenRAM.git
Don't make internal bus pins because magic will extract ports
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@ -495,11 +495,11 @@ class hierarchical_decoder(design.design):
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if (self.num_inputs >= 4):
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# This leaves an offset for the predecoder output jogs
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input_bus_names = ["predecode_{0}".format(i) for i in range(self.total_number_of_predecoder_outputs)]
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self.predecode_bus = self.create_vertical_pin_bus(layer=self.bus_layer,
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pitch=self.bus_pitch,
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offset=vector(self.bus_pitch, 0),
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names=input_bus_names,
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length=self.height)
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self.predecode_bus = self.create_vertical_bus(layer=self.bus_layer,
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pitch=self.bus_pitch,
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offset=vector(self.bus_pitch, 0),
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names=input_bus_names,
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length=self.height)
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self.route_bus_to_decoder()
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self.route_predecodes_to_bus()
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