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OpenRAM
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Merge branch 'dev' into laptop_checkpoint

This commit is contained in:
Jesse Cirimelli-Low 2021-06-09 18:25:45 -07:00
parent 10f561648f a1cb20878d
commit 247a388ab5
11 changed files with 52 additions and 38 deletions
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10
compiler/base/hierarchy_layout.py
View File

@ -1413,7 +1413,7 @@ class layout():
[ll, ur] = bbox
# Possibly inflate the bbox
nwell_offset = vector(self.nwell_width, self.nwell_width)
nwell_offset = vector(2 * self.nwell_width, 2 * self.nwell_width)
ll -= nwell_offset.scale(inflate, inflate)
ur += nwell_offset.scale(inflate, inflate)
@ -1452,7 +1452,7 @@ class layout():
to_layer="m1",
offset=loc)
else:
self.add_power_pin(name="gnd",
self.add_power_pin(name="vdd",
loc=loc,
start_layer="li")
count += 1
@ -1472,7 +1472,7 @@ class layout():
to_layer="m1",
offset=loc)
else:
self.add_power_pin(name="gnd",
self.add_power_pin(name="vdd",
loc=loc,
start_layer="li")
count += 1
@ -1492,7 +1492,7 @@ class layout():
to_layer="m2",
offset=loc)
else:
self.add_power_pin(name="gnd",
self.add_power_pin(name="vdd",
loc=loc,
start_layer="li")
count += 1
@ -1512,7 +1512,7 @@ class layout():
to_layer="m2",
offset=loc)
else:
self.add_power_pin(name="gnd",
self.add_power_pin(name="vdd",
loc=loc,
start_layer="li")
count += 1

4
compiler/characterizer/__init__.py
View File

@ -24,7 +24,7 @@ debug.info(1, "Initializing characterizer...")
OPTS.spice_exe = ""
if not OPTS.analytical_delay:
if OPTS.spice_name != "":
if OPTS.spice_name:
# Capitalize Xyce
if OPTS.spice_name == "xyce":
OPTS.spice_name = "Xyce"
@ -45,7 +45,7 @@ if not OPTS.analytical_delay:
if OPTS.spice_name == "ngspice":
os.environ["NGSPICE_INPUT_DIR"] = "{0}".format(OPTS.openram_temp)
if OPTS.spice_exe == "":
if not OPTS.spice_exe:
debug.error("No recognizable spice version found. Unable to perform characterization.", 1)
else:
debug.info(1, "Finding spice simulator: {} ({})".format(OPTS.spice_name, OPTS.spice_exe))

4
compiler/characterizer/stimuli.py
View File

@ -276,8 +276,8 @@ class stimuli():
self.sf.write(".OPTIONS MEASURE MEASFAIL=1\n")
self.sf.write(".OPTIONS LINSOL type=klu\n")
self.sf.write(".TRAN {0}p {1}n\n".format(timestep, end_time))
else:
debug.error("Unkown spice simulator {}".format(OPTS.spice_name))
elif OPTS.spice_name:
debug.error("Unkown spice simulator {}".format(OPTS.spice_name), -1)
# create plots for all signals
if not OPTS.use_pex: # Don't save all for extracted simulations

2
compiler/modules/dff_buf.py
View File

@ -109,7 +109,7 @@ class dff_buf(design.design):
except AttributeError:
pass
well_spacing += self.well_extend_active
well_spacing += 2 * self.well_extend_active
self.inv1_inst.place(vector(self.dff_inst.rx() + well_spacing, 0))

10
compiler/options.py
View File

@ -122,13 +122,13 @@ class options(optparse.Values):
# Tool options
###################
# Variable to select the variant of spice
spice_name = ""
spice_name = None
# The spice executable being used which is derived from the user PATH.
spice_exe = ""
spice_exe = None
# Variable to select the variant of drc, lvs, pex
drc_name = ""
lvs_name = ""
pex_name = ""
drc_name = None
lvs_name = None
pex_name = None
# The DRC/LVS/PEX executable being used
# which is derived from the user PATH.
drc_exe = None

4
compiler/router/router.py
View File

@ -881,7 +881,7 @@ class router(router_tech):
"""
pg = pin_group(name, [], self)
# Offset two spaces inside and one between the rings
if name == "vdd":
if name == "gnd":
offset = width + 2 * space
else:
offset = space
@ -911,7 +911,7 @@ class router(router_tech):
pg = pin_group(name, [], self)
# Offset two spaces inside and one between the rings
# Units are in routing grids
if name == "vdd":
if name == "gnd":
offset = width + 2 * space
else:
offset = space

40
compiler/sram/sram_1bank.py
View File

@ -385,6 +385,7 @@ class sram_1bank(sram_base):
if len(route_map) > 0:
# This layer stack must be different than the data dff layer stack
layer_stack = self.m1_stack
if port == 0:
@ -394,11 +395,11 @@ class sram_1bank(sram_base):
offset=offset,
layer_stack=layer_stack,
parent=self)
# This causes problem in magic since it sometimes cannot extract connectivity of isntances
# This causes problem in magic since it sometimes cannot extract connectivity of instances
# with no active devices.
self.add_inst(cr.name, cr)
self.connect_inst([])
#self.add_flat_inst(cr.name, cr)
# self.add_flat_inst(cr.name, cr)
else:
offset = vector(0,
self.bank.height + self.m3_pitch)
@ -406,11 +407,11 @@ class sram_1bank(sram_base):
offset=offset,
layer_stack=layer_stack,
parent=self)
# This causes problem in magic since it sometimes cannot extract connectivity of isntances
# This causes problem in magic since it sometimes cannot extract connectivity of instances
# with no active devices.
self.add_inst(cr.name, cr)
self.connect_inst([])
#self.add_flat_inst(cr.name, cr)
# self.add_flat_inst(cr.name, cr)
def route_data_dffs(self, port, add_routes):
route_map = []
@ -441,40 +442,49 @@ class sram_1bank(sram_base):
if len(route_map) > 0:
# The write masks will have blockages on M1
# if self.num_wmasks > 0 and port in self.write_ports:
# layer_stack = self.m3_stack
# else:
# layer_stack = self.m1_stack
# This layer stack must be different than the column addr dff layer stack
layer_stack = self.m3_stack
if port == 0:
# This is relative to the bank at 0,0 or the s_en which is routed on M3 also
if "s_en" in self.control_logic_insts[port].mod.pin_map:
y_bottom = min(0, self.control_logic_insts[port].get_pin("s_en").by())
else:
y_bottom = 0
y_offset = y_bottom - self.data_bus_size[port] + 2 * self.m3_pitch
offset = vector(self.control_logic_insts[port].rx() + self.dff.width,
- self.data_bus_size[port] + 2 * self.m3_pitch)
y_offset)
cr = channel_route(netlist=route_map,
offset=offset,
layer_stack=layer_stack,
parent=self)
if add_routes:
# This causes problem in magic since it sometimes cannot extract connectivity of isntances
# This causes problem in magic since it sometimes cannot extract connectivity of instances
# with no active devices.
self.add_inst(cr.name, cr)
self.connect_inst([])
#self.add_flat_inst(cr.name, cr)
# self.add_flat_inst(cr.name, cr)
else:
self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap
else:
if "s_en" in self.control_logic_insts[port].mod.pin_map:
y_top = max(self.bank.height, self.control_logic_insts[port].get_pin("s_en").uy())
else:
y_top = self.bank.height
y_offset = y_top + self.m3_pitch
offset = vector(0,
self.bank.height + self.m3_pitch)
y_offset)
cr = channel_route(netlist=route_map,
offset=offset,
layer_stack=layer_stack,
parent=self)
if add_routes:
# This causes problem in magic since it sometimes cannot extract connectivity of isntances
# This causes problem in magic since it sometimes cannot extract connectivity of instances
# with no active devices.
self.add_inst(cr.name, cr)
self.connect_inst([])
#self.add_flat_inst(cr.name, cr)
# self.add_flat_inst(cr.name, cr)
else:
self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap

4
compiler/tests/21_hspice_setuphold_test.py
View File

@ -45,8 +45,8 @@ class timing_setup_test(openram_test):
'setup_times_HL': [0.16357419999999998],
'setup_times_LH': [0.1757812]}
elif OPTS.tech_name == "sky130":
golden_data = {'hold_times_HL': [-0.05615234],
'hold_times_LH': [-0.03173828],
golden_data = {'hold_times_HL': [-0.03173828],
'hold_times_LH': [-0.05615234],
'setup_times_HL': [0.078125],
'setup_times_LH': [0.1025391]}
else:

4
compiler/tests/21_ngspice_setuphold_test.py
View File

@ -45,8 +45,8 @@ class timing_setup_test(openram_test):
'setup_times_HL': [0.1757812],
'setup_times_LH': [0.1879883]}
elif OPTS.tech_name == "sky130":
golden_data = {'hold_times_HL': [-0.05615234],
'hold_times_LH': [-0.03173828],
golden_data = {'hold_times_HL': [-0.03173828],
'hold_times_LH': [-0.05615234],
'setup_times_HL': [0.078125],
'setup_times_LH': [0.1025391]}
else:

4
compiler/tests/21_xyce_setuphold_test.py
View File

@ -45,8 +45,8 @@ class timing_setup_test(openram_test):
'setup_times_HL': [0.16357419999999998],
'setup_times_LH': [0.1757812]}
elif OPTS.tech_name == "sky130":
golden_data = {'hold_times_HL': [-0.05615234],
'hold_times_LH': [-0.03173828],
golden_data = {'hold_times_HL': [-0.03173828],
'hold_times_LH': [-0.05615234],
'setup_times_HL': [0.078125],
'setup_times_LH': [0.1025391]}
else:

4
compiler/verify/magic.py
View File

@ -180,6 +180,10 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa
f.write('puts "Finished drc check"\n')
f.write("drc catchup\n")
f.write('puts "Finished drc catchup"\n')
# This is needed instead of drc count total because it displays
# some errors that are not "DRC" errors.
# f.write("puts -nonewline \"Total DRC errors found: \"\n")
# f.write("puts stdout [drc listall count total]\n")
f.write("drc count total\n")
f.write("quit -noprompt\n")
f.write("EOF\n")