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push bias pins to top level power routing

This commit is contained in:
Jesse Cirimelli-Low 2021-05-28 13:41:58 -07:00
parent f9eae3fb80
commit 1a894a99dd
1 changed files with 3 additions and 3 deletions
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6
compiler/modules/bank.py
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@ -625,9 +625,9 @@ class bank(design.design):
self.copy_power_pins(inst, "vdd", add_vias=False)
self.copy_power_pins(inst, "gnd", add_vias=False)
#if 'vpb' in self.bitcell_array_inst.mod.pins and 'vnb' in self.bitcell_array_inst.mod.pins:
# for pin_name, supply_name in zip(['vpb','vnb'],['vdd','gnd']):
# self.copy_power_pins(self.bitcell_array_inst, pin_name, new_name=supply_name)
if 'vpb' in self.bitcell_array_inst.mod.pins and 'vnb' in self.bitcell_array_inst.mod.pins:
for pin_name, supply_name in zip(['vpb','vnb'],['vdd','gnd']):
self.copy_power_pins(self.bitcell_array_inst, pin_name, new_name=supply_name)
# If we use the pinvbuf as the decoder, we need to add power pins.
# Other decoders already have them.