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OpenRAM
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2813 Commits

Author SHA1 Message Date
Hunter Nichols b201fa4bca Fixed path measurement in delay 2020-11-19 22:53:38 -08:00
mrg b77f168270 Fix original pin name bug in bitcell too. 2020-11-19 15:12:02 -08:00
mrg 033111a5f3 Default to no hierarchical word lines. 2020-11-19 10:48:35 -08:00
mrg 35c162acbd Use internal pin names in path names for signal traces. 2020-11-19 08:45:09 -08:00
mrg fbed738b4a Merge multiple cell_name fix. 2020-11-18 16:27:28 -08:00
mrg 8c72d3f2e7 PEP8 and small fix 2020-11-18 14:01:25 -08:00
mrg 8507881ea8 Merge branch 's8_single_port' into dev 2020-11-18 13:59:43 -08:00
jcirimel 50a0b88ef8 fix typo 2020-11-18 11:02:40 -08:00
jcirimel 520b496611 check for cell prop names list 2020-11-18 10:47:05 -08:00
mrg 6cfa20731c Consistent naming in example configs 2020-11-18 09:59:38 -08:00
mrg 305b546ad5 PEP8 cleanup 2020-11-17 16:56:00 -08:00
mrg 02c1fac3b8 Remove partial Verilog output 2020-11-17 16:51:08 -08:00
Hunter Nichols 7a0f5e15db Added polarity checks in modules to allow to make it easier to get spice rise/fall. Path measures not failing now but should be changed later. 2020-11-17 15:05:07 -08:00
Hunter Nichols 35e1a523cc Changed named on delay chain sizing variable. Automatic sizing default is False. 2020-11-17 14:29:01 -08:00
Hunter Nichols df4c2bad1f Disabled debug measures that are WIP. 2020-11-17 13:30:18 -08:00
Hunter Nichols ac425643a0 Merge branch 'dev' into characterizer_bug_fixes 2020-11-17 13:22:56 -08:00
Hunter Nichols eaf285639a Added debug measurements along main delay paths in SRAM. WIP. 2020-11-17 12:43:17 -08:00
mrg baae28194b Add custom cell custom port order code. Update setup/hold to use it. 2020-11-17 11:12:59 -08:00
mrg 80333ffacb Fix setup/hold characterization to use custom cell and pin names/orders. 2020-11-17 09:44:03 -08:00
mrg 902b92223f Small fix for finding pin names in timing graph. 2020-11-16 13:57:31 -08:00
mrg 86799ae3ff Small bug fixes related to new name mapping. 2020-11-16 13:42:42 -08:00
mrg 1d729e8f02 Move pin name mapping to layout class. 2020-11-16 11:04:03 -08:00
mrg 93e94e26ec Get vdd/gnd from properties if it is defined. 2020-11-16 10:14:37 -08:00
mrg 7512aa6e70 Skip test 50 which is too slow 2020-11-16 08:59:25 -08:00
mrg e4bc2c4914 Update property settings with getters/setters 2020-11-14 08:08:42 -08:00
mrg 2f994b8c0a Change custom cells to use set_ports setter 2020-11-14 07:15:27 -08:00
mrg 1624d50ca9 Fix props bug again. 2020-11-13 20:35:19 -08:00
mrg e9420d57c2 Fix missing attributes 2020-11-13 19:04:26 -08:00
mrg b4342ac527 More cleanup 2020-11-13 17:29:20 -08:00
mrg a2b17a271c Port type order generated on the fly 2020-11-13 16:41:02 -08:00
mrg 01d191da40 clk_pin is redundant in DFFs 2020-11-13 16:23:27 -08:00
mrg 620e271562 Fix various typos and errors 2020-11-13 16:04:07 -08:00
mrg 8021430122 Fix pbitcell erros 2020-11-13 15:55:55 -08:00
mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 2020-11-13 10:07:40 -08:00
mrg 3567a3e913 Remove 1rw_1r 2020-11-13 08:10:16 -08:00
mrg cf63499e76 Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
mrg 198c0faf85 Remove special s8 6t names 2020-11-13 07:45:31 -08:00
mrg 662d4ea724 Merge remote-tracking branch 'private/drclvs' into dev 2020-11-12 16:01:07 -08:00
mrg e6a7ecae84 Fix missing default path in pex 2020-11-12 14:43:57 -08:00
mrg 9eeab14639 Add comment before pininfo 2020-11-12 14:33:42 -08:00
mrg bdda7c4f5f Add bl/br pins to dummy array 2020-11-12 12:38:09 -08:00
mrg 190234df58 Add PININFO to outputs too 2020-11-12 12:12:53 -08:00
mrg 63941a10e1 Add None as sp_file parameter to local_drc_check 2020-11-12 10:01:38 -08:00
mrg d4c4658c77 Clean up invalid routing layer error message 2020-11-12 09:43:08 -08:00
mrg d3cb22c8c1 Fix pin vs module names issue #26 2020-11-12 09:33:48 -08:00
mrg 537e862d48 Add -full to LVS script 2020-11-10 20:38:41 -08:00
mrg 03dad01e4c Use readspice to define ports from sp netlist in Magic extract. 2020-11-10 17:06:24 -08:00
mrg 31ae56ff39 Simplify to a single DRC/LVS library test. 2020-11-10 16:45:00 -08:00
Hunter Nichols 84ba5c55d1 Merged with dev 2020-11-10 15:47:56 -08:00
mrg 56c2222c2b Temp comment Magic GDS filter code. 2020-11-10 13:37:18 -08:00
mrg 57e708a6e1 Add 200 cycles. Can be commented out or run for shorter. 2020-11-09 15:20:36 -08:00
mrg 2c203530ad Merge branch 'drclvs' into dev 2020-11-09 14:36:36 -08:00
mrg 0ba2feee53 Fix errors in new run_sim calls and corners 2020-11-09 13:59:46 -08:00
mrg e31cbeaa6f Don't check for file to determine if it is included. 2020-11-09 12:11:47 -08:00
mrg 532492d5ae Output functional stimulus to output directory. 2020-11-09 12:00:25 -08:00
mrg 31d21e169f Skip LEF test as correct output keeps changing. 2020-11-09 11:14:55 -08:00
mrg 10542d6cc3 Output DRC and LVS run files to output directory. 2020-11-09 11:12:31 -08:00
mrg 66633a843b Add PDK layer names to tech file 2020-11-09 09:10:43 -08:00
mrg 2da9c307db Disable 4x16 decoder test for now 2020-11-06 13:50:04 -08:00
mrg 147649e142 Why was single port decoder test a dual port? 2020-11-06 12:21:30 -08:00
mrg 493c9125f1 Read different modules overrides for different num ports 2020-11-06 11:09:50 -08:00
mrg 8be1436d51 Use OPTS.bitcell everywhere 2020-11-05 16:55:08 -08:00
mrg 18d2987805 Cleanup 2020-11-05 16:30:15 -08:00
mrg a40716dd48 Cleanup imports 2020-11-05 14:32:08 -08:00
mrg 0118b73eec Cleanup imports 2020-11-05 14:31:53 -08:00
mrg 681b3a91aa Drop to debug in debug module when -d 2020-11-05 13:20:54 -08:00
mrg 2c76a2680f Adjust openram options. 
Remove option -d (dontpurge) and replace with keeptemp
Add option -d (debug) to drop into pdb.
Add option -k (--keeptemp) to keep temp files
 2020-11-05 13:12:26 -08:00
mrg a52aac5f31 Add gds flatten option for Magic 2020-11-05 13:12:08 -08:00
mrg ce7be7466f Model as subckt for Magic too 2020-11-05 13:11:36 -08:00
mrg b160c4a35d Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-11-04 14:31:42 -08:00
mrg 9a38f7a5f4 Enable gds readonly in Magic DRC/LVS 2020-11-04 10:50:53 -08:00
mrg fb0b285652 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-11-04 10:40:20 -08:00
mrg 6e12d4d46c Skip tri gate array test 2020-11-04 06:57:51 -08:00
Matt Guthaus 844b850b74 Fix typo in 1w_1r bitcell 2020-11-03 17:14:45 -08:00
mrg 3315fe32ba Improve nominal corner message 2020-11-03 16:49:49 -08:00
mrg 45cdecdea9 Improve error message about missing DRC/LVS tools. 2020-11-03 15:47:04 -08:00
mrg 6335bc3784 Do not drop to pdb shell when verbose 2020-11-03 15:46:46 -08:00
mrg 29f4ee492b Fix missing imports in replica bitcells. 2020-11-03 15:24:44 -08:00
mrg 2f12c77668 Create single port memory config examples. 2020-11-03 14:42:56 -08:00
mrg fb9956fe96 Fix missing include 2020-11-03 13:50:45 -08:00
mrg d209e8d9a3 Disable perimeter pins for now 2020-11-03 13:35:34 -08:00
mrg 1de545fc8e Fix row and col cap custom names by adding default. 2020-11-03 13:32:15 -08:00
mrg 29ac541b28 Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
mrg a128e0501e Use cell_name in col and row caps too. 2020-11-03 12:10:18 -08:00
mrg 1890385be1 Use custom cells when needed. 2020-11-03 11:58:25 -08:00
mrg 87419bd640 Fix bitcell and pbitcell with different cell names 2020-11-03 11:30:40 -08:00
mrg cb3e9517bb Use cell_properties to override cell names 2020-11-03 07:06:01 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg 8c4584daa1 Missing import fix. 2020-11-03 06:09:42 -08:00
mrg aec5865d71 Fix base class error 2020-11-02 17:41:14 -08:00
mrg f9787eb878 Use bitcell_base for all bitcells. Fix missing setup_bitcell call 2020-11-02 17:00:15 -08:00
mrg fa89b73ef8 PR from mithro + other changable GDS file names 2020-11-02 16:00:16 -08:00
mrg 1caecf5a69 Undo version and traceback 2020-11-02 10:44:49 -08:00
Tim 'mithro' Ansell bb164d915d Allow overriding the cell size layer name. 2020-11-02 10:03:52 -08:00
Tim 'mithro' Ansell 232f754c73 Adding traceback printing to tech file import. 2020-11-02 09:52:00 -08:00
Tim 'mithro' Ansell 95d77119c7 Add caches to GDS related functions in utils.py 
* Cache the GDS reader.
 * Cache the properties (size / pins / etc) measured from the GDS files.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2020-11-02 09:52:00 -08:00
Tim 'mithro' Ansell 6514bcb4c1 Use default bitcell name if one isn't provided. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2020-11-02 09:52:00 -08:00
Tim 'mithro' Ansell 5c1250191c Fixup the bitcell.py to make subclassing work. 
Read in the GDS properties inside the __init__ method.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2020-11-02 09:51:54 -08:00
mrg 029f655c1b Merge remote-tracking branch 'private/dev' into dev 2020-10-30 16:01:38 -07:00
mrg bd9bac6635 Fixed nominal_corner_only parameter. 2020-10-30 15:52:07 -07:00
mrg da9ed5494c Merge remote-tracking branch 'private/dev' into dev 2020-10-29 17:46:33 -07:00
mrg 857f5cb136 Fix copy pasta: decoder to predecode 2020-10-28 15:46:10 -07:00
mrg ae0f4fe682 Fix spice model bin parameter error 2020-10-28 10:39:54 -07:00
mrg 00cb8a28d9 Fix supply layer query 2020-10-28 10:36:13 -07:00
mrg f6c5f48b4c Default channel route is true 2020-10-28 10:31:05 -07:00
mrg acfec369d6 Add ptx cell properties 2020-10-28 09:54:15 -07:00
mrg 25495f3d94 getattr for bank parameters 2020-10-28 09:21:36 -07:00
mrg 611a4155b9 Add initial custom layer properties. 2020-10-27 15:11:04 -07:00
mrg 5bff641c0a Multiport constants can't be static 2020-10-27 09:28:21 -07:00
mrg 575f504e4b Remove static method call 2020-10-27 09:26:40 -07:00
mrg 07ef43eaf8 Convert design class data to static 2020-10-27 09:23:11 -07:00
mrg f23fe07893 Add custom layers without defaults 2020-10-26 16:37:00 -07:00
mrg dc991cbcab Use pin of pgate to figure out supply layer. 2020-10-26 15:54:16 -07:00
mrg 38ba5fc10d Use pin of pgate to figure out supply layer. 2020-10-26 15:53:22 -07:00
mrg b45a7902c0 PEP8 cleanup 2020-10-26 13:13:38 -07:00
mrg b20036a867 Merge remote-tracking branch 'private/dev' into dev 2020-10-25 16:25:21 -07:00
mrg cae41c63f0 Merge branch 'spmodels' into dev 2020-10-23 16:23:12 -07:00
mrg b4ebbdd5df Require either device models or device library. Remove sky130 flag. 2020-10-23 14:07:26 -07:00
mrg f97ae723f0 Remove extraneous config files. 2020-10-23 13:56:27 -07:00
mrg cbf9c48504 Names in skiptests changed. Reduce grid router verbosity. 2020-10-23 09:22:59 -07:00
mrg dcd29214bc Temp fix to use old device names during Calibre LVS. 2020-10-21 17:05:48 -07:00
Hunter Nichols 12a8531248 Allowed for OPTS writeback of words_per_row if automatically generated during generation. 2020-10-21 03:02:39 -07:00
mrg 3d5c73709b Merge branch 'dev' into spmodels 2020-10-19 14:49:07 -07:00
mrg 9c6af8937d Merge remote-tracking branch 'private/dev' into dev 2020-10-16 17:00:05 -07:00
mrg 7da3653ce5 Only output wmask to lib file in w or rw ports. 2020-10-16 16:59:51 -07:00
mrg 5268ec547b Merge remote-tracking branch 'private/dev' into dev 2020-10-16 16:51:50 -07:00
mrg 3295a813d6 Don't use single slew for nominal corner 2020-10-16 16:51:28 -07:00
mrg db1bcd0774 Merge remote-tracking branch 'private/dev' into dev 2020-10-16 13:54:43 -07:00
mrg 35c91168f7 Add load/slew scale option to config files 2020-10-16 13:52:36 -07:00
mrg 804814d18d Add bitlines to dummy modules 2020-10-16 13:43:56 -07:00
mrg 20be7caf98 Make conditional wl and bl for dummy rows/cols. 2020-10-15 13:56:37 -07:00
mrg af40f3077c Change sky130 device cards to start with X 2020-10-15 13:56:10 -07:00
mrg b4f293b311 Merge branch 'dev' into spmodels 2020-10-15 09:46:16 -07:00
mrg 6a1f12b62d Refactored to utilize OOP 2020-10-13 11:07:31 -07:00
mrg 68d74737f7 Different bitcell and array supply pins 2020-10-13 07:41:21 -07:00
mrg 555e776712 Merge branch 'dev' into spmodels 2020-10-13 06:41:26 -07:00
jcirimel 05667d784f move sky130 specific stuff to tech module lib 2020-10-13 04:48:10 -07:00
mrg fcb7f42e48 Remove split_wl 2020-10-12 17:27:20 -07:00
mrg ca2ce8b070 Default bitcell opt1 2020-10-12 17:08:32 -07:00
mrg 6b56c833df Merge branch 'dev' into spmodels 2020-10-12 15:51:40 -07:00
mrg ef310970bf Use new Google PDK lib 2020-10-12 15:46:11 -07:00
mrg a5e8818014 OpenRAM v1.1.7 
Global and local wordlines.
Many updates all around.
 2020-10-12 09:02:38 -07:00
mrg c3d6be27be Fix argument name bug for remove wordlines 2020-10-08 16:58:38 -07:00
mrg 3648401e67 Remove another boundary subcell 2020-10-08 16:58:19 -07:00
mrg 8d5db50062 Fix missing update for left RBL offset 2020-10-08 16:40:53 -07:00
mrg b0b15e8151 Fix indent bug that failed to create rbl wl pin labels. 2020-10-08 15:28:01 -07:00
mrg 01fe02bd90 Fixes to replica bitline array. 
Copy pasta error for right dummy column offset.
Put end_caps in try/except block.
PEP 8 formatting
 2020-10-08 14:53:44 -07:00
mrg 03e1b9c50d Clean up custom cells 2020-10-08 14:22:09 -07:00
mrg 8a9bf2d4f0 Remove hardcoded structure 2020-10-08 14:07:46 -07:00
mrg 3c2e8754e0 Search all shapes for boundary rather than specify structure 2020-10-08 14:04:19 -07:00